Low Latency GNN Accelerator for Quantum Error Correction

Alessio Cicero; Luigi Altamura; Mats Granath; Moritz Lange; Pedro Trancoso

REVIEW 3 major objections 5 minor 1 cited by

A hardware-co-designed Graph Neural Network decoder on FPGA beats matching-based surface-code decoding at one-microsecond real-time latency while lowering logical error rates.

Reviewed by Pith at T0; open to challenge. T0 means a machine referee read the full paper against a public rubric. the ladder, T0–T4 →

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T0 review · grok-4.5

2026-07-13 20:22 UTC pith:INXPENX7

load-bearing objection Solid FPGA co-design that beats MWPM on LER under 1 µs budgets at d≤7, but the accuracy edge and latency targets are unproven beyond that narrow regime. the 3 major comments →

arxiv 2603.22149 v3 pith:INXPENX7 submitted 2026-03-23 quant-ph cs.AR

Low Latency GNN Accelerator for Quantum Error Correction

Alessio Cicero , Luigi Altamura , Moritz Lange , Mats Granath , Pedro Trancoso This is my paper

classification quant-ph cs.AR PACS 03.67.Pp

keywords quantum error correctionsurface codegraph neural networkreal-time decodingFPGA acceleratorminimum-weight perfect matchingsyndrome decodinghardware-software co-design

verification ladder T0 review T1 audit T2 compute T3 formal T4 reserved

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

Fault-tolerant quantum computers need error decoders that keep up with continuous syndrome measurements, or the decoder itself becomes the bottleneck. Most real-time systems use minimum-weight perfect matching, which is fast but leaves higher residual logical errors than heavier neural methods. This paper shows that a high-accuracy Graph Neural Network decoder can be made practical for real time by hardware-guided pruning and retraining, input-graph filtering, and post-training quantization, then mapped to a custom FPGA accelerator. Evaluated on surface codes up to distance 7 under circuit-level noise at physical error rate 0.001, the design outperforms matching in accuracy for both average-latency and strict worst-case one-cycle targets, cutting logical error rate by about 40 percent at 1 µs average latency and by 13 percent under a hard 1 µs deadline. A reader who wants useful logical qubits soon cares because decoder accuracy and latency jointly set how soon error correction can keep a machine running.

Core claim

Through algorithm-hardware co-design, a Graph Neural Network surface-code decoder can be pruned, quantized, and accelerated on FPGA so that it meets one-syndrome-cycle (about 1 µs) latency targets while still reducing logical error rate relative to minimum-weight perfect matching on codes up to distance 7 under circuit-level noise.

What carries the argument

Hardware-guided pruning and retraining that yield two lean GNN models (about 3.1× and 6.5× fewer parameters) aimed at average and worst-case one-cycle latency, plus input-graph filtering, post-training quantization, and a dedicated FPGA inference architecture for real-time decoding.

Load-bearing premise

The accuracy and latency gains measured only on simulated surface codes up to distance 7 at a single physical error rate will still hold for the larger codes and noise conditions needed for useful fault tolerance.

What would settle it

Run the same pruned and quantized FPGA GNN decoder against minimum-weight perfect matching on surface codes of distance 9 or higher (and at other physical error rates) under the same circuit-level noise model; if the logical-error-rate advantage disappears within the 1 µs budget, the central real-time claim does not transfer.

Watch this falsifier — get emailed when new claim-graph text bears on it.

If this is right

Real-time GNN decoding can be provisioned on FPGA without giving up the accuracy edge over matching at distances up to 7.
Separate average-latency and strict max-latency models let designers trade model size for guaranteed one-cycle decoding.
Graph filtering and quantization reduce hardware cost enough that the heavier neural decoder becomes deployable.
Tens-of-percent logical-error-rate reductions become available inside the roughly 1 µs syndrome-cycle window used by many superconducting platforms.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

If the accuracy gap survives larger distances, GNN accelerators could relax the physical error rate or code distance required for a target logical error rate.
The same pruning-plus-filtering-plus-quantization recipe may transfer to other graph-based quantum error-correcting codes beyond the surface code.
Strict max-latency co-design points toward hardware sized for guaranteed real-time operation rather than only average throughput.
Limited evaluation at one noise rate and d≤7 leaves open whether the reported advantage holds in the noise regimes of near-term devices.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit.

Desk Editor's Note

Solid FPGA co-design that beats MWPM on LER under 1 µs budgets at d≤7, but the accuracy edge and latency targets are unproven beyond that narrow regime.

read the letter

The one thing worth knowing is that this is a real algorithm-hardware co-design result, not just another neural decoder paper. They take a high-accuracy GNN, prune and retrain it under hardware guidance into two models (3.1× and 6.5× fewer parameters) that respectively hit average and worst-case latency of one syndrome cycle, then add input-graph filtering and post-training quantization, and map the whole thing onto an FPGA. On surface codes up to distance 7 under circuit-level noise at p=10^{-3}, the resulting decoder reduces logical error rate 40% versus MWPM at 1 µs average latency and 13% under a hard 1 µs deadline. Those numbers are concrete and the targets are the right ones for real-time QEC control.

What is new is the co-design loop itself: pruning guided by the latency budget rather than accuracy alone, the dual-model strategy (average vs max), and the FPGA datapath that makes the pruned GNN actually fit the cycle time. The paper does this cleanly and reports the accuracy-latency trade-off points that matter. Circularity is low; they measure against an external MWPM baseline on simulated syndromes.

The soft spot is exactly the one the stress-test flags and it is not minor: everything is shown only at d≤7 and a single physical error rate. Nothing demonstrates that the pruned/quantized models keep their edge (or even stay competitive) as distance grows into the regime needed for useful fault tolerance, or under different noise. If the GNN advantage shrinks with d while matching scales more gracefully, both the LER claims and the justification for the 1 µs hardware targets fail to transfer. Baseline fairness and error bars are also hard to audit from the corrupted extract, so those need checking. That said, the central empirical claim as scoped is still useful.

This is for people building the classical control stack for FTQC, especially anyone already looking at neural or FPGA decoders. It is not foundational theory. It deserves a serious referee; the contribution is real enough and the measurements are falsifiable. I would send it out.

Referee Report

3 major / 5 minor

Summary. The paper presents an algorithm–hardware co-design of a Graph Neural Network (GNN) decoder for surface-code quantum error correction, targeting real-time decoding on FPGA. Starting from a high-accuracy GNN, the authors apply hardware-guided pruning and retraining to obtain two reduced models (parameter cuts of 3.1× and 6.5×) aimed at average and worst-case latency of one syndrome cycle (~1 µs). Further cost reduction uses input-graph filtering and post-training quantization. An FPGA inference architecture is proposed and evaluated on surface codes up to distance 7 under circuit-level noise at p=10^{-3}. Within this scope the decoder is reported to outperform MWPM, reducing logical error rate by ~40% at 1 µs average latency and by ~13% under a strict 1 µs deadline.

Significance. Real-time decoding is a recognized bottleneck for fault-tolerant quantum computing; most deployed or proposed real-time decoders use MWPM or related matching methods. Demonstrating that a pruned/quantized GNN can meet microsecond-scale syndrome-cycle budgets on FPGA while improving logical error rate over MWPM is a concrete and useful contribution to the co-design literature. The work ships explicit hardware-friendly model variants, a proposed FPGA datapath (filtering + quantized inference), and falsifiable accuracy/latency numbers at a standard noise point. If the reported LER gains and 1 µs targets hold under the stated conditions, the paper provides a practical alternative path to high-accuracy real-time decoding at modest distances and a template for further GNN–hardware co-design.

major comments (3)

Abstract and evaluation claim LER reductions of 40% (average-latency) and 13% (strict 1 µs deadline) vs MWPM only for surface codes up to d=7 at a single physical error rate p=10^{-3} under circuit-level noise. The paper frames the work as enabling real-time decoding for fault-tolerant quantum computing, yet provides no distance-scaling study (e.g., d=9–13) or multi-p sweep showing that the pruned/quantized models retain their accuracy edge as d grows or p changes. Because pruning and quantization are co-designed to the reported d and p, this is load-bearing for transfer of both the LER advantage and the justification of the 1 µs targets. At minimum, add scaling trends or a clear limitation statement that the co-design and gains are demonstrated only in the d≤7, p=10^{-3} regime.
The MWPM baseline comparison is central to the accuracy claim. The manuscript must specify which MWPM implementation is used (e.g., PyMatching or equivalent), whether it is configured for real-time/online decoding with a comparable latency budget, and how syndrome batches and decoding windows are aligned with the GNN pipeline. If MWPM is run offline without a hard 1 µs constraint while the GNN is latency-capped, the 40%/13% LER reductions are not a fair real-time comparison. Report MWPM latency distribution under the same cycle constraint (or an explicit real-time MWPM variant) so that accuracy is compared under equivalent timing pressure.
FPGA latency and resource claims (average vs worst-case within one syndrome cycle) rest on the proposed architecture and on the accuracy of the timing/resource model after pruning, filtering, and quantization. Clarify whether the 1 µs figures are post-place-and-route measurements on a named FPGA device or estimates from a cycle-accurate model. If estimated, state the assumptions (clock frequency, memory ports, graph-filter hit rates) and provide utilization (LUTs, BRAM/URAM, DSP) for both model variants so that the hardware feasibility of the co-design can be audited.

minor comments (5)

Define the two pruned models (average-latency vs max-latency) with explicit layer widths, remaining edge/parameter counts, and pruning criteria in one place (table or subsection) so readers can reproduce the 3.1× and 6.5× reductions.
State the post-training quantization bit-widths (weights/activations) and any calibration set used; report accuracy drop from full precision to quantized models separately from pruning.
Input-graph filtering rules/thresholds should be specified (which syndrome nodes/edges are dropped and under what conditions) and their effect on both latency and LER quantified in an ablation.
Ensure all figures that plot LER vs p or latency include error bars or trial counts; the abstract percentages should be tied to a specific table/figure with sample size.
Related-work discussion of other neural and union-find real-time decoders should note latency and accuracy under comparable noise so the contribution relative to recent FPGA/ASIC QEC decoders is clear.

Circularity Check

0 steps flagged

No significant circularity: empirical LER/latency claims are measured against external MWPM baselines, not identities of fitted inputs or self-citation chains.

full rationale

This is an algorithm–hardware co-design paper. Its load-bearing claims (abstract and evaluation) are comparative logical error rates and decoding latencies of two hardware-guided pruned/quantized GNN models versus MWPM on simulated surface-code syndromes (d ≤ 7, circuit-level noise, p = 10^{-3}). Training, pruning (3.1×/6.5× parameter reduction), input-graph filtering and post-training quantization use data, but the reported 40 % and 13 % LER reductions at 1 µs average/max latency are direct empirical measurements against an independent classical baseline, not closed-form predictions that reduce by construction to the training fits. No self-definitional equations appear, no uniqueness theorem is imported from the authors to force the architecture, and no ansatz is smuggled via self-citation that would make the accuracy claim tautological. The derivation chain is the ordinary ML + FPGA pipeline evaluated on external benchmarks; it is self-contained. Minor self-citations of prior GNN decoder work (if present) are not load-bearing for the co-design or LER results.

Axiom & Free-Parameter Ledger

5 free parameters · 5 axioms · 2 invented entities

The load-bearing claim is empirical systems performance under a standard QEC simulation stack. It rests on domain models (surface code, circuit-level noise), design choices treated as free knobs (prune ratios, quantization, latency budget), and engineered artifacts (pruned models, FPGA pipeline) rather than new physical entities. No formal derivation from first principles; axioms are standard QEC and ML-hardware practice.

free parameters (5)

pruning / parameter-reduction factors (two models) = 3.1× and 6.5× parameter count reduction
Hardware-guided pruning produces 3.1× and 6.5× smaller models targeting average vs worst-case 1 µs latency; the exact sparsity pattern and which layers are pruned are design choices fitted to hardware and accuracy.
post-training quantization bit-width / scheme
Quantization is used to cut hardware cost; bit precision is a free implementation parameter that trades accuracy for resources and is not fixed by theory.
latency budget / syndrome cycle time = 1 µs
1 µs average and hard-deadline targets define the co-design objective; they are engineering constraints chosen for the evaluation, not derived constants.
physical error rate and noise model for training/eval = p=10^{-3}
Results are reported at p=10⁻³ under circuit-level noise; models trained and pruned for that operating point may not be optimal elsewhere.
input-graph filtering thresholds / rules
Graph filtering reduces hardware cost; filter criteria are design parameters that can change which syndromes the network sees.

axioms (5)

domain assumption Surface-code syndrome decoding under a circuit-level noise model is an adequate proxy for the real-time decoding problem studied.
All accuracy claims are under this standard simulation regime (abstract evaluation statement).
domain assumption A GNN decoder can achieve lower logical error rates than MWPM at the cost of more compute, and that accuracy can survive aggressive pruning and quantization.
Central motivation and co-design premise; accuracy after compression is measured, not proved.
domain assumption One syndrome cycle on the order of 1 µs is the relevant real-time constraint for the targeted control stack.
Latency targets and architecture sizing are built around this engineering assumption.
standard math Standard neural-network training, pruning, and post-training quantization procedures apply to the syndrome-to-correction mapping task.
ML co-design toolkit treated as given; no new learning theory claimed.
ad hoc to paper FPGA resource and timing models used for the proposed architecture accurately reflect achievable inference latency.
Latency claims depend on the specific pipeline mapping and toolflow results for the proposed design.

invented entities (2)

Two hardware-friendly pruned/retrained GNN decoder models (average-latency and max-latency targets) no independent evidence
purpose: Reduce parameter count 3.1× / 6.5× so GNN inference can meet real-time syndrome-cycle budgets while retaining accuracy advantage over MWPM.
Engineered model variants specific to this co-design; independent evidence would be public weights and third-party re-runs.
FPGA-based low-latency GNN inference architecture for QEC (with input-graph filtering and quantized datapath) no independent evidence
purpose: Realize real-time decoding on reconfigurable hardware under the stated latency constraints.
Paper-specific accelerator organization; falsifiable via bitstream/resource/timing reports and open RTL if released.

pith-pipeline@v1.1.0-grok45 · 28436 in / 3673 out tokens · 43040 ms · 2026-07-13T20:22:54.440611+00:00 · methodology

0 comments

read the original abstract

Quantum computers can solve selected problems more efficiently than classical computers, but current devices are limited by high physical error rates. Quantum Error Correction (QEC) mitigates this by encoding many physical qubits into a logical qubit, with the surface code among the most widely studied approaches. Since syndrome measurements are produced continuously, the decoder must process them fast enough to avoid becoming a system bottleneck, making real-time decoding essential for fault-tolerant quantum computing. While most state-of-the-art real-time decoders rely on Minimum-Weight Perfect Matching (MWPM), we instead use a high-accuracy Graph Neural Network (GNN) that trades higher computational cost for lower logical error rates. To make this GNN practical for real-time decoding, we apply algorithm-hardware co-design. We reduce complexity through hardware-guided pruning and retraining, producing two hardware-friendly models that reduce parameter count by $3.1\times$ and $6.5\times$. These target, respectively, an average decoding latency of one syndrome cycle and a worst-case latency within one syndrome cycle. We further reduce hardware cost using input-graph filtering and post-training quantization. Based on these optimized models, we propose an FPGA-based architecture for low-latency inference and real-time decoding. Evaluated on surface codes up to distance 7 under circuit-level noise at physical error rate $p=10^{-3}$, our decoder outperforms MWPM in decoding accuracy for both average-latency and max-latency settings. It reduces logical error rate by 40% at $1\mu s$ average latency, and by 13% under a strict $1\mu s$ deadline.

Figures

Figures reproduced from arXiv: 2603.22149 by Alessio Cicero, Luigi Altamura, Mats Granath, Moritz Lange, Pedro Trancoso.

**Figure 2.** Figure 2: Surface code of distance 3, with qubits highlighted according to their [PITH_FULL_IMAGE:figures/full_fig_p003_2.png] view at source ↗

**Figure 3.** Figure 3: Three pipeline stages architecture of the GNN. [PITH_FULL_IMAGE:figures/full_fig_p007_3.png] view at source ↗

**Figure 5.** Figure 5: Tail probabilities of the GNN input graph node count for code distance [PITH_FULL_IMAGE:figures/full_fig_p008_5.png] view at source ↗

**Figure 6.** Figure 6: Effect of weights, layers output features, or biases only quan [PITH_FULL_IMAGE:figures/full_fig_p009_6.png] view at source ↗

**Figure 7.** Figure 7: Latency as a function of the number of input graph nodes [PITH_FULL_IMAGE:figures/full_fig_p009_7.png] view at source ↗

**Figure 8.** Figure 8: Comparison of logical error rate and latency across different [PITH_FULL_IMAGE:figures/full_fig_p010_8.png] view at source ↗

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