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REVIEW 3 major objections 7 minor 27 references

FINN-GL: Generalized Mixed-Precision Extensions for FPGA-Accelerated LSTMs

T0 review · 3 major / 7 minor · reviewed 2026-08-06 · deepseek-v4-flash

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Pith's one-line read The FINN framework, extended with ONNX Scan-based LSTM support and new compiler transformations, compiles a mixed-precision quantized ConvLSTM into an FPGA IP that runs at 4.3 ms with 77.40% macro F1 on FI-2010, within 0.5 points of…

desk verdict Useful FINN extension for mixed-precision LSTM deployment, with a credible case study, but the recurrent-state equivalence claim needs harder evidence before I'd rely on the generated hardware. read the letter →

arxiv 2506.20810 v1 pith:J5XZZZ2F submitted 2025-06-25 cs.LG cs.AIcs.AReess.SP

Shashwat Khandelwal , Jakoba Petri-Koenig , Thomas B. Preu{ss}er , Michaela Blott , Shreejith Shanker This is my paper
classification cs.LGcs.AIcs.AReess.SP
keywords BrevitasFieldProgrammableGateArraysFINNHFTONNXQuantisedLSTMsRNNsmixed-precisionquantization
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

This paper claims that the FINN framework, historically limited to feed-forward quantized networks, can be generalized to deploy recurrent LSTMs on FPGAs without hand-built per-model hardware. The authors represent the LSTM's hidden-state loop with ONNX's Scan operator, expose all eleven internal quantizers so mixed precision becomes possible, and add compiler transformations that absorb floating-point scale and bias into threshold-based activations, producing an integer-only computation graph. They validate the flow by training a W8A6 quantized ConvLSTM on the FI-2010 limit-order-book dataset and compiling it to an XCZU7EV FPGA IP. The resulting accelerator runs a batch in 4.3 ms and achieves a macro F1 of 77.40%, nearly matching the 77.88% of the floating-point DeepLOB baseline while using under half the LUTs and 15% of DSPs. If correct, this offers a reusable, resource-efficient path for RNN deployment on edge FPGAs rather than one-off custom implementations.

What carries the argument

The load-bearing mechanism is FINN's multithreshold operator, which approximates monotonically increasing activations such as $\tanh$ and $\sigma$ by comparing inputs against a set of thresholds and returning the count of thresholds exceeded. The flow converts the QCDQ graph ($\text{QuantizeLinear}+\text{Clip}+\text{DequantizeLinear}$) into a QONNX $\text{Quant}$ node and then into FINN-ONNX as $\text{Multithreshold}+\text{Mul}+\text{Add}$. New or adapted transformations (MoveScalarMulPastMatMul, MoveLinearPastEltwiseMul, AbsorbMulIntoMultithreshold, AbsorbSignBiasIntoMultithreshold, RoundAndClipThresholds) move scalar floating-point scale and bias factors across the graph until they can be absorbed into threshold values, eliminating floating-point arithmetic entirely. The ONNX Scan operator—a container that executes a body graph iteratively while updating state variables—encapsulates the per-timestep recurrence, so the streamlined body is compiled once into HLS blocks and run in a standard for-loop bounded by the sequence length.

What would settle it

Take a trained QLSTM of any supported mixed-precision configuration, compile it through the flow, run the generated IP on a fixed input sequence, and compare the IP's output at every timestep with the Brevitas model's outputs; a single mismatch falsifies the claimed functional equivalence. A more targeted check is to compile an extreme configuration such as INT2 activations and observe whether recurrent-state errors accumulate beyond the rounding tolerance of RoundAndClipThresholds.

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Extended reading notes

Core claim

The central claim is that a quantized LSTM's recurrent computation can be expressed as an ONNX Scan body and then pushed through the QCDQ-to-QONNX-to-FINN-ONNX conversion chain into threshold-based integer-only hardware blocks, with the trained model's behavior preserved. The paper demonstrates this on a ConvLSTM for mid-price stock prediction: after quantizing to W8A6, the model compiles to a 150 MHz IP that reproduces the Brevitas-trained outputs, processes batch-1 in 4.3 ms, and scores macro F1 77.40% on FI-2010, comparable to floating-point DeepLOB at 77.88% and above several published baselines. The mixed-precision capability comes from controlling the bit-widths of all eleven internal quantizers of the LSTM layer, which the standard ONNX LSTM node does not expose.

Load-bearing premise

Everything hinges on the claim that replacing sigmoid and tanh with threshold-based approximations, and folding floating-point scale and bias into the thresholds, is exactly semantically equivalent to the original Brevitas QCDQ computation at every recurrent step; if any mixed-precision configuration breaks that equivalence, the FPGA would no longer reproduce the trained model's outputs.

Editorial extensions

If this is right

  • LSTM layers can be dropped into the standard FINN pipeline alongside convolutional and dense layers, so hybrid models such as ConvLSTMs compile to hardware automatically.
  • All eleven internal quantizers of an LSTM layer become individually selectable, enabling systematic mixed-precision exploration of accuracy against hardware cost.
  • At 4.3 ms per batch, the compiled IP processes FI-2010 data far faster than the roughly 192 ms average interval between market events, leaving a large real-time margin.
  • The integer-only streamlined graph keeps resource use modest on an edge FPGA (49.6% LUTs, 12.8% FFs, 15.2% DSPs), leaving headroom to unroll or replicate LSTM cells for further latency reduction.
  • Because the final graph contains no floating-point operators, the approach avoids the resource overhead of flows that retain floating-point blocks, at the cost of the threshold-approximation error.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • The paper validates the flow on a single W8A6 quantized configuration; whether the semantic equivalence of the threshold approximations holds across the full mixed-precision space remains an open empirical question, since error accumulation over long sequences could vary with bit-width choices.
  • The same Scan-based ONNX representation should extend naturally to other recurrent cells such as GRUs, because the Scan body is just an ONNX subgraph; the paper only exercises the LSTM case.
  • The reported 4.3 ms latency excludes data-movement overhead from the AXI-DMA subsystem; end-to-end latency will be higher, though the 192 ms event interval suggests the margin remains comfortable.
  • The accuracy comparison, while close, was obtained on a model that omits the inception blocks of DeepLOB; the paper's own experiments attribute no significant loss to this omission, but the claim of being 'comparable to DeepLOB' should be read against that architectural difference.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

3 major / 7 minor

Summary. The paper presents FINN-GL, an extension of the FINN toolchain for deploying quantized LSTM networks on FPGAs. The authors model a quantized LSTM using the ONNX Scan operator, convert the Brevitas QCDQ graph to QONNX and then to FINN-ONNX, and introduce or modify streamlining transformations that absorb floating-point scale and bias operations into thresholding operators. A custom HLS backend maps the streamlined graph to finn-hlslib blocks. They validate the flow with a W8A6 quantized ConvLSTM for the FI-2010 limit-order-book dataset, targeting a ZCU104/XCZU7EV device, reporting 4.3 ms batch-1 latency, resource utilization of about 49% LUTs, 13% FFs, and 15% DSPs, and macro F1 of 77.40% versus 77.88% for floating-point DeepLOB. The central claim is that the extended FINN flow provides a generalizable, mixed-precision FPGA deployment path for LSTMs that preserves the trained model's behavior.

Significance. If the central claim is established, this is a useful contribution to FPGA-based ML deployment. The work leverages an established open-source ecosystem (FINN, Brevitas, QONNX) and extends it at a sensible abstraction level: the Scan-based representation exposes all internal quantizers, and the compiler transformations map recurrent computations onto reusable HLS blocks. The case study provides concrete latency, resource, and accuracy numbers, and the authors state that their implementations are open sourced. The main gaps are in verification: the semantic equivalence of the recurrent streamlining transformations and the equivalence between the trained model and the generated hardware are asserted rather than demonstrated, and the accuracy comparison rests on single-run numbers without statistical error bars.

major comments (3)
  1. [III.B, Eqs. (7)-(8), Table I] The streamlining transformations that absorb floating-point scale and bias into MultiThreshold nodes are not shown to be semantics-preserving in a recurrent graph. In the LSTM equations (1)-(6), affine operations interact with elementwise multiplications (e.g., C_t = f_t ⊙ C_{t-1} + i_t ⊙ C̃_t and h_t = o_t ⊙ tanh(C_t)), so moving scalar or affine factors past elementwise multiplications and into thresholds requires careful reconciliation of state scales at every timestep. Moreover, RoundAndClipThresholds can change outputs for inputs near threshold boundaries, and in a feedback loop such perturbations can accumulate. The paper asserts that the graph is "functionally verified" (Section III.B) and claims a "one-to-one mapping" (Section IV.C.1), but it provides neither a proof nor numerical evidence. I ask for a concrete equivalence test: compare hidden states, cell states, and outputs of the original QCDQ graph with the streamlined FINN-ONNX graph over all timesteps for each supported mixed-precision configuration, reporting bit-exact or bounded-error results and a discussion of threshold-boundary cases.
  2. [IV.B.2, Tables III-IV] The accuracy comparison is not statistically grounded. All reported metrics appear to come from a single training and evaluation run; there are no error bars, confidence intervals, or multiple seeds. The macro F1 difference between Q-ConvLSTM (77.40%) and DeepLOB (77.88%) is small and may be within run-to-run variation, yet Section IV.C.2 claims "matching (or bettering)" and quantifies gains over baselines as percentages. Please report mean and standard deviation over at least several seeds for the floating-point and quantized models, and state the significance test used. In addition, the statements "accuracy drop of ≈1.5%" and "1% higher accuracy" in Section IV.B.2 need a defined metric and repeatability.
  3. [IV.C.1] The hardware deployment section does not report any direct comparison between the outputs of the generated IP and the trained software model. The "one-to-one mapping" is the load-bearing assertion of the paper, but the only evidence cited is agreement between HLS cosimulation latency and board-level latency. Please include a measured accuracy or output-comparison experiment on the FPGA, for example running the test set through the IP and reporting the resulting F1, or comparing IP outputs to software outputs sample by sample, and state the data widths and rounding modes used in the HLS kernels.
minor comments (7)
  1. [Table I] The transformation name "AbsorbsignbiasintoMultithrehsold()" is misspelled; it should be "AbsorbSignBiasIntoMultiThreshold()".
  2. [III.B] The phrase "the result shown in eq8" should be "the result shown in Eq. (8)".
  3. [IV.B.2] The text says the z-score normalized features were quantized to INT8, while the model is later described as W8A6; clarify whether input quantization is separate from the activation bit-widths and report the input precision used in the hardware implementation.
  4. [Abstract and IV.C.2] The claim that the quantized model "matches (or betters)" state-of-the-art models is stronger than Table IV supports, since the macro F1 of Q-ConvLSTM is slightly below DeepLOB and C(TABL); please qualify the claim.
  5. [III.A and IV.C.1] The paper refers to open-source repositories (qonnx and FINN-GLSTM-Hw) but provides no URLs or version hashes; please include them for reproducibility.
  6. [Eq. (8)] The mapping "Tanh + Quant -> Multithreshold + Mul + Add" is not fully explained; please clarify how sigmoid and tanh thresholds are generated and what the Mul and Add nodes represent after the transformation.
  7. [References] Reference [25] is listed as "A. Brevitas"; please provide the actual author or tutorial title for the QuantLSTM documentation.

Circularity Check

0 steps flagged · score 0.0 of 10

No significant circularity: the paper's claims rest on external benchmarks (FI-2010, XCZU7EV latency) and on functional verification against Brevitas QuantLSTM; the recurrent-streamlining gap is an unsupported-equivalence risk, not a circular reduction.

full rationale

The central results are measured, not derived from fitted inputs: macro F1 77.40% is evaluated on the held-out two days of FI-2010 and compared against independently reproduced DeepLOB (77.88%); batch-1 latency 4.3 ms is measured from the synthesized IP on XCZU7EV. No accuracy or latency number is obtained by fitting a parameter and then 'predicting' a related quantity. The QCDQ-to-QONNX-to-FINN-ONNX conversions in Eqs. (7)-(8) are compiler rewrite rules defined by the QONNX/FINN operator semantics; they are not empirical predictions, and the paper does not present them as derived from the target numbers. The paper cites FINN, Brevitas, and QONNX, all with overlapping author groups, but these are open-source toolchains with external user bases and the relevant comparison (against Brevitas QuantLSTM) is a functional check against an independent reference implementation of the same layer, not a self-referential derivation. The skeptical concern that threshold-based streamlining may not preserve recurrent state semantics across iterations is a correctness/verification gap: the paper asserts 'functional verification' and 'one-to-one mapping' (Section IV.C.1) without publishing the equivalence proof or per-timestep numerical traces. That is an evidence deficiency, not a circular argument, because the hardware output is not defined to equal the streamlined graph by construction; it is an empirical claim that could fail. No circular step can be quoted, so the circularity score is 0.

Assumptions & free parameters 4 free parameters · 3 assumptions · 0 invented entities

The central claim depends on semantic equivalence assumptions in the compiler transformation pipeline and on case-study-specific design choices. These are reasonable engineering assumptions, but they are tested rather than formally proven.

free parameters (4)
  • Activation bit-width (A6) = 6 bits
    Chosen after systematically reducing activation bit-width until significant accuracy degradation was observed; affects both accuracy and hardware resource usage.
  • Weight bit-width (W8) = 8 bits
    Standard choice for quantized training; not derived from first principles.
  • LSTM hidden units = 64
    Selected through iterative model design to balance performance and complexity.
  • Input sequence length = 25
    Chosen after setting convolutional strides to optimize the input size for the LSTM layer.
assumptions (3)
  • domain assumption Quantized sigmoid and tanh activations can be exactly represented by multithreshold operators with appropriate integer thresholds.
    Invoked in Section II.C and used in converting the QONNX graph to FINN-ONNX in eq. 8; the hardware relies on this equivalence.
  • domain assumption The ONNX Scan operator body graph exactly replicates the LSTM recurrence semantics of the Brevitas QuantLSTM layer.
    Stated in Section III.A as the basis for functional verification; any semantic mismatch would propagate to the hardware.
  • domain assumption The streamlining transformations, including the new ones described in Table I, preserve functional equivalence after absorbing floating-point operations into thresholds.
    Assumed throughout Section III.B and III.C; no formal proof is given, only functional testing.

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Cite this review

Pith. "Pith review of FINN-GL: Generalized Mixed-Precision Extensions for FPGA-Accelerated LSTMs." pith.science (2026). https://pith.science/paper/J5XZZZ2F

@misc{pith2026250620810,
  author       = {Pith},
  title        = {Pith review of: FINN-GL: Generalized Mixed-Precision Extensions for FPGA-Accelerated LSTMs},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/J5XZZZ2F}},
  note         = {Machine review of arXiv:2506.20810}
}
read the original abstract

Recurrent neural networks (RNNs), particularly LSTMs, are effective for time-series tasks like sentiment analysis and short-term stock prediction. However, their computational complexity poses challenges for real-time deployment in resource constrained environments. While FPGAs offer a promising platform for energy-efficient AI acceleration, existing tools mainly target feed-forward networks, and LSTM acceleration typically requires full custom implementation. In this paper, we address this gap by leveraging the open-source and extensible FINN framework to enable the generalized deployment of LSTMs on FPGAs. Specifically, we leverage the Scan operator from the Open Neural Network Exchange (ONNX) specification to model the recurrent nature of LSTM computations, enabling support for mixed quantisation within them and functional verification of LSTM-based models. Furthermore, we introduce custom transformations within the FINN compiler to map the quantised ONNX computation graph to hardware blocks from the HLS kernel library of the FINN compiler and Vitis HLS. We validate the proposed tool-flow by training a quantised ConvLSTM model for a mid-price stock prediction task using the widely used dataset and generating a corresponding hardware IP of the model using our flow, targeting the XCZU7EV device. We show that the generated quantised ConvLSTM accelerator through our flow achieves a balance between performance (latency) and resource consumption, while matching (or bettering) inference accuracy of state-of-the-art models with reduced precision. We believe that the generalisable nature of the proposed flow will pave the way for resource-efficient RNN accelerator designs on FPGAs.

Figures

Figures reproduced from arXiv: 2506.20810 by the authors.

Figure 1
Figure 1. The figure contrasts the information flows of con [PITH_FULL_IMAGE:figures/full_fig_p001_1.png] view at source ↗
Figure 2
Figure 2. This figure illustrates the different stages in the overall deployment workflow for generalized quantised LSTM layer [PITH_FULL_IMAGE:figures/full_fig_p003_2.png] view at source ↗
Figure 4
Figure 4. The figure illustrates how the Scan operator replicates the recurrent hidden state computations in an LSTM layer. The yellow, red, and blue arrows highlight the pathways for input data processing and state updates at each time step for every input in the sequence. outputs comprise the updated state variables and one or more output tensors. The computation performed in each iteration is defined by the operator’s body… view at source ↗
Figures from the paper (2 more)
Figure 5
Figure 5. Figure 5: The figure illustrates examples of which transforma [PITH_FULL_IMAGE:figures/full_fig_p005_5.png]
Figure 6
Figure 6. Figure 6: The figure demonstrates the compute nodes each [PITH_FULL_IMAGE:figures/full_fig_p006_6.png]

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Reviewed August 6, 2026 · model on record in the stance chip above.