Bias-preserving cat-cat CNOT gate via vacuum-conditional beam-splitter

Arne L. Grimsmo; Connor T. Hann; Harald Putterman; Kyungjoo Noh; Oskar Painter; Ron Belyansky; Yufeng Ye

A coherent CNOT between two cat qubits can preserve the cats' exponential bit-flip bias by swapping the target through an empty auxiliary mode and back, with a cross-Kerr-controlled beam-splitter supplying the conditional phase.

Reviewed by Pith at T0; open to challenge. T0 means a machine referee read the full paper against a public rubric. the ladder, T0–T4 →

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2026-08-01 04:23 UTC pith:JQGGNPGW

load-bearing objection A well-executed, honestly-conditional design study for a bias-preserving cat-cat CNOT; the physics is coherent, but the megaquop claim rests on a χ/K~1000 coupler that no one has built. the 2 major comments →

arxiv 2607.22852 v2 pith:JQGGNPGW submitted 2026-07-24 quant-ph

Bias-preserving cat-cat CNOT gate via vacuum-conditional beam-splitter

Yufeng Ye , Connor T. Hann , Kyungjoo Noh , Harald Putterman , Ron Belyansky , Arne L. Grimsmo , Oskar Painter This is my paper

classification quant-ph PACS 03.67.Lx85.25.-j

keywords cat qubitsnoise biasbias-preserving CNOTvacuum-conditional beam-splittercross-Kerr interactionrepetition codequantum error correctiongeometric phase

verification ladder T0 review T1 audit T2 compute T3 formal T4 reserved

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

Cat qubits are attractive for quantum error correction because their bit-flip errors are exponentially suppressed as the photon number grows, while phase-flip errors grow only linearly. Preserving that strong noise bias through an entangling CNOT has been the bottleneck: earlier cat–cat CNOT proposals keep two-photon dissipation active during the gate and are limited by adiabaticity. This paper proposes a CNOT built from pure unitary dynamics: a cross-Kerr interaction makes a beam-splitter swap the target cat into an empty bin mode and back only when the control is in |0>, and the round trip accumulates a (−1)^n geometric phase that flips the target. The paper argues that the gate keeps bit-flip errors exponentially suppressed on both control and target, and that a distance-7 repetition code made of 13 cat qubits could then hold logical error below 10^-6 per cycle, assuming 1 ms cavity lifetimes, a 10^-4 bin thermal population, and a strong sign-flippable cross-Kerr coupler. The paper is explicit that this exact coupler operating point has not yet been demonstrated in a single device.

Core claim

The central claim is that a CNOT between two dissipative cat qubits can be made bias-preserving without engineered dissipation during the gate, by realizing the target X gate as a controlled SWAP2. The control is first displaced so its logical states become |0> and |2α>; when the control is in |0> (ON), a beam-splitter pulse swaps the target coherent state into an auxiliary bin mode, and a second pulse swaps it back, with the two swaps accumulating a per-photon (−1)^n geometric phase that maps |α> to |−α>. When the control is in |2α> (OFF), the cross-Kerr interaction detunes the bin by 4χ|α|^2 and the target is untouched. Because the beam-splitter preserves total photon number and carries th

What carries the argument

The load-bearing object is the vacuum-conditional beam-splitter (VCB): a Hamiltonian H = χ a_c†a_c b†b + g(b†a_t + b a_t†), in which a cross-Kerr coupling between control cat and a vacuum 'bin' mode conditionally detunes a resonant beam-splitter between bin and target. The controlled-SWAP2 consists of two beam-splitter pulses of area π/2; acting on a Fock state |m,n>_b,t it accumulates (−1)^{m+n}, so with the bin starting empty each target photon contributes (−1)^n and a coherent state |α> maps to |−α>, i.e. an X gate on the cat qubit. Two echo layers complete the scheme: a χ-echo flips the sign of the cross-Kerr at mid-gate to cancel detuned-branch phases, and a displacement echo swaps whic

Load-bearing premise

The entire proposal hinges on a hardware ingredient the paper admits has not yet been built as a single device: a few-MHz cross-Kerr interaction between control and bin whose sign can be flipped mid-gate while self-Kerr stays below ~4 kHz (χ/K ~ 10^3).

What would settle it

A three-mode circuit experiment implementing H above would settle it: measure the control OFF bit-flip as a function of |α|^2; if it does not fall exponentially with cat size, or if the echoed control phase-flip saturates above ~10^-4 at |α|^2=10 with bin thermal population 10^-4, the central performance claim is refuted. A simpler necessary check is whether any coupler can flip the sign of a ~4 MHz cross-Kerr at the pulse midpoint without lifting self-Kerr above the kHz level.

Watch this falsifier. Get emailed when new claim-graph text bears on it.

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If this is right

A bias-preserving CNOT can be executed with the two-photon stabilization turned off, so gate speed is set by the two interaction strengths, not by the dissipation rate κ2, removing the non-adiabatic phase-flip channel of Zeno-based gates.
In repetition-code syndrome extraction, ancilla bit-flips that occur mid-round do not propagate onto the data cats, because the ancilla remains in the displaced basis until both CNOTs finish and is only then restored and stabilized.
At the paper's operating point (T1=1 ms, nbar=10, bin thermal population 10^-4, T_SWAP=50 ns), the simulated logical error per cycle is below 10^-6 at code distance 7 (13 cat qubits) and near 10^-9 at distance 11.
Because the gate preserves bias on both control and target, it can be applied transversally between repetition-code blocks and extends to a bias-preserving Toffoli gate, giving a native non-Clifford element for a universal set.
All bit-flip channels remain exponentially suppressed (control ≲10^-7, target ≲10^-9 per gate at nbar=10), while phase-flip errors are dominated by photon-loss dephasing ~nbar*T_CX/T1.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

If the assumed coupler is realized, the dominant path to better logical memory shifts from gate design to cavity lifetime and bin thermalization: errors scale roughly as nbar*T_gate/T1 plus a ~nth floor, so hardware improvements map almost linearly onto logical error reduction.
The (−1)^n phase is a generic property of beam-splitter SWAP2, not of coherent-state cats specifically; the same vacuum-conditional detuning could in principle be adapted to other bosonic qubit encodings with a parity structure, though the paper does not explore this.
The bin thermal floor p_Z^(c) ≈ n_th is intrinsic to the parity of the geometric phase, so a device that cannot reach n_th ≲ 10^-4 would need a fundamentally different refocusing strategy than the χ-echo, which only cancels persistent deterministic phases.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit.

Desk Editor's Note

A well-executed, honestly-conditional design study for a bias-preserving cat-cat CNOT; the physics is coherent, but the megaquop claim rests on a χ/K~1000 coupler that no one has built.

read the letter

Here's my take. The gate mechanism is genuinely new: a cross-Kerr-controlled beam-splitter that swaps the target cat into an auxiliary bin and back, picking up the (−1)^n geometric phase, with χ-echo and displacement-echo sequences to kill the leading coherent errors. The supplement derives the error channels carefully, the error budget is transparent, and the comparison with a Zeno CNOT in the same decoder is fair. That is real work, done well.

The soft spots are the load-bearing hardware assumptions. The headline pL<1e-6 at d=7 requires χ/K≈1000 with a mid-gate sign flip of χ, bin thermal population 1e−4 (which the paper admits is a factor-of-two better than the best direct bounds), and T1=1 ms. The paper says plainly that the exact operating point has not been demonstrated in a single device. That is not a hidden flaw, but it means the central claim is conditional. If χ/K is an order of magnitude lower, the echoed self-Kerr phase-flip term scales as (K T)^4 and would swamp the T1 floor—the stress-test note gets that right. Also, no code or data files are shipped, so the numerical results are not immediately re-runnable. The circuit-level noise model is a reasonable approximation, but it is an approximation: per-gate rates from unitary simulations with dissipation added analytically, independent Pauli injection, projection-based errors.

None of this is internally contradictory. The derivations are clean, the limitations are stated, and the proposal is a sensible design study rather than an overclaim. I would send it to referees. The main things I'd want referees to push on: (1) how plausible the χ/K≈1000 sign-flippable coupler actually is, and whether there are alternative circuit implementations that could relax it; (2) whether the thermal population assumption can be met; (3) reproducibility—code/data release would help a lot. For a reader in cat-qubit QEC, this is worth a careful read; I'd probably cite it as the reference for the VCB approach.

Referee Report

2 major / 3 minor

Summary. This paper proposes a bias-preserving CNOT gate between two dissipative cat qubits based on a vacuum-conditional beam-splitter (VCB). The control cat is displaced to the {|0>, |2α>} basis; a cross-Kerr interaction χ n_c n_b conditionally detunes an auxiliary bin mode, so a beam-splitter drive executes a SWAP2 (two π/2 exchanges) on the target only when the control is in vacuum. The SWAP2 geometric phase (−1)^n maps |α> to |−α>, realizing X. A χ-echo (sign flip of χ at the gate midpoint) and a control displacement echo suppress the leading coherent errors. The authors simulate the three-mode unitary dynamics with analytic photon-loss and thermal corrections, build a repetition-code circuit-level noise model with independent Pauli errors, and find p_L < 10^-6 per cycle at distance 7 (13 cat qubits) for n=10, T1=1 ms, n_th=10^-4, and χ/K≈10^3.

Significance. If the stated hardware parameters can be met, the proposal is significant: it provides a dissipation-free route to a bias-preserving cat–cat CNOT, avoiding the Zeno adiabaticity constraint, and it quantifies all relevant error channels to below the repetition-code threshold. The analytic derivations—target bit-flip preservation under T1 loss, the SU(2)/geometric-phase structure of SWAP2, and the echo scalings—are clean and useful, and the supplemental material is unusually detailed and honest about assumptions. The paper is also explicit about the unproven nature of the key nonlinearity requirement, which is a credit to the authors but needs to be reflected in the central claim.

major comments (2)

[S-VIID/S-XI] The central megaquop claim rests on the unvalidated requirement χ/K≳10^3 with a mid-gate sign-flippable cross-Kerr. S-VIID states that K/2π≲4 kHz (χ/K≈1000) is needed to keep the echoed control self-Kerr below 10^-3 at n≈10; S-XI admits that “the exact operating point used in our simulations has not been demonstrated in a single device.” Since the residual control phase-flip scales as (K_a T)^4 |α|^4 (Eq. S42), a realized χ/K≈100 would raise this contribution by roughly 10^4, far above the T1 floor and incompatible with the d=7 p_L<10^-6 claim. Please add a sensitivity analysis over χ/K and over the sign-flip fidelity δ, and either substantiate the coupler pathway in Eqs. (S49)–(S51) or state the megaquop claim as explicitly conditional on this future device capability.
[S-XIIID] The repetition-code simulation injects a product of independent single-qubit Pauli channels on data and ancilla, with no correlated errors, no leakage, and no explicit twirling. The gate-simulation output is a projected density matrix, not by construction an independent Pauli channel; bin-thermal or cross-Kerr processes can produce correlated phase-flips between control and target, and the projection step converts leakage into Pauli errors. Because the headline p_L is a quantitative number below 10^-6, this simplification is load-bearing. Please justify it, for example by twirling the simulated gate map or by bounding the largest correlated component, or show that the repetition-code result is insensitive to such correlations.

minor comments (3)

[Abstract/Discussion] The “megaquop regime” is defined through a memory p_L<10^-6 per cycle. Since megaquop computation also requires fault-tolerant logical operations and a full resource estimate, I suggest clarifying that the present result demonstrates a bias-preserving memory/gate primitive rather than a complete megaquop computation.
[S-VIIE] The pure-dephasing contribution in Eq. (S44) depends on the 1/f IR cutoff and on the assumed T_φ/T1=5. A one-sentence sensitivity note would help, since T_φ/T1 could vary by factor two in other devices.
[S-XIIIE/Fig. S11] The Zeno-CNOT comparison uses a representative κ2/(2π)=1 MHz and the phase-flip model of Refs. [26,27] rather than a microscopic simulation. This is stated, but the figure/caption should more prominently say that the Zeno curve is not optimized in κ2 or in other Zeno-specific parameters.

Circularity Check

0 steps flagged

No circular derivation: the megaquop-level logical error rates are simulation outputs from a stated Hamiltonian and explicit noise model; the undemonstrated hardware operating point is an acknowledged feasibility assumption, not a fitted or self-referential input.

full rationale

The paper's central claim is a gate simulation, not an empirical prediction: pL<1e-6 per syndrome cycle in Fig. 4 is obtained by injecting explicitly enumerated per-gate error rates (Fig. S10) into a standard Stim/MWPM repetition-code decoder. No parameter is fitted to the reported pL values. The conditional statement in the abstract ('Assuming good component lifetimes and precise nonlinearity engineering') makes the hardware requirements part of the premise rather than a hidden output. Critically, Sec. S-XI explicitly admits 'the exact operating point used in our simulations has not been demonstrated in a single device' — this is an honest limitation about realizability, not a circular step. The displacement-echo technique is attributed to co-authored prior work [24], but the paper independently re-derives the (KaT)^4 scaling in Sec. S-VII and validates it numerically against simulation, so the self-citation is not load-bearing in the circularity sense. Similarly, the assumed thermal population nth=1e-4 is explicitly labeled 'a factor-of-two improvement over the best direct bounds we are aware of,' i.e. an acknowledged assumption rather than a disguised fit. No equation in the derivation reduces by construction to its own inputs, and no predicted quantity is a renamed fitted parameter. The most fragile element — the requirement of a sign-flippable cross-Kerr with chi/K ~ 1000 — is a hardware feasibility risk, not a circularity of the derivation chain.

Axiom & Free-Parameter Ledger

10 free parameters · 6 axioms · 1 invented entities

The central claim depends on several hand-chosen or assumed parameters—most importantly bin thermal population, cavity T1, and the χ/K ratio—plus standard cat-qubit and beam-splitter physics. The paper is transparent about these requirements, but the headline pL<1e-6 is only as strong as the assumptions.

free parameters (10)

bin thermal population ¯n_th = 1e-4
Assumed residual thermal occupancy of the bin mode; sets control phase-flip floor pZ(c)≈¯n_th and control OFF bit-flip floor 2¯n_th TCX/T1. Paper states this is a factor-of-two improvement over best direct bounds (2e-4) and corresponds to ~26 mK effective temperature.
cavity lifetime T1 = 1 ms
Assumed single-photon lifetime of control/target/bin cavities; phase-flip budget ¯n TCX/T1 scales linearly with 1/T1. At T1=250 µs the logical error at d=11 rises to ~1e-6.
cross-Kerr/self-Kerr ratio χ/K = 1000 (χ/2π=4 MHz, K/2π≈4 kHz)
Chosen operating point for displacement echo to keep control self-Kerr phase-flip below 1e-3 at ¯n=10; not yet demonstrated in a single device.
elementary SWAP duration T_SWAP = 50 ns (syndrome extraction), 100 ns (transversal)
Chosen gate speed trading control OFF bit-flip (adiabaticity) against coherence-limited phase-flip; DRAG parameters optimized per T.
ancilla cat size ¯n_a = 8
Chosen so the Fock-space tail of displaced control |2α> has negligible probability of low-n_c components that would resonantly drive the bin; suppresses target OFF bit-flip below 1e-9.
pure dephasing assumption T_φ = 5 T1
Assumed Ramsey dephasing time for the displaced-basis 1/f dephasing contribution pZ,φ; from reported storage-cavity T1 and T2 measurements.
measurement/reset error p_meas = 1e-3
Assumed ancilla measurement and reset error probability in the QEC simulation; standard target but not derived.
DRAG pulse shape parameters (σ,γ) = σ=0.22, γ=1.0 at T=50 ns; σ=0.18, γ=1.0 at T=100 ns
Optimized via two-dimensional sweep at ¯n=6 to minimize control OFF bit-flip; residual bin population tracks control bit-flip.
bin-target self-Kerr matching = K_b≈K_t (within factor 0.2–1.9)
Required to avoid control phase-flip from which-path information; Fig S6 shows tolerance 0.2–1.9 for pZ<1e-3.
measurement time T_meas = 200 ns
Assumed ancilla readout/reset/stabilization time in the repetition-code round; sets round time 600 ns.

axioms (6)

domain assumption Two-photon dissipation stabilizes the cat manifold and gives exponential bit-flip / linear phase-flip scaling
Background assumption of dissipative cat qubits, cited from Refs [10,11,13-16]; used throughout, e.g., Sec. S-I.
domain assumption Infinite-time projection onto the cat basis accurately models finite-time restabilization after the gate
Sec. S-I defines errors via projection; if real restabilization adds logical errors, the per-gate rates feeding Fig. 4 are optimistic.
domain assumption Intermittent stabilization (κ2 off during gate, on before/after) does not significantly degrade the noise bias
Main text cites Refs [15,16]; the gate requires this behavior, but it is not derived in this paper.
ad hoc to paper The cross-Kerr interaction can be made sign-flippable at the gate midpoint with negligible overhead and with χ/K ≈ 10^3
Needed for the χ-echo; Sec. S-XI sketches a flux-tunable SQUID/quarton path but states the operating point has not been demonstrated.
ad hoc to paper Circuit-level noise model uses independent single-qubit Pauli channels with rates from gate simulations plus analytic photon loss
Stated in Sec. S-XIIID; correlated errors through the shared bin are not injected.
standard math Beam-splitter unitary on Fock states gives U|m,n> = (-i)^(m+n)|n,m> and SWAP2 gives (-1)^n phase
Standard beam-splitter SU(2) result, derived in Sec. S-III from Heisenberg equations; not a new assumption.

invented entities (1)

Auxiliary bin mode b independent evidence
purpose: Auxiliary bosonic mode that mediates the conditional SWAP2; temporarily stores the target cat and enables the geometric-phase X gate while preserving bit-flip suppression.
Not a new physical entity; an extra cavity mode whose beam-splitter interaction with another mode is experimentally established (Refs [44,45]). The gate requires its lifetime and self-Kerr to match the target.

pith-pipeline@v1.3.0-alltime-deepseek · 41546 in / 20670 out tokens · 206993 ms · 2026-08-01T04:23:09.280785+00:00 · methodology

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Cite this review

Pith. "Pith review of Bias-preserving cat-cat CNOT gate via vacuum-conditional beam-splitter." pith.science (2026). https://pith.science/paper/JQGGNPGW

@misc{pith2026260722852,
  author       = {Pith},
  title        = {Pith review of: Bias-preserving cat-cat CNOT gate via vacuum-conditional beam-splitter},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/JQGGNPGW}},
  note         = {Machine review of arXiv:2607.22852}
}

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read the original abstract

Cat qubits can exhibit strong noise bias due to their exponentially enhanced bit-flip times and only polynomially reduced phase-flip times with increasing photon number, which makes them attractive candidates for hardware-efficient quantum error correction. However, it is difficult to maintain this strong noise bias in logical operations such as CNOT gates between cats. Here, we propose a coherent CNOT gate scheme between two dissipative cats that preserves the exponential noise bias. The proposed gate relies only on unitary operations, which avoids the non-idealities associated with many existing gate schemes that rely on engineered dissipations. Assuming good component lifetimes and precise nonlinearity engineering, the proposed gate can enable logical memory in the megaquop regime (logical error rates < 10^-6) with a distance-7 repetition code consisting of 13 cat qubits.

Figures

Figures reproduced from arXiv: 2607.22852 by Arne L. Grimsmo, Connor T. Hann, Harald Putterman, Kyungjoo Noh, Oskar Painter, Ron Belyansky, Yufeng Ye.