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REVIEW 3 major objections 5 minor 5 cited by

Analysis of Generalized Hebbian Learning Algorithm for Neuromorphic Hardware Using Spinnaker

T0 review · 3 major / 5 minor · reviewed 2026-08-12 · deepseek-v4-flash

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Pith's one-line read Running the Generalized Hebbian Algorithm on the SpiNNaker neuromorphic platform is reported to lift classification accuracy on the UCI Wine dataset to 80.56%, with 2650 J of energy consumption.

desk verdict An incomplete draft whose central hardware-benefit claim is confounded by different train/test splits and missing tables; worth a desk reject, not referee time. read the letter →

arxiv 2411.11575 v1 pith:KCSS2ZZS submitted 2024-11-18 cs.NE

Shivani Sharma , Darshika G. Perera This is my paper · ORCID
classification cs.NE
keywords GeneralizedHebbianAlgorithmSpiNNakerneuromorphichardwarelearningclassificationaccuracyenergyconsumptionUCIMachineRepositoryMNIST
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

This paper sets out to show that the Generalized Hebbian Algorithm (GHA), a biologically plausible unsupervised learning rule, can be implemented on the SpiNNaker neuromorphic hardware platform and deliver competitive classification accuracy with low energy use. The authors compare GHA with standard Hebbian learning on MNIST and five UCI Machine Learning Repository datasets, measuring error rate, convergence rate, training time, memory usage, accuracy, and energy. They report that GHA outperforms Hebbian learning on error rate, convergence, and accuracy, at the cost of higher training time and memory. Their headline result is 80.56% classification accuracy on the Wine dataset with 2650 J of energy using a 30% training split on SpiNNaker, compared with 72.80% accuracy without SpiNNaker using an 80% split. The sympathetic reading is that biologically inspired learning rules are viable and energy-efficient on parallel neuromorphic hardware.

What carries the argument

The Generalized Hebbian Algorithm (GHA) is the central object: an unsupervised online update rule in which each output unit learns one eigenvector of the input correlation matrix, with outputs ordered by decreasing eigenvalue, extending Hebb's 'fire together, wire together' rule to find principal components from data without first computing the correlation matrix. SpiNNaker is the hardware carrier: a massively parallel neuromorphic machine built from ARM cores, with packet-switched Address Event Representation (AER) multicast communication, designed to simulate spiking neural networks in real time. The paper's argument runs through the interaction of these two: GHA's simple, local, sample-by-sample updates are well matched to SpiNNaker's parallel event-driven architecture. The experiments also rely on adjusting the training/test split (70/30, 50/50, 80/20, 30/70), which the authors identify as the main change that raised GHA's classification accuracy from 30.56% on MNIST to over 80% on the UCI Wine dataset.

What would settle it

Run GHA on the UCI Wine dataset with the same training/test split (for example 30/70) both on SpiNNaker and on the non-SpiNNaker setup and compare the accuracies and energy readings; if the reported 80.56% versus 72.80% gap vanishes or inverts at matched splits, the hardware-driven improvement is not supported.

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Extended reading notes

Core claim

The paper's central claim is that GHA—an online rule that learns the eigenvectors of the input autocorrelation matrix directly from samples—maps cleanly onto SpiNNaker and yields significant improvements in classification accuracy compared with both plain Hebbian learning and the same GHA run without SpiNNaker. On MNIST, GHA shows a lower error rate and a higher average convergence rate than Hebbian learning, but it also uses more memory and takes longer to train. On the UCI datasets, the authors report the highest accuracy of 80.56% for the Wine dataset with a 30% training split on SpiNNaker at 2650 J, and 72.80% without SpiNNaker at 7100 J with an 80% training split. They attribute the improvement to SpiNNaker's neuromorphic, energy-efficient processing and conclude that GHA is well suited to high-performance, rapid-convergence tasks such as image and speech recognition.

Load-bearing premise

The claim that SpiNNaker improves accuracy rests on comparing runs with different training-set sizes, 30% on SpiNNaker versus 80% without, so the hardware effect is never separated from the effect of the data split.

Editorial extensions

If this is right

  • GHA offers a biologically plausible route to feature extraction that can run on parallel neuromorphic hardware without pre-computing input covariance matrices.
  • On the reported UCI Wine result, GHA on SpiNNaker reaches 80.56% accuracy with 2650 J, indicating that brain-inspired learning can be energy-efficient on small benchmark tasks.
  • GHA's higher accuracy and convergence rate come with increased training time and memory usage, so resource management is a direct constraint on its practical use.
  • Adjusting the training-to-test split is the lever the authors used to improve GHA accuracy from 30.56% on MNIST to above 80% on UCI datasets.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • Because the SpiNNaker and non-SpiNNaker comparisons used different training splits, the accuracy gap cannot be cleanly attributed to the hardware; a matched-split comparison would settle whether SpiNNaker itself improves generalization.
  • The 80.56% figure is a single small dataset result; a natural extension is to test GHA on larger benchmarks with the same split-adjustment protocol to see whether the accuracy gain generalizes beyond the UCI Wine dataset.
  • If matched-split comparisons confirm a hardware benefit, it would suggest that event-driven parallel execution adds a regularization-like effect to Hebbian learning, a hypothesis that future work could test directly.
  • The authors' planned FPGA-based GHA accelerators could reuse the same accuracy and energy metrics to compare neuromorphic versus reconfigurable platforms on equal terms.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

3 major / 5 minor

Summary. The paper reports an experimental comparison of the Generalized Hebbian Algorithm (GHA) and standard Hebbian learning on the MNIST and UCI Machine Learning datasets, with and without the SpiNNaker neuromorphic platform. The central claim is that GHA on SpiNNaker achieves significant improvements in classification accuracy, with a reported peak of 80.56% on the UCI Wine dataset using a 30% training split, versus 72.80% without SpiNNaker using an 80% training split, along with energy consumption of 2650 J and 7100 J respectively. The authors conclude that GHA outperforms Hebbian learning and that SpiNNaker is a powerful platform for improving classification accuracy.

Significance. If the central claim were supported, demonstrating that running GHA on SpiNNaker improves classification accuracy relative to the same algorithm without the platform would be a notable result for neuromorphic computing. The paper also provides a concise summary of SpiNNaker's architecture and the GHA update rule. However, the experimental design does not support the claim: the hardware and non-hardware conditions differ in training set size, the supporting tables are absent and mislabeled, and no hyperparameters or error bars are provided. As presented, the result is not a reproducible measurement of hardware-driven improvement.

major comments (3)
  1. [Section III.B, paragraph after Table VII] The comparison that grounds the abstract's claim of 'significant improvements' is confounded: the SpiNNaker condition uses a 30% training split and the non-SpiNNaker condition uses an 80% split, and the manuscript itself states that 'the main change was the adjustment of the training and test data split.' Consequently, the difference between 80.56% and 72.80% cannot be attributed to SpiNNaker, and the central claim collapses unless the comparison is rerun with identical splits.
  2. [Tables IV-VII] The tables are captioned 'ON HEBBIAN LEARNING ALGORITHM' even though the text describes the results as being for the GHA model, and the table bodies are missing entirely. This makes it impossible to verify which algorithm produced the reported accuracy and energy figures, including the headline 80.56% result; the algorithm attribution must be corrected and the tables populated before the results can be assessed.
  3. [Section III.A and III.B] The paper reports no hyperparameter values (learning rate, number of epochs, number of output principal components), no preprocessing details for the UCI datasets, and no repeated runs or error bars. Instead, the paper selects the highest accuracy across four training/test splits as the headline result; this post hoc selection is not an independent measurement of GHA or of SpiNNaker and inflates the apparent improvement.
minor comments (5)
  1. [Title] The title spells the platform as 'Spinnaker'; it should be 'SpiNNaker' throughout the paper.
  2. [Section I, third paragraph] The phrase 'By offers numerous advantages as an extension of the classical Hebbian learning rule' is ungrammatical and should be revised to 'It offers numerous advantages as an extension of the classical Hebbian learning rule.'
  3. [Section I, fourth paragraph] The sentence 'making it ideal platform for Neuromorphic computing' should read 'making it an ideal platform for neuromorphic computing.'
  4. [Section III.B, paragraph after Table II] The claims that GHA has higher memory usage and training time than HA are unsupported because Table II is empty in the manuscript.
  5. [Section II.C] Reference [10] appears truncated, and the GHA description would be clearer with a formal pseudocode listing or numbered equations for the update rule.

Circularity Check

0 steps flagged · score 0.0 of 10

No circular derivation: the paper is an empirical comparison with a serious training-split confound, but its claims do not reduce to their inputs by construction.

full rationale

This paper does not contain a derivation chain of the kind that can be circular. The Generalized Hebbian Algorithm is presented by citing Sanger's external algorithm and convergence theorem (reference [10]), and the SpiNNaker hardware properties are cited from Furber et al. (reference [22]). Neither is re-derived, and neither load-bearing algorithmic step is justified by a self-citation. The authors' many self-citations appear only in the future-work section, where they argue that FPGA-based systems are a good avenue for future GHA acceleration; that is not load-bearing for the paper's central accuracy claim. The central empirical claim compares 80.56% accuracy at a 30% training split with SpiNNaker against 72.80% at an 80% training split without SpiNNaker, and the text explicitly states that 'the main change was the adjustment of the training and test data split.' This is a genuine experimental confound and a correctness risk, but it is not circularity: the reported accuracy is not a fitted parameter renamed as a prediction, nor is any equation equivalent to its own input by construction. The mismatched table captions ('ON HEBBIAN LEARNING ALGORITHM' in Tables IV-VII while the narrative describes GHA results) are internal consistency problems, not circular reasoning. Because no load-bearing step reduces to its own inputs, the circularity score is 0.

Assumptions & free parameters 4 free parameters · 3 assumptions · 0 invented entities

The central claim depends on the GHA convergence theorem, on an unspecified mapping to SpiNNaker, and on post hoc split selection. No new entities are introduced.

free parameters (4)
  • train/test split ratio = 30/70 for best with-SpiNNaker result; 80/20 for best without-SpiNNaker result
    The paper searches over four splits and reports the best accuracy; the split is a free choice that determines the headline result.
  • learning rate
    Not specified in the paper; GHA requires a learning rate that affects convergence and accuracy.
  • number of epochs
    Not specified; convergence is claimed but no epoch count is given.
  • number of output principal components
    GHA maps to M eigenvectors; the choice of M for classification is unspecified.
assumptions (3)
  • standard math GHA converges to the eigenvectors of the input autocorrelation matrix (Sanger's rule theorem)
    Paper cites [10] and relies on this convergence to interpret the learned weights.
  • domain assumption SpiNNaker simulation preserves GHA learning dynamics without significant numerical deviation
    The paper compares accuracy with and without SpiNNaker but does not describe how GHA is mapped to spiking hardware or whether fixed-point arithmetic alters the result.
  • domain assumption A single deterministic train/test split adequately estimates generalization performance
    The paper reports a single split per condition and treats the resulting accuracy as a stable performance measure.

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Cite this review

Pith. "Pith review of Analysis of Generalized Hebbian Learning Algorithm for Neuromorphic Hardware Using Spinnaker." pith.science (2026). https://pith.science/paper/KCSS2ZZS

@misc{pith2026241111575,
  author       = {Pith},
  title        = {Pith review of: Analysis of Generalized Hebbian Learning Algorithm for Neuromorphic Hardware Using Spinnaker},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/KCSS2ZZS}},
  note         = {Machine review of arXiv:2411.11575}
}
read the original abstract

Neuromorphic computing, inspired by biological neural networks, has emerged as a promising approach for solving complex machine learning tasks with greater efficiency and lower power consumption. The integration of biologically plausible learning algorithms, such as the Generalized Hebbian Algorithm (GHA), is key to enhancing the performance of neuromorphic systems. In this paper, we explore the application of GHA in large-scale neuromorphic platforms, specifically SpiNNaker, a hardware designed to simulate large neural networks. Our results demonstrate significant improvements in classification accuracy, showcasing the potential of biologically inspired learning algorithms in advancing the field of neuromorphic computing.

Figures

Figures reproduced from arXiv: 2411.11575 by the authors.

Figure 1
Figure 1. Comparison Factors for Hebbian learning Algorithm and Generalized Hebbian learning Algorithm. 1) Quantitative Analysis: There are three metrics involved : average convergence rate is the measure of quickly algorithm converges to stable solution. Error rate is the measure of how well the network captures and reproduces the input patterns and Computational Complexity includes memory [PITH_FULL_IMAGE:figures/full_fig_… view at source ↗

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Forward citations

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    J.R. Graf and D.G. Perera, “Optimizing Density -Based Ant Colony Stream Clustering Using FPGA -Based Hardware Accelerator”, in Proc. Of IEEE Int . Symp. on Circuits and Systems (ISCAS’23), 5- page manuscript, Monterey, California, May 2023

    2023

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    Efficient Embedded Architectures for Model Predictive Controller for Battery Cell Management in Electric Vehicles

    A.K. Madsen and D.G. Perera, “Efficient Embedded Architectures for Model Predictive Controller for Battery Cell Management in Electric Vehicles”, EURASIP Journal on Embedded Systems, SpringerOpen, vol. 2018, article no. 2, 36-page manuscript, July 2018

    2018

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    An Optimized FPGA - Based Hardware Accelerator for Physics -Based EKF for Battery Cell Management

    A.K. Madsen, M.S. Trimboli, and D.G. Perera, “An Optimized FPGA - Based Hardware Accelerator for Physics -Based EKF for Battery Cell Management”, in Proc . of IEEE Int ,l Symp , on Circuits and Systems, (ISCAS’20), 5-page manuscript, Seville, Spain, May 2020

    2020

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    Towards Composing Efficient FPGA - Based Hardware Accelerators for Physics -Based Model Predictive Control Smart Sensor for HEV Battery Cell Management

    A.K. Madsen and D.G. Perera, “Towards Composing Efficient FPGA - Based Hardware Accelerators for Physics -Based Model Predictive Control Smart Sensor for HEV Battery Cell Management”, IEEE ACCESS, (Open Access Journal in IEEE), pp. 106141- 106171, 25th September 2023

    2023

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    Composing Optimized Embedded Software Architectures for Physics -Based EKF -MPC Smart Sensor for Li-Ion Battery Cell Management

    A.K. Madsen and D.G. Perera, “Composing Optimized Embedded Software Architectures for Physics -Based EKF -MPC Smart Sensor for Li-Ion Battery Cell Management”, Sensors, MDPI open access journal, Intelligent Sensors Section, 21- page manuscript, vol. 22, no. 17, 26th August 2022

    2022

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    Efficient FPGA -Based Reconfigurable Accelerators for SIMON Cryptographic Algorithm on Embedded Platforms

    A. Alkamil and D.G. Perera, “Efficient FPGA -Based Reconfigurable Accelerators for SIMON Cryptographic Algorithm on Embedded Platforms”, in Proceedings of the IEEE International Conferences on Reconfigurable Computing and FPGAs, (ReConFig’19), 8- page manuscript, Cancun, Mexic...

    2019

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    Towards Dynamic and Partial Reconfigurable Hardware Architectures for Cryptographic Algorithms on Embedded Devices

    A. Alkamil and D.G. Perera, “Towards Dynamic and Partial Reconfigurable Hardware Architectures for Cryptographic Algorithms on Embedded Devices”, IEEE Access, Open Access Journal in IEEE, vol. 8, pp: 221720 – 221742, 10th December 2020

    2020

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    An FPGA -Based Hardware Accelerator for K-Nearest Neighbor Classification for Machine Learning on Mobile Devices

    M.A. Mohsin and D.G. Perera, “An FPGA -Based Hardware Accelerator for K-Nearest Neighbor Classification for Machine Learning on Mobile Devices”, in Proceedings of the IEEE/ACM International Symposium on Highly Efficient Accelerators and Reconfigurable Techn ologies, (HEART’18)...

    2018

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    An Efficient FPGA -Based Hardware Accelerator for Convex Optimization-Based SVM Classifier for Machine Learning on Embedded Platforms

    S. Ramadurgam and D.G. Perera, “An Efficient FPGA -Based Hardware Accelerator for Convex Optimization-Based SVM Classifier for Machine Learning on Embedded Platforms”, Electronics, MDPI open access journal, 36-page manuscript, vol. 10, no. 11, 31st May 2021

    2021

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    A Systolic Array Architecture for SVM Classifier for Machine Learning on Embedded Devices

    S. Ramadurgam and D.G. Perera, “A Systolic Array Architecture for SVM Classifier for Machine Learning on Embedded Devices”, in Proc . of IEEE Int . Symp. on Circuits and Systems (ISCAS’23), 5- page manuscript, Monterey, California, May 2023

    2023

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    Intelligent Cognitive Radio Architecture Applying Machine Learning and Reconfigurability

    J. Nurmi and D.G. Perera, “Intelligent Cognitive Radio Architecture Applying Machine Learning and Reconfigurability” in Proc . of IEEE Nordic Circuits and Systems (NorCAS'21) Conf ., 6 -page manuscript, Oslo, Norway, October 2021

    2021

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    Reconfigurable Architectures for Data Analytics on Next - Generation Edge -Computing Platforms

    D.G. Perera, “Reconfigurable Architectures for Data Analytics on Next - Generation Edge -Computing Platforms”, Featured Article, IEEE Canadian Review, vol. 33, no. 1, Spring 2021. DOI: 10.1109/MICR.2021.3057144

    2021

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    Composing Efficient Computational Models for Real -Time Processing on Next -Generation Edge-Computing Platforms

    M.A. Mohsin, S.N. Shahrouzi, and D.G. Perera, “Composing Efficient Computational Models for Real -Time Processing on Next -Generation Edge-Computing Platforms” IEEE ACCESS, (Open Access Journal in IEEE), 30-page manuscript, 13th February 2024

    2024

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    Neuromorphic Sentiment Analysis Using Spiking Neural Networks

    R.K. Chunduri and D.G. Perera, “Neuromorphic Sentiment Analysis Using Spiking Neural Networks”, Sensors, MDPI open access journal, Sensing and Imaging Section, 24-page manuscript, vol. 23, no. 7701, 6th September 2023

    2023

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    A Fast and Scalable FPGA-Based Parallel Processing Architecture for K-Means Clustering for Big Data Analysis

    R. Raghavan and D.G. Perera, “A Fast and Scalable FPGA-Based Parallel Processing Architecture for K-Means Clustering for Big Data Analysis”, in Proceedings of the IEEE Pacific Rim International Conference on Communications, Computers, and Signal Processing, (PacRim’17), pp. 1-...

    2017

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    Parallel Computation of Similarity Measures Using an FPGA -Based Processor Array,

    D.G. Perera and Kin F. Li, “Parallel Computation of Similarity Measures Using an FPGA -Based Processor Array,” in Proceedings of 22nd IEEE International Conference on Advanced Information Networking and Applications, (AINA’08), pp. 955- 962, Okinawa, Japan, March 2008

    2008

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    A Design Methodology for Mobile and Embedded Applications on FPGA -Based Dynamic Reconfigurable Hardware

    D.G. Perera and K.F. Li, “A Design Methodology for Mobile and Embedded Applications on FPGA -Based Dynamic Reconfigurable Hardware”, International Journal of Embedded Systems, (IJES), Inderscience publishers, 23-page manuscript, vol. 11, no. 5, Sept . 2019

    2019

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    Analysis of FPGA -Based Reconfiguration Methods for Mobile and Embedded Applications

    D.G. Perera, “Analysis of FPGA -Based Reconfiguration Methods for Mobile and Embedded Applications”, in Proceedings of 12th ACM FPGAWorld International Conference, (FPGAWorld’15), pp. 15- 20, Stockholm, Sweden, September 2015

    2015

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    Discrepancy in Execution Time: Static Vs. Dynamic Reconfigurable Hardware

    D.G. Perera and K.F. Li, “Discrepancy in Execution Time: Static Vs. Dynamic Reconfigurable Hardware”, IEEE Pacific Rim Int . Conf. on Communications, Computers, and Signal Processing, (PacRim’24), 6- page manuscript, Victoria, BC, Canada, August 2024

    2024

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    FPGA -Based Reconfigurable Hardware for Compute Intensive Data Mining Applications

    D.G. Perera and Kin F. Li, “FPGA -Based Reconfigurable Hardware for Compute Intensive Data Mining Applications”, in Proc. of 6th IEEE Int. Conf. on P2P, Parallel, Grid, Cloud, and Internet Computing, (3PGCIC’11), pp. 100-108, Barcelona, Spain, October 2011

    2011

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    Similarity Computation Using Reconfigurable Embedded Hardware,

    D.G. Perera and Kin F. Li, “Similarity Computation Using Reconfigurable Embedded Hardware,” in Proceedings of 8th IEEE International Conference on Dependable, Autonomic, and Secure Computing (DASC’09), pp. 323-329, Chengdu, China, December 2009

    2009

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    Dynamic Partial Reconfigurable Hardware Architecture for Principal Component Analysis on Mobile and Embedded Devices

    S.N. Shahrouzi and D.G. Perera, “Dynamic Partial Reconfigurable Hardware Architecture for Principal Component Analysis on Mobile and Embedded Devices”, EURASIP Journal on Embedded Systems, SpringerOpen, vol. 2017, article no. 25, 18- page manuscript, 21st February 2017

    2017

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    HDL Code Optimization: Impact on Hardware Implementations and CAD Tools

    S.N Shahrouzi and D.G. Perera, “HDL Code Optimization: Impact on Hardware Implementations and CAD Tools”, in Proc . of IEEE Pacific Rim Int. Conf. on Communications, Computers, and Signal Processing, (PacRim’19), 9-page manuscript, Victoria, BC, Canada, August 2019

    2019

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    HDL Code Variation: Impact on FPGA Performance Metrics and CAD Tools

    I.D. Atwell and D.G. Perera, “HDL Code Variation: Impact on FPGA Performance Metrics and CAD Tools”, IEEE Pacific Rim Int. Conf. on Communications, Computers, and Signal Processing, (PacRim’24), 6- page manuscript, Victoria, BC, Canada, August 2024

    2024

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    Towards Composing Optimized Bi- Directional Multi -Ported Memories for Next -Generation FPGAs

    S.N. Shahrouzi, A. Alkamil, and D.G. Perera, “Towards Composing Optimized Bi- Directional Multi -Ported Memories for Next -Generation FPGAs”, IEEE Access, Open Access Journal in IEEE, vol. 8, no. 1, pp. 91531-91545, 14th May 2020

    2020

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    An Efficient Embedded Multi -Ported Memory Architecture for Next -Generation FPGAs

    S.N. Shahrouzi and D.G. Perera, “An Efficient Embedded Multi -Ported Memory Architecture for Next -Generation FPGAs”, in Proceedings of 28th Annual IEEE International Conferences on Application- Specific Systems, Architectures, and Processors, (ASAP’17), pp. 83- 90, Seattle, W...

    2017

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    An Efficient FPGA -Based Memory Architecture for Compute -Intensive Applications on Embedded Devices

    S.N. Shahrouzi and D.G. Perera, “An Efficient FPGA -Based Memory Architecture for Compute -Intensive Applications on Embedded Devices”, in Proceedings of the IEEE Pacific Rim International Conference on Communications, Computers, and Signal Processing, (PacRim’17), pp. 1-8, Vi...

    2017

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    Optimized Counter-Based Multi-Ported Memory Architectures for Next -Generation FPGAs

    S.N. Shahrouzi and D.G. Perera, “Optimized Counter-Based Multi-Ported Memory Architectures for Next -Generation FPGAs”, in Proceedings of the 31st IEEE International Systems -On-Chip Conference, (SOCC’18), pp. 106-111, Arlington, VA, Sep. 2018

    2018

Pith tools

Reviewed August 12, 2026 · model on record in the stance chip above.