Mitigating Compiler Fusion-Induced Power Bursts in Mobile NPU Inference as the Battery Depletes

Masayoshi Tomizuka; Ryoga Yuzawa

REVIEW 3 major objections 5 minor 28 references

Compiler fusion on mobile NPUs can cause current bursts that trigger early throttling; splitting at peak-power hot spots restores low-voltage operating margin.

Reviewed by Pith at T0; open to challenge. T0 means a machine referee read the full paper against a public rubric. the ladder, T0–T4 →

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T0 review · deepseek-v4-flash

2026-08-01 20:37 UTC pith:KCWND6H4

load-bearing objection Honest, well-scoped measurement study; the 173 mV headline is a fitted estimate, but the direct within-model sweep in Fig. 6 carries the argument — worth serious refereeing. the 3 major comments →

arxiv 2607.16555 v1 pith:KCWND6H4 submitted 2026-07-17 cs.AR cs.AI

Mitigating Compiler Fusion-Induced Power Bursts in Mobile NPU Inference as the Battery Depletes

Ryoga Yuzawa , Masayoshi Tomizuka This is my paper

classification cs.AR cs.AI

keywords mobile NPUoperator fusionvoltage droopDVFSpeak currentPAPRpower integritylow-voltage inference

verification ladder T0 review T1 audit T2 compute T3 formal T4 reserved

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

This paper establishes that aggressive operator fusion in a mobile NPU compiler can fuse consecutive layers into monolithic superlayers whose concentrated execution produces large peak-current bursts. Through the power-delivery network, these bursts cause voltage droops that trigger hardware DVFS throttling at higher supply voltages, shrinking the usable low-voltage operating range as the battery depletes. On a Snapdragon 8 Gen 3 smartphone, the authors measure this effect and show that a measurement-guided pre-compilation graph rewrite—inserting quantize–dequantize barriers at selected peak-to-average power ratio (PAPR) hot spots—reduces peak current from 3.12 A to 1.94 A (−37.8%) with only 3.76% latency overhead. The split model maintains stable latency down to about 3.28 V where the original throttles at about 3.45 V, corresponding to an inferred DVFS margin improvement of about 173 mV. If correct, this means efficient, aggressively fused models are not automatically voltage-stable, and compiler-level waveform shaping is a viable, retraining-free lever for extending low-battery inference.

Core claim

The central claim is that fusion-induced current transients, not just average power, are a measurable determinant of low-voltage DVFS onset on a commercial mobile NPU. The paper shows that the vendor compiler's fusion of UIR blocks in MobileNetV4 creates a superlayer with PAPR about 2.6, causing a deep rail droop that pushes the PMIC input voltage below the hardware threshold. Splitting that superlayer at four Q-DQ barriers reduces the current peak, shifting the measured DVFS-onset voltage downward by roughly 147 mV per amp of peak-current reduction. The result is a 173 mV wider low-voltage operating margin on the tested device.

What carries the argument

The key machinery is the PAPR-guided boundary selection algorithm (Algorithm 1). It computes the peak-to-average power ratio of the measured current waveform, identifies compile-feasible graph edges adjacent to PAPR hot spots (PAPR ≥ γ, with γ = 2.0), ranks them by local peak current, and greedily inserts up to K quantize–dequantize operator pairs as barriers that the vendor compiler cannot fold away. This breaks monolithic superlayers without retraining, weight changes, or compiler modification. The quantitative link between peak current and DVFS onset is an exploratory linear fit of 0.147 V/A, used to derive the ≈173 mV margin improvement.

Load-bearing premise

The load-bearing premise is the 0.147 V/A linear association between peak current and DVFS-onset voltage, fit to five measurements per bin across different models without confidence intervals or causal controls; all derived margin improvements, including the 173 mV estimate, rest on this slope. A second premise is that driving the PMIC rail from a low-impedance bench supply reproduces the DVFS and shutdown engagement voltages of a real battery.

What would settle it

Measure DVFS-onset voltage for two configurations of the same model that differ in peak current by about 1 A while keeping average power and kernel structure matched. If the observed shift in DVFS-onset voltage is not close to ~147 mV, the linear model and the derived margin improvement are wrong. Alternatively, on a device where the hardware protection threshold is fixed and independent of rail droop, the claimed shift would not appear.

Watch this falsifier — get emailed when new claim-graph text bears on it.

If this is right

Compiler fusion decisions that optimize throughput can inadvertently create voltage hazards; future NPU compilers may need to consider transient current waveforms, not just average power or latency.
A black-box, measurement-guided graph rewrite can extend the low-battery operating window without retraining or changing the model weights; the 37.8% peak-current reduction and <4% latency overhead suggest this is deployable.
The method is complementary to vendor frequency capping: combining the proposed split with sustained mode gives a 52.2% peak reduction, while splitting alone preserves burst-mode latency better than capping alone.
On models or resolutions with PAPR below about 2.0, splitting is not worthwhile—latency overhead climbs 25–36% for little peak benefit—so the PAPR threshold acts as a practical deployment gate.
Accuracy impact is small: worst-case −0.31 pp Top-1 on ImageNet-1k, supporting use in accuracy-sensitive camera and perception workloads.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

If the DVFS-onset relationship is causal and portable, the ~173 mV margin could translate into meaningfully longer usable operation near end-of-discharge, but the paper does not measure actual battery runtime; this is a testable extension.
The one-time offline profiling per model–resolution–compiler configuration could be replaced by static PAPR prediction from operator-graph features, removing the need for per-model measurement—an avenue the paper lists as future work.
The same Q-DQ barrier mechanics might be applied to other voltage-sensitive phases of mobile execution, such as GPU or CPU bursts, but the paper only demonstrates NPU inference.
Because the fit is descriptive and on one SoC, devices with different PDN impedance or DVFS policies may need their own calibration; the method's benefit likely scales with how aggressively the compiler fuses layers.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit.

Desk Editor's Note

Honest, well-scoped measurement study; the 173 mV headline is a fitted estimate, but the direct within-model sweep in Fig. 6 carries the argument — worth serious refereeing.

read the letter

This is a genuinely useful paper. The new thing is the measurement itself: on a commodity Snapdragon 8 Gen 3, aggressive NPU compiler fusion creates current bursts that push DVFS onset to higher supply voltages, and a pre-compilation graph rewrite that inserts Q–DQ barriers at high-PAPR boundaries reduces peak current by ~38% with under 4% latency overhead. That combination — measured current-waveform feedback into a vendor compiler's fusion decisions — is new, and the PAPR-gated splitting clearly beats equal-interval and random baselines. The paper is also refreshingly honest: Section 5.7 flags most of the real limitations, and the regression in Fig. 4 is explicitly labeled an association, not a causal estimate.

The soft spots are real but not fatal. The headline 173 mV margin is a derived quantity: 1.18 A times a fitted 147 mV/A slope from six configurations with n=5 per bin and no confidence interval. As a headline number it is over-sold — and the stress-test is right that peak current is correlated with total energy, so the slope could be partly confounded. But the paper's central claim does not actually rest on that regression. Figure 6 shows a direct within-model voltage sweep: the split version maintains stable latency down to ~3.28 V, while the original throttles around 3.45 V. That is a single experiment, but it holds the model fixed and isolates the effect of the split, so it is far more convincing than the fitted number. My advice to the authors would be to make Fig. 6 the primary evidence and demote Eq. (5) to a sanity check.

Other gaps: no code or artifacts released, so replication requires rebuilding a proprietary-toolchain rig; the γ=2.0 gate is tuned on the same configurations it is evaluated on, with no held-out model–resolution–compiler test; and accuracy impact was measured at 448×448, not at the deployment resolution of 768×768. These are structural, not stylistic, and the authors acknowledge most of them.

Who gets value: systems researchers working on mobile NPU power integrity, compiler engineers thinking about energy-aware fusion, and anyone deploying always-on camera/perception workloads. It deserves a serious referee — the measurements are internally consistent and the direct evidence supports the qualitative claim. I would send it out with a request to rebalance the presentation toward Fig. 6 and to release whatever artifacts they can.

Referee Report

3 major / 5 minor

Summary. The paper presents a measurement study on a Snapdragon 8 Gen 3 mobile NPU showing that aggressive compiler fusion creates high peak-current bursts, which shift DVFS-onset to higher voltages and reduce the low-voltage operating margin. The authors propose a black-box mitigation: a measurement-guided pre-compilation graph rewrite that inserts Quantize–Dequantize barriers at PAPR-ranked fusion boundaries to prevent harmful superlayer merging. On MobileNetV4@768, they report a 37.8% peak-current reduction (3.12 A to 1.94 A) with 3.76% latency overhead, and infer a ~173 mV improvement in DVFS margin via a linear regression between peak current and DVFS-onset voltage.

Significance. If the results hold, this is a valuable and non-obvious finding: it identifies compiler fusion---not just workload size or average power---as a controllable cause of voltage-transient hazards in mobile NPU inference, and it offers a practical, weight-preserving mitigation that works without modifying the vendor compiler or hardware. The paper's strengths include synchronized current/voltage/latency measurements on real hardware, a within-model comparison (Fig. 6) that directly shows the split version maintaining stable latency at lower voltages, and an honest limitations section that flags the exploratory nature of the regression. The work is most convincing qualitatively; the quantitative voltage-margin claim is the weakest link.

major comments (3)

[§4.2.2, Fig. 6] The headline ~173 mV margin is computed as 1.18 A × 147 mV/A, where 147 mV/A is an exploratory linear fit with no confidence interval, no hypothesis test, and no control for confounders. Table 1 shows a strong correlation between peak current and energy per inference (e.g., MNV4@1024: 3.04 A and 205.8 mJ vs. MNV4@224: 1.99 A and 9.6 mJ), so the fitted slope could partly reflect inference duration, average power, or kernel identity rather than the causal effect of peak current. Since the abstract and conclusion present 173 mV as a primary quantitative result, this is load-bearing. The within-model Fig. 6 evidence is stronger and should be the primary support; the regression-derived number should either be given proper statistical treatment (with confounder adjustment and uncertainty) or be explicitly demoted to an illustrative estimate.
[§5.3, §5.4] The voltage-sweep protocol drives the PMIC input rail with an external programmable supply. The paper attributes DVFS onset to momentary droops of Vterm(t) caused by current transients; however, replacing the battery with a low-impedance bench supply removes the battery's internal impedance and changes the PDN transient response. The measured DVFS-onset voltages may therefore not match what a real depleting battery would produce, especially since the title emphasizes battery depletion. The authors should characterize the supply's output impedance versus the battery's, or at minimum discuss how the external supply affects the droop mechanism and include a real-battery low-SOC validation if the quantitative voltage claims are to be supported.
[§4.2, Fig. 4] The deployment threshold γ = 2.0 and the selection of MobileNetV4@768 as the favorable operating point are derived from the same six model–resolution configurations used to report the main result. The Hiera-Tiny results show that forced splitting can degrade behavior (e.g., Hiera@384 PAPRmax increases from 1.66 to 1.91 with no peak reduction), which demonstrates that the threshold is not universally beneficial but is being tuned post hoc on the evaluation set. A held-out configuration or a more systematic model-selection procedure would be needed to claim an 'empirical operating threshold' rather than a data-dependent observation.

minor comments (5)

[§5.2, Fig. 1] The acronym for the MobileNetV4 block is inconsistent: 'UIB' appears in Fig. 1, while the text uses 'UIR'. Please unify.
[References] Reference [4] lists 'Guilio Zhou'; the correct spelling is 'Giulio Zhou'.
[Fig. 6] Each plotted point is an average of 100 inferences, but no variance or error bars are shown. Adding standard deviations or confidence bands would strengthen the figure, particularly because the paper elsewhere emphasizes statistical caution.
[§3.2] The claim that Q–DQ pairs are needed because the vendor compiler folds Identity and Reshape nodes would be more convincing with a short compiled-graph or timing trace showing that a plain identity barrier is indeed fused away.
[§4.2.1] The software-protection description states that throttling fires 'when SoC approaches about 5%' without a citation or measured evidence; please add a reference or a measurement of the SoC threshold.

Circularity Check

0 steps flagged

No significant circularity: the paper's central claims rest on direct measurements, and the regression-derived 173 mV margin is explicitly labeled exploratory and corroborated by a direct voltage sweep.

full rationale

The paper's derivation chain is measurement-driven rather than definitionally circular. The claim that compiler fusion creates peak-current bursts is supported by direct synchronized current/voltage/latency measurements (Fig. 5, §5.2), and the mitigation's effect is shown by measured peak-current reductions (Table 1) and by a within-model voltage sweep (Fig. 6) in which the split version maintains stable latency about 170 mV lower than the original. The headline ~173 mV figure (Eq. 5) is computed as 1.18 A × 147 mV/A, where 147 mV/A is an exploratory linear fit to the Fig. 4 data. However, the paper does not present this as an independent prediction: it explicitly calls the fit 'an association rather than an isolated causal estimate' (§5.1) and states in §5.7 that 'the 147 mV/A slope and the derived 173 mV margin are exploratory estimates rather than calibrated transfer laws.' The margin is a derived quantity from a fitted slope, not a fitted parameter renamed as a prediction, and it is not the sole basis for the central claim—direct Fig. 6 evidence provides independent, model-held-constant support. There is no self-citation chain: the reference list contains no prior work by Yuzawa or Tomizuka. The PDN transient model (Eq. 1) is a standard R-L circuit model cited to external literature [7], not an ansatz smuggled in via self-citation. The PAPR threshold γ=2.0 is selected from the same exploratory measurements used to evaluate the method, which creates a selection-bias risk, but selection bias is not definitional circularity. No step in the paper reduces by construction to its own inputs, so no circular step meets the quoted-reduction bar.

Axiom & Free-Parameter Ledger

4 free parameters · 6 axioms · 1 invented entities

The paper is measurement-driven, so the ledger is dominated by fitted and empirical choices: the DVFS-onset slope (147 mV/A) that produces the headline 173 mV via Eq. (5), the PAPR gate γ=2.0 chosen from the same exploratory data it gates, and the barrier budget K=4. Modeling axioms are standard (series R-L PDN) or empirically validated on the single test device (Q-DQ non-fusibility). Structural exposures: the onset regression cannot separate peak-current from model-level confounders; the bench supply omits battery internal-resistance dynamics; accuracy impact of Q-DQ is measured at 448×448, not at the 768×768 deployment point.

free parameters (4)

PAPR deployment threshold gamma = 2.0
'This exploratory dichotomy suggests an empirical operating threshold near PAPRmax ≈ 2.0' (§5.3). The gate is derived from the same six configurations it then classifies into beneficial (17–40% peak reduction) vs overhead (25–36% latency increase) regimes; no held-out configuration validates it.
Barrier budget K = 4
Cap on inserted barriers in Algorithm 1, chosen in the trade-off analysis ('budget K=4 identified as effective', §5.4) and used for all evaluations including the forced-split characterization (|Beval| ≤ K = 4, §5.3). It directly bounds latency overhead.
DVFS-onset sensitivity slope = 0.147 V/A
Exploratory linear fit of DVFS-onset voltage vs peak current (Fig. 4, §5.1), n=5 per bin across models, no CI or hypothesis test. Multiplied by the measured 1.18 A peak reduction in Eq. (5) to produce the headline 'approximately 173 mV' margin improvement.
Inter-frame wait duration = not reported
Waits inserted between frames 'to equalize average power across models while keeping each DNN's instantaneous peak current distinct' (§4.2). The causal attribution of DVFS onset to peak current depends on this equalization; the duration is unspecified, so the exposure is not auditable.

axioms (6)

domain assumption PDN transient model: ΔV(t) ≈ R·I(t) + L·dI/dt (Eq. 1)
Standard series R-L power-delivery model invoked in §3.1; the R and L terms are not measured separately, so all effects are lumped into the observed DVFS-onset voltage.
domain assumption Current PAPR is proportional to power PAPR ('supply-rail voltage is approximately constant during a single inference', §3.2)
Justifies PAPR = I(t)/Ī as a stress proxy on the measured device; asserted rather than verified per superlayer.
domain assumption Hardware protection (DVFS/near-halt) engages when Vterm(t) crosses a hardware threshold, independent of displayed SoC (§4.2.2)
The mechanistic link from current bursts to throttling; supported by the voltage-sweep behavior but not by an independent probe of the threshold.
domain assumption Q-DQ operator pairs are not folded by Qualcomm HTP, while Identity/Reshape are merged (§3.2)
Compiler-specific empirical behavior validated by the per-edge feasibility probing; required for the barrier mechanism to function.
domain assumption Bench supply at the PMIC rail reproduces a real cell's protection-engagement behavior (§4.2.2)
Voltage sweeps drive the rail with a DP832A supply instead of a Li-ion battery; a cell's internal resistance changes droop magnitude and absolute engagement voltage, an effect not analyzed.
standard math Battery OCV falls steeply at low state of charge (Fig. 2, from [16, 24])
Background electrochemistry taken from cited literature; presented schematically, not measured here.

invented entities (1)

Q-DQ barrier (Quantize–Dequantize operator pair) no independent evidence
purpose: Graph-level roadblock the vendor NPU compiler cannot fold away; forces harmful fused superlayers to split at PAPR-selected boundaries before compilation.
A rewrite artifact rather than a physical entity; its efficacy is demonstrated only on this paper's single device/toolchain, and it carries a −0.31 pp Top-1 accuracy cost the authors themselves flag as non-ideal, wishing for a zero-cost identity substitute (§3.2, Table 2).

pith-pipeline@v1.3.0-alltime-deepseek · 11438 in / 27716 out tokens · 262589 ms · 2026-08-01T20:37:42.130988+00:00 · methodology

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read the original abstract

Mobile devices increasingly rely on real-time NPU inference for camera and perception workloads. Under low-voltage conditions, however, a single inference can induce an instantaneous voltage droop in the power-delivery network, causing the power management integrated circuit to invoke dynamic voltage and frequency scaling (DVFS) and increase latency. We present a measurement study of this effect on a commercial smartphone. We show that aggressive operator fusion in a mobile NPU compiler can create monolithic superlayers whose concentrated execution produces large peak-current bursts. These bursts shift the DVFS-onset voltage upward and reduce the low-voltage operating margin. We further evaluate a practical black-box mitigation: a measurement-guided, pre-compilation graph rewrite that inserts barriers at selected peak-to-average power ratio hot spots to prevent harmful superlayer merging in the vendor NPU compiler. On Snapdragon 8 Gen 3 with MobileNetV4 at 768 x 768 resolution on ImageNet-1k, this method reduces peak current from 3.12 A to 1.94 A with 3.76% latency overhead, preserves stable latency deeper into the low-voltage regime, and shifts the inferred DVFS margin by approximately 173 mV.

Figures

Figures reproduced from arXiv: 2607.16555 by Masayoshi Tomizuka, Ryoga Yuzawa.

**Figure 2.** Figure 2: Li-ion terminal voltage vs. SOC (schematic, based on [ [PITH_FULL_IMAGE:figures/full_fig_p004_2.png] view at source ↗

**Figure 3.** Figure 3: Power measurement setup. The battery terminals are driven by an external supply (DP832A), and instantaneous [PITH_FULL_IMAGE:figures/full_fig_p006_3.png] view at source ↗

**Figure 4.** Figure 4: DVFS-onset voltage vs. peak current. Dots: all measurements per peak-current bin ( [PITH_FULL_IMAGE:figures/full_fig_p007_4.png] view at source ↗

**Figure 5.** Figure 5: Correspondence between PAPR (upper) and layer execution intervals (lower) in MobileNetV4 (768 [PITH_FULL_IMAGE:figures/full_fig_p008_5.png] view at source ↗

**Figure 6.** Figure 6: Applied voltage vs. average latency (MobileNetV4@768). Inference time is the average over every 100 [PITH_FULL_IMAGE:figures/full_fig_p010_6.png] view at source ↗

discussion (0)

Reference graph

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