Pith. sign in

REVIEW 3 major objections 5 minor 22 references

Ramping Up Open-Source RISC-V Cores: Assessing the Energy Efficiency of Superscalar, Out-of-Order Execution

T0 review · 3 major / 5 minor · reviewed 2026-08-07 · deepseek-v4-flash

Challenge this review Re-run · record.json Download PDF Read on arXiv ↗ Review JSON

Pith's one-line read An out-of-order RISC-V core can beat in-order cores on energy efficiency once clocks pass roughly 500 MHz, according to a controlled three-core comparison on the same SoC, the same 22 nm technology, and the same tools.

desk verdict A controlled same-technology comparison of three open-source RISC-V cores with a genuinely useful C910 port; the headline energy-efficiency claim is workload-dependent and needs tempering. read the letter →

arxiv 2505.24363 v1 pith:KUFWEE2P submitted 2025-05-30 cs.AR

Zexin Fu , Riccardo Tedeschi , Gianmarco Ottavi , Nils Wistoff , César Fuguet , Davide Rossi , Luca Benini This is my paper · ORCID
classification cs.AR
keywords RISC-Vout-of-orderexecutionsuperscalarenergyefficiencyopen-sourcehardwareXuanTieC910CVA622nmFDSOI
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

This paper tries to settle a practical question: does buying superscalar, out-of-order execution force you to surrender energy efficiency? The authors built the apples-to-apples comparison the field usually lacks — three open-source RISC-V cores, one out-of-order and two in-order, implemented in the same 22 nm FDSOI technology with the same EDA tools, integrated into the same open-source SoC, and run on identical benchmark binaries. They also did the enabling engineering: a XuanTie C910 core made fully RISC-V compliant in its debug, interrupt, and memory interfaces, and CVA6S+, a dual-issue superscalar CVA6 with register renaming, a two-level branch predictor, operand forwarding, and a working FPU, which gains 34.4% in IPC over vanilla CVA6 at a 6% area cost. The headline result is that energy efficiency (GOPS per watt) is not a simple in-order win: beyond roughly 500 MHz the out-of-order C910 overtakes both in-order cores, while the superscalar in-order CVA6S+ keeps the best area efficiency (GOPS per mm²). This matters because it contradicts the common belief that high-performance out-of-order execution inherently costs energy efficiency, and because the cores and SoC are open-source, so the measurement can be repeated and extended.

What carries the argument

The load-bearing mechanism is a same-everything comparison environment: the three cores drop into the same Cheshire SoC, are implemented in the same 22 nm FDSOI technology, go through the identical synthesis, place-and-route, and power-analysis flow, and run the same benchmark binaries compiled with the same toolchain, so the microarchitecture is the only variable. Inside that frame, the decisive objects are the two modified cores: the C910 stripped of its proprietary interrupt, debug, and AXI-ACE memory protocol and made fully RISC-V compliant, and CVA6S+, the dual-issue in-order CVA6 enhanced with register renaming, a two-level branch predictor, ALU-to-ALU operand forwarding, and FPU integration. The argument is carried by the frequency-swept efficiency curves — GOPS per watt versus target frequency — which reveal the crossover near 500 MHz where the deeper-pipeline out-of-order core's higher IPC per watt overtakes the simpler in-order designs.

What would settle it

Re-run the same GOPS-per-watt frequency sweep with a memory-bound workload under a realistic, nonzero-latency memory model (for example, RaiderSTREAM scatter/gather with cold caches) and check whether the C910 curve still crosses the in-order curves near 500 MHz; if the crossover disappears or climbs above 1 GHz, the general claim is refuted.

Watch

Extended reading notes

Core claim

The paper's central claim is that the XuanTie C910, a 12-stage, three-issue out-of-order core, becomes more energy-efficient than in-order cores once the clock target passes 500 MHz: 'beyond the 500 MHz timing target, the C910 core surpasses in-order cores in energy efficiency' (Section 6). Measured on the same Cheshire SoC in 22 nm FDSOI, the C910 reaches an average IPC of 1.61 and 4.86 Coremark/MHz, versus 0.70 and 2.19 for the vanilla single-issue CVA6, at a 75% area increase — yet its power draw stays competitive at high frequency, and it achieves the highest maximum frequency of the three (1718 MHz at the fast corner, against 1340 MHz and 1227 MHz for CVA6 and CVA6S+). The frequency-swept efficiency data show all three cores' GOPS/W first rising and then falling as timing constraints tighten, with the out-of-order core's curve crossing above the in-order cores' beyond 500 MHz. The authors read this as a direct challenge to the long-standing assumption that superscalar and out-of-order execution inherently carries a significant energy-efficiency penalty.

Load-bearing premise

The energy-efficiency crossover is measured on one compute-intensive benchmark (matmult-int) over a 30,000-cycle power window and against an idealized main memory with no latency, so the claim that out-of-order execution wins above 500 MHz could fail for workloads that stall on memory or branches.

Editorial extensions

If this is right

  • If the crossover claim holds, a designer targeting clocks above roughly 500 MHz can pick an out-of-order core without assuming an energy penalty: its performance per watt is higher, not lower, than the in-order alternatives.
  • The in-order superscalar design point (CVA6S+) delivers the best area efficiency (GOPS/mm²) and the best combined area-energy efficiency, making it the rational choice when silicon area is the binding constraint.
  • Because every core's energy efficiency peaks at an intermediate frequency and then falls as timing closure forces low-threshold cells into the design, the operating frequency itself becomes a first-order efficiency control.
  • With the C910's debug, interrupt, and memory interfaces made RISC-V-standard-compliant, the open-source out-of-order design becomes usable with standard industrial EDA flows, the Cheshire software stack, and Linux, removing the integration barriers that previously excluded it from open-source SoCs.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • My extension: the frequency sweep that produces the crossover is built on a single compute-intensive benchmark (matmult-int). Repeating the sweep with a branch-heavy kernel (statemate) or a floating-point kernel (nbody) would likely move the crossover, since those workloads exercise the out-of-order core's extra fetch, issue, and retirement machinery differently.
  • My extension: the ideal, zero-latency main memory probably favors the out-of-order core, whose deep reorder buffer and large load/store queues exist precisely to hide memory latency. A realistic DRAM latency model is the natural stress test and could push the crossover above 500 MHz or erase it entirely.
  • My extension: if the effect scales, the crossover frequency between in-order and out-of-order energy efficiency may drift downward on smaller process nodes, because deeper pipelines gain more frequency headroom while the relative energy cost of wide issue and retirement logic changes; this is testable by repeating the same setup on the next generation of these open-source cores.
Share X Bluesky LinkedIn Reddit HN

Signed reviews

No signed human review yet.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

3 major / 5 minor

Summary. The paper presents a controlled comparison of three open-source RISC-V cores—the single-issue in-order CVA6, the dual-issue in-order CVA6S+ (an enhanced superscalar variant), and the out-of-order XuanTie C910—implemented in GF22FDX technology and integrated into the same Cheshire SoC. The authors modify the C910 to achieve RISC-V standard compliance in its interrupt, debug, and memory interfaces, and they add register renaming, branch prediction, operand forwarding, and FPU integration to create CVA6S+. Using identical tools, technology, and benchmarks, they report performance (IPC, Coremark/MHz, RaiderSTREAM bandwidth), timing, area, power, and energy-efficiency results. The central claim is that out-of-order execution is not inherently much less energy-efficient than in-order execution: beyond a 500 MHz timing target, the C910 surpasses the in-order cores in energy efficiency (GOPS/W), while CVA6S+ remains the most area-efficient design.

Significance. If the results hold, the paper makes a valuable contribution to the open-source RISC-V ecosystem: it provides a RISC-V-compliant C910 variant with a clean integration path, a publicly described CVA6S+ microarchitecture, and one of the most carefully controlled apples-to-apples comparisons of in-order and out-of-order RISC-V cores to date. The methodological strengths are substantial: same ISA, same SoC platform, same 22nm technology, same EDA tools and flow, and the same benchmark binaries across all three cores. The detailed area and power breakdowns and the open-source release plans enhance reproducibility. The quantitative area and performance trends are internally consistent, and the paper clearly identifies the microarchitectural components responsible for the power and area overheads. These strengths make the paper a useful reference for core selection and for future open-source high-performance RISC-V designs.

major comments (3)
  1. [Section 5.5, Figure 8(b), Section 6] The energy-efficiency crossover that supports the central claim is computed from power measurements of a single benchmark, matmult-int, as stated in Section 5.5 ('The power consumption ... using VCD files generated from ... matmult-int benchmark'). Figure 9 shows that the power relationship is workload-dependent: at 900 MHz, C910's power is much higher relative to the in-order cores on the memory-intensive RaiderSTREAM kernels seqcopy and sgcopy than on matmult-int. Because matmult-int is L1-resident and high-ILP, it is the favorable case for an out-of-order core. The Section 6 conclusion that 'beyond the 500 MHz timing target, the C910 core surpasses in-order cores in energy efficiency' is therefore not yet established for general workloads; please either restrict the claim to compute-intensive, L1-resident workloads or provide energy-efficiency results for memory-intensive and low-ILP benchmarks.
  2. [Section 2.3, Section 4.2] The main memory is modeled as an ideal component with no internal latency, and the power traces cover a 30,000-cycle window from the steady-state benchmark body. This removes the memory latency that out-of-order execution is specifically designed to hide and excludes cold-cache behavior. The reported performance and energy results therefore cannot be directly extrapolated to realistic memory hierarchies or to workloads with capacity and conflict misses. Please discuss how the ideal-memory assumption and the finite power window affect the generality of the Section 6 conclusion, or add a sensitivity study with a latency model.
  3. [Section 5.2, Figure 4, Section 5.4] The energy-efficiency crossover is partly driven by circuit-level timing slack rather than by microarchitecture alone: at 900 MHz, C910 is far from its maximum frequency and consequently uses fewer LVT cells and has lower leakage, while CVA6 and CVA6S+ are near their timing limit. This is a legitimate design-point comparison, but it conflates the OoO microarchitecture with the ability to downclock a deeper pipeline. To support the 'not inherently less energy-efficient' claim, please compare at matched operating points (e.g., equal voltage/frequency, equal slack, or each core at its maximum frequency) or explicitly scope the conclusion to these specific implementations compared at equal target frequency.
minor comments (5)
  1. [Section 5.5] The metric 'GOPS' is used in GOPS/mm² and GOPS/W but never defined; please specify how GOPS is computed from the benchmark results (e.g., IPC × frequency × instruction count, or Coremark/MHz).
  2. [Abstract, Section 1] The abstract and introduction report a '119.5% improvement in IPC' for C910 over CVA6, but the average IPC values in Section 5.1 (1.61 vs. 0.70) imply an improvement of roughly 130%; please reconcile these numbers.
  3. [Figure 6, Figure 7] The 'Rest' category in the area and power breakdowns is not explained; a one-sentence definition would help readers interpret what components are included.
  4. [Section 4.2] The text says RaiderSTREAM is used with cold caches, while power analysis is performed after warm-cache iterations 'where present'; please clarify which configuration is used for the RaiderSTREAM power measurements.
  5. [Section 6] There is a missing space in 'analysis ofRISC-V open-source cores' in the first sentence; please fix this typo.

Circularity Check

0 steps flagged · score 0.0 of 10

No circularity found: this is an empirical measurement study whose conclusions rest on post-layout simulation, synthesis, and benchmark data, not on fitted parameters or self-cited uniqueness theorems.

full rationale

The paper makes no claim of deriving a predicted quantity from a fitted input. All central results—IPC, CoreMark/MHz, area, power, energy efficiency—are obtained from standard synthesis, place-and-route, post-layout simulation, and power-estimation flows applied uniformly to three RISC-V cores. The energy-efficiency crossover in Figure 8 is a measured quantity computed from VCD waveforms of a selected benchmark (matmult-int), not the output of a model whose constants were fit to that same crossover. The self-citations present in the paper (Cheshire [12], HPDcache [9], CVA6 [20]) describe components the authors built or maintain; citing these as the integration platform and cache implementation is not circular because the benchmark results and power numbers are external measurements made on those components, not consequences of the citations themselves. The authors' modifications to C910 (standardizing debug, interrupt, and memory interfaces) and to CVA6S+ (register renaming, branch prediction, forwarding, FPU integration) are concrete engineering changes, and the reported 34.4% IPC improvement is a measured outcome, not a prediction derived from an assumption that already contains that improvement. The skeptical concern that the energy-efficiency claim rests on a single compute-intensive benchmark (matmult-int) with an ideal memory model is a threat to external validity and generalization, not circularity: it does not mean any result is equivalent to its inputs by construction. The paper itself reports workload-dependent power behavior in Figure 9, showing larger C910 power gaps on memory-intensive kernels. That is a limitation of the evidence, but it is not a circularity. No step in the paper reduces, by definition, by fitted parameter, or by self-citation, to its own input. Therefore the appropriate circularity score is 0.

Assumptions & free parameters 0 free parameters · 4 assumptions · 0 invented entities

The central efficiency comparison rests on modeling assumptions about the memory system and the representativeness of the measured workloads. The paper states these assumptions clearly but does not validate them against alternative models or a broader benchmark set.

assumptions (4)
  • domain assumption Main memory is modeled as ideal with no internal latency (Section 2.3).
    This abstraction removes memory latency effects and could disproportionately benefit the OoO core with deeper buffers, affecting the energy efficiency comparison.
  • domain assumption Power and energy are characterized from 30,000-cycle VCD windows, assumed representative of steady-state benchmark behavior (Section 4.2).
    Short windows may not capture all workload phases; the same window length is used for all cores, so relative comparisons are likely fair, but absolute values are approximate.
  • domain assumption matmult-int is representative for the area and energy efficiency sweep (Section 5.5).
    The headline efficiency curves are generated solely from matmult-int; conclusions about C910's energy competitiveness rest on this single workload.
  • domain assumption Equivalent L1 cache configurations (64KB, 2-way) for all cores ensure fair comparison (Section 3.3).
    CVA6 uses VIPT with an added anti-aliasing scheme while C910 uses PIPT; the paper assumes the added scheme does not bias power or performance.

how reviews work

0 comments
Cite this review

Pith. "Pith review of Ramping Up Open-Source RISC-V Cores: Assessing the Energy Efficiency of Superscalar, Out-of-Order Execution." pith.science (2026). https://pith.science/paper/KUFWEE2P

@misc{pith2026250524363,
  author       = {Pith},
  title        = {Pith review of: Ramping Up Open-Source RISC-V Cores: Assessing the Energy Efficiency of Superscalar, Out-of-Order Execution},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/KUFWEE2P}},
  note         = {Machine review of arXiv:2505.24363}
}
read the original abstract

Open-source RISC-V cores are increasingly demanded in domains like automotive and space, where achieving high instructions per cycle (IPC) through superscalar and out-of-order (OoO) execution is crucial. However, high-performance open-source RISC-V cores face adoption challenges: some (e.g. BOOM, Xiangshan) are developed in Chisel with limited support from industrial electronic design automation (EDA) tools. Others, like the XuanTie C910 core, use proprietary interfaces and protocols, including non-standard AXI protocol extensions, interrupts, and debug support. In this work, we present a modified version of the OoO C910 core to achieve full RISC-V standard compliance in its debug, interrupt, and memory interfaces. We also introduce CVA6S+, an enhanced version of the dual-issue, industry-supported open-source CVA6 core. CVA6S+ achieves 34.4% performance improvement over CVA6 core. We conduct a detailed performance, area, power, and energy analysis on the superscalar out-of-order C910, superscalar in-order CVA6S+ and vanilla, single-issue in-order CVA6, all implemented in a 22nm technology and integrated into Cheshire, an open-source modular SoC. We examine the performance and efficiency of different microarchitectures using the same ISA, SoC, and implementation with identical technology, tools, and methodologies. The area and performance rankings of CVA6, CVA6S+, and C910 follow expected trends: compared to the scalar CVA6, CVA6S+ shows an area increase of 6% and an IPC improvement of 34.4%, while C910 exhibits a 75% increase in area and a 119.5% improvement in IPC. However, efficiency analysis reveals that CVA6S+ leads in area efficiency (GOPS/mm2), while the C910 is highly competitive in energy efficiency (GOPS/W). This challenges the common belief that high performance in superscalar and out-of-order cores inherently comes at a significant cost in area and energy efficiency.

Figures

Figures reproduced from arXiv: 2505.24363 by the authors.

Figure 1
Figure 1. Architecture comparison of CVA6, CVA6S, and C910 cores [PITH_FULL_IMAGE:figures/full_fig_p003_1.png] view at source ↗
Figure 2
Figure 2. Memory hierarchy of the Cheshire SoC Branch Target Buffer (BTB) for target resolution, comprising a 16- entry fully associative L0 BTB for zero-bubble prediction on hits and a 4K-entry set-associative L1 BTB for broader target cover￾age. The branch history table (BHT) utilizes a two-level adaptive mechanism that combines global and local history patterns for a higher prediction hit rate. It is also equipped with a d… view at source ↗
Figure 3
Figure 3. Performance comparison on Embench-IoT and RaiderSTREAM [PITH_FULL_IMAGE:figures/full_fig_p006_3.png] view at source ↗
Figures from the paper (5 more)
Figure 4
Figure 4. Figure 4: Maximum frequency at different supply voltages [PITH_FULL_IMAGE:figures/full_fig_p006_4.png]
Figure 6
Figure 6. Figure 6: Area breakdown [kGE] near max target frequencies: 900 MHz (CVA6, CVA6S+), 1300 MHz (C910) [PITH_FULL_IMAGE:figures/full_fig_p007_6.png]
Figure 7
Figure 7. Figure 7: Power breakdown (leak/dyn) [mW] near max target frequencies: 900 MHz (CVA6, CVA6S+), 1300 MHz (C910) [PITH_FULL_IMAGE:figures/full_fig_p007_7.png]
Figure 8
Figure 8. Figure 8: Area, energy and area-energy efficiency of the three cores under varying target frequencies [PITH_FULL_IMAGE:figures/full_fig_p007_8.png]
Figure 9
Figure 9. Figure 9: Power comparison on selected benchmarks at the [PITH_FULL_IMAGE:figures/full_fig_p007_9.png]

Discussion (0). Continue with ORCID to comment.

Reference graph

Works this paper leans on

22 extracted references · 20 canonical work pages

  1. [1]

    Côme Allart, Jean-Roch Coulon, André Sintzoff, Olivier Potin, and Jean-Baptiste Rigaud. 2024. Using a Performance Model to Implement a Superscalar CVA6. In Proceedings of the 21st ACM International Conference on Computing Frontiers: Workshops and Special Sessions. 43–46

    work page 2024

  2. [2]

    Omid Azizi, Aqeel Mahesri, Benjamin C Lee, Sanjay J Patel, and Mark Horowitz

    work page

  3. [3]

    Michael Beebe, Brody Williams, Stephen Devaney, John Leidel, Yong Chen, and Steve Poole. 2022. RaiderSTREAM: Adapting the STREAM Benchmark to Modern HPC Systems. In 2022 IEEE High Performance Extreme Computing Conference (HPEC). IEEE, 1–7

    work page 2022

  4. [4]

    David Brooks, Robert P Dick, Russ Joseph, and Li Shang. 2007. Power, thermal, and reliability modeling in nanometer-scale microprocessors. Ieee Micro 27, 3 (2007), 49–62

    work page 2007

  5. [5]

    Nick Brown, Maurice Jamieson, Joseph Lee, and Paul Wang. 2023. Is RISC-V ready for HPC prime-time: Evaluating the 64-core Sophon SG2042 RISC-V CPU. In Proceedings of the SC’23 Workshops of The International Conference on High Performance Computing, Network, Storage, and Analysis . 1566–1574

    2023

  6. [6]

    Andrew Burgess, Ashley Whetter, George Field, Graham Markall, Hendrik Oosen- brug, James Pallister, Jeremy Bennett, Neville Grech, Pierre Langlois, and Si- mon Cook. 2023. Embench IoT Benchmark Suite. https://github.com/embench/ embench-iot. Accessed: 2024-09-19

    work page 2023

  7. [7]

    Chen Chen, Xiaoyan Xiang, Chang Liu, Yunhai Shang, Ren Guo, Dongqi Liu, Yimin Lu, Ziyi Hao, Jiahui Luo, Zhijian Chen, et al. 2020. Xuantie-910: A commer- cial multi-core 12-stage pipeline out-of-order 64-bit high performance RISC-V processor with vector extension: Industrial product. In 2020 ACM/IEEE 47th Annual International Symposium on Computer Archite...

    work page 2020

  8. [8]

    Amant, Karthikeyan Sankaralingam, and Doug Burger

    Hadi Esmaeilzadeh, Emily Blem, Renee St. Amant, Karthikeyan Sankaralingam, and Doug Burger. 2011. Dark silicon and the end of multicore scaling. In Pro- ceedings of the 38th annual international symposium on Computer architecture . 365–376

    work page 2011

Show all 22 references
  1. [9]

    César Fuguet. 2023. HPDcache: Open-source high-performance L1 data cache for RISC-V cores. In Proceedings of the 20th ACM International Conference on Computing Frontiers. 377–378

    2023

  2. [10]

    Shay Gal-On and Markus Levy. 2012. Exploring coremark a benchmark maximiz- ing simplicity and efficacy. The Embedded Microprocessor Benchmark Consortium (2012)

    2012

  3. [11]

    Hennessy and David A

    John L. Hennessy and David A. Patterson. 2019. A new golden age for computer architecture. Commun. ACM 62, 2 (Jan. 2019), 48–60. doi:10.1145/3282307

    2019 doi

  4. [12]

    Alessandro Ottaviano, Thomas Benz, Paul Scheffler, and Luca Benini. 2023. Cheshire: A lightweight, linux-capable risc-v host platform for domain-specific accelerator plug-in. IEEE Transactions on Circuits and Systems II: Express Briefs 70, 10 (2023), 3777–3781

    2023

  5. [13]

    Ronny Ronen, Avi Mendelson, Konrad Lai, Shih-Lien Lu, Fred Pollack, and John Paul Shen. 2001. Coming challenges in microarchitecture and architec- ture. Proc. IEEE 89, 3 (2001), 325–340

    2001

  6. [14]

    Semidynamics. 2025. Atrevido Processor Product Page. https://semidynamics. com/en/products/atrevido [Online; accessed 2025-01-27]

    2025

  7. [15]

    Muhammad Shafique, Siddharth Garg, Jörg Henkel, and Diana Marculescu. 2014. The EDA challenges in the dark silicon era: Temperature, reliability, and variabil- ity perspectives. In Proceedings of the 51st Annual Design Automation Conference . 1–6

    2014

  8. [16]

    SiFive, Inc. 2024. SiFive Performance P550 Core Data Sheet. https://www.sifive. com/document-file/p550-core-data-sheet [Online; accessed 2025-01-27]

    2024

  9. [17]

    Ventana Micro. 2025. Ventana Introduces Veyron V2. https://www.ventanamicro. com/ventana-introduces-veyron-v2/ [Online; accessed 2025-01-27]

    2025

  10. [18]

    Yinan Xu, Zihao Yu, Dan Tang, Guokai Chen, Lu Chen, Lingrui Gou, Yue Jin, Qianruo Li, Xin Li, Zuojun Li, et al. 2022. Towards developing high performance RISC-V processors using agile methodology. In 2022 55th IEEE/ACM International Symposium on Microarchitecture (MICRO) . IEE...

    2022

  11. [19]

    Tse-Yu Yeh and Yale N Patt. 1991. Two-level adaptive training branch prediction. In Proceedings of the 24th annual international symposium on Microarchitecture . 51–61

    1991

  12. [20]

    Florian Zaruba and Luca Benini. 2019. The Cost of Application-Class Processing: Energy and Performance Analysis of a Linux-Ready 1.7-GHz 64-Bit RISC-V Core in 22-nm FDSOI Technology. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 27, 11 (2019), 2629–2640

    2019

  13. [21]

    Jerry Zhao, Ben Korpan, Abraham Gonzalez, and Krste Asanovic. 2020. Sonic- BOOM: The 3rd Generation Berkeley Out-of-Order Machine. (May 2020)

    2020

  14. [2010]

    ACM SIGARCH Computer Architecture News 38, 3 (2010), 26–36

    Energy-performance tradeoffs in processor architecture and circuit design: a marginal cost analysis. ACM SIGARCH Computer Architecture News 38, 3 (2010), 26–36

    2010

Pith tools

Reviewed August 7, 2026 · model on record in the stance chip above.