pith. sign in

arxiv: 2607.01473 · v1 · pith:LJTVQ72Vnew · submitted 2026-07-01 · 🪐 quant-ph

Surface code logical operations on a superconducting quantum processor

Weiping Lin , Shaojun Guo , Yuwei Ma , Zhengzhong Yi , Kai Zhang , Jiahao Bei , Jianbin Cai , Sirui Cao
show 139 more authors
Danning Chen Guoben Chen Jianguo Chen Kefu Chen Xiawei Chen Zhe Chen Zhiyuan Chen Zihua Chen Wenhao Chu Hui Deng Xun Ding Zhuzhengqi Ding Yajie Du Bo Fan Daojin Fan Yuanhao Fu Dongxin Gao Ming Gong Jiacheng Gui Cheng Guo Lianchen Han Tan He Linyin Hong Yisen Hu He-Liang Huang Yong-Heng Huo Chenyan Jiang Lei Jiang Tao Jiang Wei Jiang Zuokai Jiang Dayu Li Dongdong Li Jiaqi Li Jinjin Li Junyun Li Shaowei Li Wei Li Xu Li Yuan Li Yuhuai Li Futian Liang Nanxing Liao Jin Lin Maliang Liu Yancheng Liu Haoxin Lou Kailiang Nan Meijuan Nie Le Niu Wenyi Peng Haoran Qian Hao Rong Tao Rong Yanyan Shao Huiyan Shen Qiong Shen Ganlin Song Hong Su Feifan Su Chenyin Sun De Sun Liangchao Sun Tianzuo Sun Yingxiu Sun Yimeng Tan Jun Tan Shibiao Tang Yueyang Tang Wenbing Tu Jiafei Wang Biao Wang Chang Wang Chen Wang Chu Wang Jian Wang Rui Wang Shengtao Wang Xinzhe Wang Zhi Wang Zuolin Wei Gang Wu Yulin Wu Hongjun Xia Shouzhong Xia Shiyong Xie Zhilin Xie Liang Xiong Jianping Xu Yan Xu Yu Xu Chun Xue Kai Yan Xin Yan Weifeng Yang Xinpeng Yang Yang Yang Yicheng Yang Yangsen Ye Zhenping Ye Jianghan Yin Chong Ying Jiale Yu Qinjing Yu Chen Zha Shaoyu Zhan Cha Zhang Fang Zhang Haibin Zhang He Zhang Huanmei Zhang Kaili Zhang Qipeng Zhang Shijia Zhang Wen Zhang Xin Zhang Yiming Zhang Yongzhuo Zhang Ziying Zhang Guming Zhao Xintao Zhao Youwei Zhao Zhong Zhao Luyuan Zheng Fei Zhou Liang Zhou Naibin Zhou Chengjun Zhu Qingling Zhu Yongsheng Zhu Guihong Zou Haonan Zou Qiang Zhang Chao-Yang Lu Jianxin Chen Cheng-Zhi Peng Fusheng Chen XiaoBo Zhu Jian-Wei Pan
This is my paper

Pith reviewed 2026-07-03 19:55 UTC · model grok-4.3

classification 🪐 quant-ph
keywords surface codelattice surgerylogical gatessuperconducting qubitsfault-tolerant quantum computationClifford gatesdistance-three codeneural-network decoding
0
0 comments X

The pith

A superconducting processor executes logical CNOT and other Clifford gates on distance-three surface-code patches using lattice-surgery primitives.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper demonstrates experimental realization of active logical operations on encoded qubits protected by the surface code in a 107-qubit superconducting device. It first builds a set of reusable primitives including patch merge and split, expansion and shrinkage, and deformations through domain walls and twist defects. These are then composed into logical state routing, a two-qubit controlled-NOT gate, and single-qubit Hadamard and phase gates, all performed with repeated syndrome extraction and neural-network decoding on distance-three patches and without discarding any runs.

Core claim

We experimentally realize key elements of patch-based surface-code logical processing on a 107-qubit superconducting quantum processor. We first implement a reusable primitive layer comprising merge and split, patch expansion and shrinkage, and deformations mediated by domain walls and twist defects. We then compose these primitives to realize logical state routing, the logical controlled-NOT gate, and the single-qubit Hadamard and phase gates, which together form a Clifford-generating set. All operations are implemented on distance-three rotated surface-code patches with multi-round syndrome extraction and neural-network decoding, without post-selection.

What carries the argument

Lattice-surgery primitives (merge, split, expansion, shrinkage, domain walls, twist defects) acting on distance-three rotated surface-code patches, combined with multi-round syndrome extraction and neural-network decoding.

If this is right

  • Logical routing of quantum states between separate patches can be achieved by composing merge, split, and deformation operations.
  • A logical controlled-NOT gate is realized between two distance-three patches through lattice surgery without post-selection.
  • Single-qubit Hadamard and phase gates together with the logical CNOT generate the full Clifford group on the encoded qubits.
  • All operations maintain the distance-three error-correction threshold through repeated syndrome measurements decoded by a neural network.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • Extending the same primitives to distance-five or higher patches would test whether logical error rates continue to drop with code distance during active gates.
  • The demonstrated Clifford set could serve as a foundation for injecting non-Clifford states to reach universal fault-tolerant computation.
  • Real-time neural-network decoding on hardware of this scale indicates a practical path for handling the classical processing load of larger surface-code processors.

Load-bearing premise

The neural-network decoder correctly identifies and corrects errors across the multi-round syndrome extraction cycles on distance-3 patches without introducing undetected logical errors that would invalidate the gate fidelities.

What would settle it

Observing that the logical error rate extracted from the final patch states fails to decrease (or increases) when the number of syndrome-extraction rounds is increased would falsify the claim that the operations preserve error-correction protection.

Figures

Figures reproduced from arXiv: 2607.01473 by Biao Wang, Bo Fan, Chang Wang, Chao-Yang Lu, Cha Zhang, Cheng Guo, Chengjun Zhu, Cheng-Zhi Peng, Chen Wang, Chenyan Jiang, Chenyin Sun, Chen Zha, Chong Ying, Chun Xue, Chu Wang, Danning Chen, Daojin Fan, Dayu Li, De Sun, Dongdong Li, Dongxin Gao, Fang Zhang, Feifan Su, Fei Zhou, Fusheng Chen, Futian Liang, Gang Wu, Ganlin Song, Guihong Zou, Guming Zhao, Guoben Chen, Haibin Zhang, Haonan Zou, Haoran Qian, Hao Rong, Haoxin Lou, He-Liang Huang, He Zhang, Hongjun Xia, Hong Su, Huanmei Zhang, Hui Deng, Huiyan Shen, Jiacheng Gui, Jiafei Wang, Jiahao Bei, Jiale Yu, Jianbin Cai, Jianghan Yin, Jianguo Chen, Jianping Xu, Jian Wang, Jian-Wei Pan, Jianxin Chen, Jiaqi Li, Jinjin Li, Jin Lin, Jun Tan, Junyun Li, Kailiang Nan, Kaili Zhang, Kai Yan, Kai Zhang, Kefu Chen, Lei Jiang, Le Niu, Lianchen Han, Liangchao Sun, Liang Xiong, Liang Zhou, Linyin Hong, Luyuan Zheng, Maliang Liu, Meijuan Nie, Ming Gong, Naibin Zhou, Nanxing Liao, Qiang Zhang, Qingling Zhu, Qinjing Yu, Qiong Shen, Qipeng Zhang, Rui Wang, Shaojun Guo, Shaowei Li, Shaoyu Zhan, Shengtao Wang, Shibiao Tang, Shijia Zhang, Shiyong Xie, Shouzhong Xia, Sirui Cao, Tan He, Tao Jiang, Tao Rong, Tianzuo Sun, Weifeng Yang, Wei Jiang, Wei Li, Weiping Lin, Wenbing Tu, Wenhao Chu, Wenyi Peng, Wen Zhang, Xiaobo Zhu, Xiawei Chen, Xinpeng Yang, Xintao Zhao, Xin Yan, Xin Zhang, Xinzhe Wang, Xu Li, Xun Ding, Yajie Du, Yancheng Liu, Yangsen Ye, Yang Yang, Yan Xu, Yanyan Shao, Yicheng Yang, Yimeng Tan, Yiming Zhang, Yingxiu Sun, Yisen Hu, Yong-Heng Huo, Yongsheng Zhu, Yongzhuo Zhang, Youwei Zhao, Yuanhao Fu, Yuan Li, Yueyang Tang, Yuhuai Li, Yulin Wu, Yuwei Ma, Yu Xu, Zhe Chen, Zhengzhong Yi, Zhenping Ye, Zhilin Xie, Zhi Wang, Zhiyuan Chen, Zhong Zhao, Zhuzhengqi Ding, Zihua Chen, Ziying Zhang, Zuokai Jiang, Zuolin Wei.

Figure 1
Figure 1. Figure 1: FIG. 1 [PITH_FULL_IMAGE:figures/full_fig_p002_1.png] view at source ↗
Figure 2
Figure 2. Figure 2: a shows the state-teleportation protocol implemented by lattice surgery. The input patch was prepared in the target logical state, while an auxiliary patch was initialized in |+⟩. A merge–split sequence measured the joint logical ZZ parity between the two patches. The input patch was then measured in the X basis, and the logical state was recovered on the aux￾iliary patch through Pauli-frame updates condit… view at source ↗
Figure 3
Figure 3. Figure 3: FIG. 3 [PITH_FULL_IMAGE:figures/full_fig_p005_3.png] view at source ↗
Figure 5
Figure 5. Figure 5: FIG. 5 [PITH_FULL_IMAGE:figures/full_fig_p006_5.png] view at source ↗
read the original abstract

Fault-tolerant quantum computation requires logical operations that manipulate encoded information while preserving quantum error-correction protection. In planar surface-code architectures, code deformation and lattice surgery provide a local, measurement-based route to such operations. Here we experimentally realize key elements of patch-based surface-code logical processing on a 107-qubit superconducting quantum processor. We first implement a reusable primitive layer comprising merge and split, patch expansion and shrinkage, and deformations mediated by domain walls and twist defects. We then compose these primitives to realize logical state routing, the logical controlled-NOT gate, and the single-qubit Hadamard and phase gates, which together form a Clifford-generating set. All operations are implemented on distance-three rotated surface-code patches with multi-round syndrome extraction and neural-network decoding, without post-selection. Our results advance superconducting surface-code experiments from protected logical memory to active, patch-based fault-tolerant logical operations.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

2 major / 1 minor

Summary. The paper claims an experimental realization of patch-based surface-code logical processing on a 107-qubit superconducting processor. It implements a primitive layer of merge/split, patch expansion/shrinkage, and domain-wall/twist-defect deformations, then composes these into logical routing, CNOT, Hadamard, and phase gates (a Clifford-generating set) on distance-3 rotated surface-code patches. All operations use multi-round syndrome extraction and neural-network decoding without post-selection.

Significance. If the results hold, the work advances superconducting surface-code experiments from logical memory to active, patch-based logical operations at a scale of 107 qubits. The reusable primitive layer and explicit composition to a Clifford set provide a concrete experimental pathway for lattice-surgery-based fault tolerance. The absence of post-selection on d=3 patches is a notable experimental strength if supported by the data.

major comments (2)
  1. [Abstract] Abstract and decoder description: The central claim that operations are realized 'without post-selection' rests on the neural-network decoder producing no undetected logical errors on multi-round syndrome data from d=3 patches. No quantitative logical-error rates, error budgets, or raw fidelity numbers are stated, and no cross-validation against MWPM or lookup-table decoding on the experimental syndrome streams is reported. This directly affects whether the measured gate fidelities can be trusted.
  2. [Results] Results on gate composition: The logical CNOT, H, and S gates are obtained by composing the primitives, but without reported logical error rates per gate or comparison to the underlying physical error rates, it is not possible to confirm that the distance-3 protection is preserved through the multi-round cycles.
minor comments (1)
  1. Figure captions should explicitly state the number of syndrome extraction rounds and the training data used for the neural-network decoder to allow direct assessment of the d=3 performance.

Simulated Author's Rebuttal

2 responses · 0 unresolved

We thank the referee for the constructive comments highlighting the need for quantitative metrics to support the no-post-selection claims and distance-3 protection. We agree these details strengthen the paper and have revised the manuscript to incorporate logical error rates, error budgets, and decoder cross-validation.

read point-by-point responses

  1. Referee: [Abstract] Abstract and decoder description: The central claim that operations are realized 'without post-selection' rests on the neural-network decoder producing no undetected logical errors on multi-round syndrome data from d=3 patches. No quantitative logical-error rates, error budgets, or raw fidelity numbers are stated, and no cross-validation against MWPM or lookup-table decoding on the experimental syndrome streams is reported. This directly affects whether the measured gate fidelities can be trusted.

    Authors: We agree that explicit quantitative support is required. The revised manuscript adds a dedicated decoder performance subsection reporting logical error rates per operation (extracted from the full neural-network-decoded dataset with no post-selection), including error budgets broken down by physical error sources. We also include a direct comparison of the neural-network decoder against MWPM on the experimental syndrome streams from the d=3 patches, confirming consistent logical error suppression. These additions allow independent assessment of the gate fidelities. revision: yes

  2. Referee: [Results] Results on gate composition: The logical CNOT, H, and S gates are obtained by composing the primitives, but without reported logical error rates per gate or comparison to the underlying physical error rates, it is not possible to confirm that the distance-3 protection is preserved through the multi-round cycles.

    Authors: We concur that per-gate logical error rates and physical comparisons are needed to verify preservation of distance-3 protection. The revised Results section now reports logical error rates for each composed gate (CNOT, H, S) over the multi-round cycles and directly compares them to the measured physical error rates on the device. The data show logical rates suppressed relative to physical rates, consistent with d=3 error correction being maintained through the primitive compositions. revision: yes

Circularity Check

0 steps flagged

No circularity: experimental outcomes with no derivation chain or fitted predictions

full rationale

The manuscript presents direct experimental results from a 107-qubit processor implementing merge/split, deformations, routing, CNOT, Hadamard and phase gates on d=3 surface-code patches using multi-round syndrome extraction and neural-network decoding. No equations, ansatzes, or first-principles derivations are claimed; no parameters are fitted to data and then relabeled as predictions; no self-citation chain is invoked to justify uniqueness or load-bearing premises. The neural-network decoder is an applied post-processing step whose correctness is an empirical assumption (not a definitional loop), and the paper does not reduce any reported fidelity or operation to its own inputs by construction. This is a standard experimental report whose claims stand or fall on hardware data rather than internal redefinition.

Axiom & Free-Parameter Ledger

0 free parameters · 0 axioms · 0 invented entities

Abstract-only review provides no explicit free parameters, axioms, or invented entities beyond standard surface-code assumptions; neural-network decoder parameters are implicit but unquantified.

pith-pipeline@v0.9.1-grok · 6237 in / 1125 out tokens · 21376 ms · 2026-07-03T19:55:39.550848+00:00 · methodology

discussion (0)

Sign in with ORCID, Apple, or X to comment. Anyone can read and Pith papers without signing in.

Reference graph

Works this paper leans on

28 extracted references · 5 canonical work pages · 2 internal anchors

  1. [1]

    He, T. et al. Experimental quantum error correction below the surface code threshold via all-microwave leakage suppression. Physical Review Letters135, 260601 (2025). 32

    2025

  2. [2]

    Gao, D. et al. Establishing a new benchmark in quantum computational advantage with 105-qubit zuchongzhi 3.0 processor. Physical Review Letters134, 090601 (2025)

    2025

  3. [3]

    Jiang, T. et al. One- and two-dimensional cluster states for topological phase simulation and measurement-based quantum computation. Nature Physics22, 430–438 (2026)

    2026

  4. [4]

    P., Tuckett, D

    Bonilla Ataides, J. P., Tuckett, D. K., Bartlett, S. D., Flammia, S. T. & Brown, B. J. The xzzx surface code. Nature communications12, 2172 (2021)

    2021

  5. [5]

    Arute, F. et al. Quantum supremacy using a programmable superconducting processor. Nature574, 505–510 (2019)

    2019

  6. [6]

    Grbic, D., Beni, L. A. & Shutty, N. Accelerating the tesseract decoder for quantum error correction (2026). arXiv.2602.02985

    work page arXiv 2026

  7. [7]

    G., Devitt, S

    Horsman, C., Fowler, A. G., Devitt, S. & Van Meter, R. Surface code quantum computing by lattice surgery. New Journal of Physics14, 123011 (2012)

    2012

  8. [8]

    A game of surface codes: Large-scale quantum computing with lattice surgery

    Litinski, D. A game of surface codes: Large-scale quantum computing with lattice surgery. Quantum3, 128 (2019)

    2019

  9. [9]

    BeliefMatching: An implementation of the belief-matching decoder (v0.1.0).https://github.com/oscarhiggott/ BeliefMatching(2023)

    Higgott, O. BeliefMatching: An implementation of the belief-matching decoder (v0.1.0).https://github.com/oscarhiggott/ BeliefMatching(2023)

    2023

  10. [10]

    PyMatching: A python package for quantum error-correction decoding with minimum-weight perfect matching.https: //github.com/oscarhiggott/PyMatching(2025)

    Higgott, O. PyMatching: A python package for quantum error-correction decoding with minimum-weight perfect matching.https: //github.com/oscarhiggott/PyMatching(2025)

    2025

  11. [11]

    Zhang, K. et al. Learning to decode in parallel: Self-coordinating neural network for real-time quantum error correction (2026). arXiv.2601.09921

    work page arXiv 2026

  12. [12]

    Bausch, J. et al. Learning high-accuracy error decoding for quantum processors. Nature635, 834–840 (2024)

    2024

  13. [13]

    Chuang, I. L. & Nielsen, M. A. Prescription for experimental determination of the dynamics of a quantum black box. Journal of Modern Optics44, 2455–2467 (1997)

    1997

  14. [14]

    Lacroix, N., Bourassa, A., Heras, F. J. H. et al. Scaling and logic in the colour code on a superconducting quantum processor. Nature645, 614–619 (2025)

    2025

  15. [15]

    Rosenfeld, E., Gidney, C., Roberts, G. et al. Magic state cultivation on a superconducting quantum processor (2025). arXiv.2512.13908

    work page arXiv 2025

  16. [16]

    Erhard, A. et al. Entangling logical qubits with lattice surgery. Nature589, 220–224 (2021)

    2021

  17. [17]

    Ryan-Anderson, C. et al. High-fidelity teleportation of a logical qubit using transversal gates and lattice surgery. Science385, 1327–1331 (2024)

    2024

  18. [18]

    Bluvstein, D. et al. A fault-tolerant neutral-atom architecture for universal quantum computation. Nature649, 39–46 (2026)

    2026

  19. [19]

    Besedin, I. et al. Lattice surgery realized on two distance-three repetition codes with superconducting qubits. Nature Physics22, 189–194 (2026)

    2026

  20. [20]

    A superconducting surface-code processor with lattice-surgery logical operations

    Wang, Y .et al. A superconducting surface-code processor with lattice-surgery logical operations (2026). arXiv.2606.06598

    work page internal anchor Pith review Pith/arXiv arXiv 2026

  21. [21]

    Inplace access to the surface code Y basis

    Gidney, C. Inplace access to the surface code Y basis. Quantum8, 1310 (2024)

    2024

  22. [22]

    Quantum error correction below the surface code threshold

    Google Quantum AI & Collaborators. Quantum error correction below the surface code threshold. Nature638, 920–926 (2025)

    2025

  23. [23]

    P., McLauchlan, C., Campbell, E

    Geh ´er, G. P., McLauchlan, C., Campbell, E. T., Moylett, A. E. & Crawford, O. Error-corrected Hadamard gate simulated at the circuit level. Quantum8, 1394 (2024)

    2024

  24. [24]

    J., Laubscher, K., Kesselring, M

    Brown, B. J., Laubscher, K., Kesselring, M. S. & Wootton, J. R. Poking holes and cutting corners to achieve Clifford gates with the surface code. Physical Review X7, 021029 (2017)

    2017

  25. [25]

    Logical blocks for fault-tolerant topological quantum computation

    Bomb ´ın, H.et al. Logical blocks for fault-tolerant topological quantum computation. PRX Quantum4, 020303 (2023)

    2023

  26. [26]

    Stim: a fast stabilizer circuit simulator

    Gidney, C. Stim: a fast stabilizer circuit simulator. Quantum5, 497 (2021)

    2021

  27. [27]

    Krentel, M. W. The complexity of optimization problems. Journal of Computer and System Sciences36, 490–509 (1988)

    1988

  28. [28]

    A $\boldsymbol{2d \times d \times d}$ Spacetime Volume Implementation of a Logical S Gate in the Surface Code

    Hirai, Y ., Ikari, S., Ueno, Y . & Suzuki, Y . A 2d×d×dspacetime volume implementation of a logical S gate in the surface code (2026). arXiv.2604.13632

    work page internal anchor Pith review Pith/arXiv arXiv 2026