High-rate qLDPC processors

Aditya Bhardwaj; Dolev Bluvstein; Hsin-Yuan Huang; John Preskill; Madelyn Cain; Muzhou Ma; Nadine Meister; Qian Xu; Robbie King

REVIEW 3 major objections 4 minor 4 cited by

High-rate qLDPC processors

T0 review · 3 major / 4 minor · reviewed 2026-08-03 · deepseek-v4-flash

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Pith's one-line read This paper claims that mitten codes, a family of non-abelian lifted product codes, reach 20% encoding rate and distances 18–24 with only hundreds of qubits, and that with a fast decoder they can sustain about 10^10 logical operations under

desk verdict Mitten codes are a genuinely new construction with solid structural proofs; the processor-level error numbers are honest simulations under a no-idling-noise model that materially limits their meaning for neutral-atom hardware. read the letter →

arxiv 2607.28795 v1 pith:M6IBYFHE submitted 2026-07-30 quant-ph

Aditya Bhardwaj , Muzhou Ma , Nadine Meister , Robbie King , Dolev Bluvstein , John Preskill , Madelyn Cain , Qian Xu

show 1 more author

Hsin-Yuan Huang

This is my paper · ORCID

classification quant-ph MSC 81P7094B05 PACS 03.67.Pp

keywords quantumerrorcorrectionqLDPCcodesliftedproductnon-abeliangroupsfault-tolerantcomputationcodesurgerymagicstateinjectionneutralatomcomputing

verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

This paper introduces mitten codes, a family of quantum low-density parity-check (qLDPC) codes built from non-abelian groups. The non-abelian structure escapes a distance bound that caps abelian designs, so a 540-qubit code can have distance 18 and a 975-qubit code roughly distance 24, each at 20% encoding rate. The authors show how to turn these codes into a full fault-tolerant processor: five reusable surgery gadgets provide Clifford logic, high-rate gadgets measure many logical products at once, and magic states can be injected into all logical qubits in parallel. Using a staged decoder in circuit-level simulations, they report block logical error rates around 10^-11 per round at 0.1% physical error, and a processing capacity consistent with 10^10 logical operations. If correct, this would make practical fault-tolerant quantum computation feasible on near-term neutral-atom and superconducting hardware with a manageable qubit count.

What carries the argument

The central object is the mitten code: a lifted product code LP(A,B) with 1x2 base matrices A=[a0 a1] and B=[b0 b1] over the group algebra F2[G] for a non-abelian group G, where L(a1) and R(b1) are full-rank. This full-rank 'square invertibility' condition is what forces a canonical logical basis with single-orbit group symmetry, letting one rewired seed gadget measure any logical operator. The parity-check matrices have a five-block 'mitten' shape that interleaves left and right regular representations. The telescoping decoder is a staged pipeline that uses belief propagation and Relay-BP on GPU to quickly decode easy shots, then sends a small residual of harder shots to an exact integer-pr

What would settle it

Simulate or run the [300,60,14] and [540,108,18] codes with a noise model that adds idle decoherence, atom loss, and movement error at 0.1% per gate; if observed per-round logical error rates rise above roughly 10^-8 or processing capacity falls below 10^8 quops, the central capacity claim fails. Independently, compute the exact distance of the [975,195,<=24] code; if it turns out to be below about 18, the high-distance claim fails.

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Extended reading notes

Core claim

The central claim is that taking the lifted product of two 1x2 classical matrices over the group algebra of a non-abelian group, with the left and right regular representations full-rank, yields codes with 20% encoding rate, check weight 9, and distances reaching 18 or more with only a few hundred physical qubits. The same full-rank condition produces a canonical logical basis in which every logical X and Z operator is a group-action image of one seed operator, so that the entire logical toolkit reduces to two seed surgery gadgets plus a few bridged gadgets. Under a uniform depolarizing circuit-level noise model, the [300,60,14] code attains about 10^-11 block logical error per round, and th

Load-bearing premise

The headline processor-capacity numbers rest on a circuit-level noise model with depolarizing gate and measurement noise but no idling noise, while the three largest code distances are certified by estimates rather than proofs; if real hardware adds idle decoherence and atom loss during the 5–24 ms syndrome-extraction cycle, or if the estimated distances are off, the claimed 10^-11 per-round and 10^10-quop figures could degrade.

Editorial extensions

If this is right

A single [300,60,14] block would run roughly a billion logical operations between errors at 0.1% physical gate error, enough for many small fault-tolerant algorithms.
The 20% encoding rate means about five physical qubits per logical qubit, roughly an order of magnitude fewer than surface-code stacks of comparable distance.
Parallel magic-state injection into all logical qubits at once removes the usual magic-state bottleneck that dominates spacetime overhead in surface-code architectures.
The decoder's estimated sub-millisecond latency fits inside the 5–24 ms syndrome-extraction cycle of neutral-atom hardware, keeping open the route to real-time decoding.
The 540-qubit distance-18 code reaches a 10^10-quop regime, a scale relevant for algorithmic demonstrations rather than only memory benchmarks.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

The paper's simulations exclude idle-time decoherence and atom-movement errors; adding those to the noise model is the most direct test of whether the claimed error rates survive on real neutral-atom hardware.
The single-orbit symmetry likely extends beyond the specific mitten instances found here, suggesting a broader design space for any lifted product code with a square-invertible base matrix over a non-abelian group.
A natural next step is to simulate a complete end-to-end circuit that includes magic-state distillation and consumption, measuring wall-clock throughput in addition to per-round logical error rate.
If the estimated distances of the larger instances are certified exactly, the same group-searching pipeline may yield distance-30-plus codes in under 1500 qubits with only modest changes to the group or base matrices.

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Signed reviews

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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Desk Editor's Note

read the letter

Bottom line: the mitten code construction is the real thing, and the paper deserves a serious referee. The headline error rates are honest simulation results, but they sit inside a noise model that omits idle and movement errors, which is a material caveat for the neutral-atom hardware the paper targets.

What is actually new: mitten codes are a genuinely new family of non-abelian lifted product codes with 1×2 base matrices. For abelian G a codeword of A caps the distance at the base check weight; taking G non-abelian removes that cap, and the paper backs this with a canonical logical basis in a single group orbit (Theorem 4), classical-distance upper bounds, distance-preserving magic injection, and thickness-3 results. The five-gadget surgery toolkit, the parallel magic injection, and the telescoping decoder are substantial engineering contributions. The paper is also unusually transparent about method: distances of the first five codes are exact, the rest are marked with ≤ and estimated by sQetch; decoder simulations use Clopper-Pearson intervals, and the code and pipeline are open-sourced.

The main soft spot is exactly what the stress test flags. The circuit-level simulations apply depolarizing noise to state preparation, two-qubit gates, and measurement, with no idling noise. For the neutral-atom implementation, syndrome extraction cycles run 5–24 ms, during which data atoms sit idle and ancillas move. With T2 around a second, even 10 ms of idle gives roughly 1% dephasing per cycle, orders of magnitude above the 0.1% gate error used in the simulations. The paper states this limitation clearly in the figure caption, so it is not an internal inconsistency, but it is load-bearing for the “~10^10 logical operations” claim and for the memory error rates as hardware predictions. That claim is also slightly rounded up: the central value from 2 failures in 15 billion is about 7.5e9 quops, not 1e10. And “sub-millisecond latency” is an FPGA extrapolation, not a measurement.

None of this touches the code construction. The structural theorems and exact parameters up to distance 18 are independent of the noise model, and the evidence for them looks solid.

Who should read this: anyone working on high-rate qLDPC codes or fault-tolerant architectures on neutral atoms and multilayer superconducting platforms. It deserves a proper peer review; a good referee should check the appendix proofs and push the authors to separate the code-construction claims from the hardware-readiness claims, ideally by labeling the no-idling assumption in the abstract and reporting the 7.5e9 central value honestly. I would send it out.

Referee Report

3 major / 4 minor

Summary. The paper introduces mitten codes, a family of qLDPC codes constructed as 1×2 lifted products over non-abelian group algebras, and argues that they satisfy four processor desiderata: 20% encoding rate, check weight 9, hardware-friendly layouts, and fast decoding. The central structural contributions are a canonical logical basis obtained from the group action (Theorem 4), distance upper bounds for lifted products (Theorem 8), explicit surgery and extractor gadgets, a distance-preserving parallel magic-state injection scheme (Theorem 7), and a proof that the codes have planar thickness three (Theorem 15). The paper also reports an end-to-end design pipeline built on sQetch, a GPU-based distance estimator, and Monte Carlo decoding results: a [300,60,14] code with block logical error rate ~10^-11 per round at 0.1% PER, and a [540,108,18] code with 2 logical failures in 15 billion surgery experiments, quoted as a ~10^10-quop processing capacity. The simulations use circuit-level depolarizing noise on state preparation, two-qubit gates, and measurements, with no idling noise.

Significance. If the structural and performance claims hold, this is a substantial step toward practical qLDPC processors: the 1/5 rate at block sizes of a few hundred qubits, the group-orbit logical basis, and the modular five-gadget Clifford toolkit are notable and well-motivated. The paper is commendably explicit: it provides concrete code instances, exact distances for the first five codes, open-source pipeline components, and Monte Carlo data with Clopper-Pearson intervals and an exact integer-programming decoding stage. However, the headline quantitative claims—10^-11 per round and ~10^10 quops—are obtained under a no-idling noise model and are therefore not directly transferable to the neutral-atom hardware the paper targets.

major comments (3)

[Section V, Fig. 2 caption, Table I] The processor-capacity claims are load-bearing and are generated with 'no idling noise' (Fig. 2 caption). For the neutral-atom implementation, Table I lists syndrome-extraction cycles of 5–24 ms, during which data qubits idle and ancillas are transported by AODs. Under even a conservative T2 ~ 1 s, idle dephasing alone contributes ~1 − exp(−10 ms/1 s) ≈ 1% error per cycle, an order of magnitude above the 0.1% PER used in the simulations; atom loss and movement errors are also omitted. Consequently, the abstract's 'capable of running ~10^10 logical operations' and the related quantitative claims are not estimates for the hardware discussed. The paper is transparent about this assumption, but the claims in the abstract and conclusion should be restricted to the no-idling model or supplemented with a hardware-realistic idle/transport noise model.
[Table I, Section V, Appendix H.5] Distances of the three largest instances (J630,126,≤20K, J780,156,≤22K, J975,195,≤24K) are estimates from sQetch and BP+OSD, not exact values, and the syndrome-extraction schedules are described as 'likely preserve' or 'verified with sQetch' rather than proven to preserve circuit-level distance. The abstract's 'distance 18 and beyond' is exactly supported only up to the [540,108,18] code; the performance of the [975,195,≤24] code and of all memory/surgery experiments depends on estimated distances. Because sQetch is a heuristic estimator, the possibility of a lower actual distance or a schedule-induced distance collapse is not excluded. Please either provide exact certificates/proofs for the reported distances and schedule fault-tolerance, or clearly label all performance claims that depend on these estimates as conditional.
[Section V, Fig. 2(b)] The claim of a '~10^10-quop processor' rests on two logical failures in 15 billion surgery experiments. The Clopper-Pearson interval reported by the authors (1.33^{+1.76}_{−0.86}×10^-10) already shows a factor-of-several uncertainty, and the statement that the code is 'capable' of 10^10 quops is a consistency extrapolation rather than a direct demonstration. The phrase 'without extrapolation' is used only for the memory rate, but the processing-capacity summary in the abstract and conclusion should distinguish between the measured two-failure result and the inferred capacity.

minor comments (4)

[Abstract and Conclusion] The no-idling assumption should be restated wherever 'capable of running ~10^10 logical operations' appears, so that hardware-readiness claims are not separated from the noise model that produced them.
[Table I] The distance column mixes exact and estimated values. Consider adding a symbol or footnote that explicitly marks which entries are exact and which are upper-bound estimates from sQetch, and mirror this in the abstract's 'distance 18 and beyond' statement.
[Fig. 2(b)] The notation '(1B X, 1B Z)' and 'R=13' is not self-explanatory. Define whether these are numbers of shots, number of rounds per shot, or total syndrome-extraction rounds, so the reader can reconstruct the reported logical-error-rate denominators.
[Appendix H] The claims about sQetch being up to 800,000× faster are impressive but should be accompanied by a reproducible benchmark procedure, including hardware, dataset, and the exact version/commit of the repository referenced as [61].

Circularity Check

0 steps flagged · score 0.0 of 10

No circular derivation: mitten-code parameters, distances, and error rates are obtained from explicit constructions, exact/estimated computations, and Monte Carlo simulations, not from fitted inputs or self-citations.

full rationale

The central claims of the paper are self-contained rather than circular. Mitten codes are explicitly defined by base matrices over a non-abelian group algebra (Definition 4), and the claimed parameters—rate 20%, check weight 9, exact distances for the first five instances, canonical logical basis, gadget overheads, and decoder performance—are supported by concrete algebraic proofs, explicit code data (Table XIII), exact or clearly labeled estimated distance computations, and Stim-based circuit-level Monte Carlo simulation. No fitted parameter is dressed as a prediction: the reported logical error rates come from direct simulation outcomes (e.g., one error in ~10^11 syndrome extraction rounds for the [300,60,14] code, two failures in 15 billion surgery experiments for the [540,108,18] code), and the decoder's final stage is an exact integer-programming decoder benchmarked against external decoders (Tesseract, Cascade) on the gross code. Self-citations are present—[55], [56], [61], [79] are by overlapping authors—but they are used for construction frameworks, hardware estimates, and the sQetch tool, not as the sole load-bearing justification for the mitten-code-specific results. The sQetch distance estimator is open-source code and is used as a computational tool; the distances of the last three codes are explicitly marked as estimates rather than exact predictions. The paper is transparent that the simulation model applies uniform depolarizing noise to state preparation, two-qubit gates, and measurements with no idling noise (Fig. 2 caption), which is a genuine limitation for the neutral-atom extrapolation given the 5–24 ms SE cycles in Table I, but that is a modeling limitation, not circular reasoning. The circuit-level distances being 'likely preserved' via sQetch for some schedules is an acknowledged uncertainty, not an input renamed as an output. Therefore the derivation chain does not reduce to its own inputs, and the circularity score is 0.

Assumptions & free parameters 3 free parameters · 9 assumptions · 2 invented entities

The central construction rests on standard module theory over F2[G] plus explicit rank conditions; the performance numbers rest on the circuit-level depolarizing noise model (no idling) and on the authors' decoder. No physical constant or fitted parameter is used to produce the claimed logical error rates; the free parameters are engineering choices (decoder dispatch, surgery R, transport inputs) that set the context of the claims rather than their content.

free parameters (3)

Surgery syndrome-extraction rounds R = R = 11, 13, 13, 15, 19 across experiments (Fig. 2(b))
The quoted 'per quop' logical error rates are defined relative to the chosen R for each surgery experiment. The paper states all observed failures in the X basis are timelike errors, so larger R would suppress error rates further; the rates are conservative in R, but the quop capacity is R-dependent.
Telescoping decoder stage thresholds = BP/Relay-BP iteration counts and dispatch criteria (Appendix I, not stated numerically in main text)
Hand-chosen thresholds decide which shots pass to the exact integer-programming stage. These affect decoder accuracy and the claimed sub-millisecond latency estimates, though not the coded instance parameters. They are engineering choices, not physics fits.
Neutral-atom transport parameters = Taken from Ref [91] (demonstrated AOD transport)
SE cycle-time estimates of 5-24 ms (2 AOD pairs) assume literature transport speeds. These are inputs from prior experiments, not fitted here, but they set the hardware-feasibility claims.

assumptions (9)

standard math Group-algebra module theory over F2[G]; regular representation identities L(g)h=gh, R(g)h=hg^{-1} (Appendix A).
Invoked throughout the LP construction, the canonical logical basis, and the surgery gadgets.
standard math Cheeger inequality λ2/2 ≤ h(G) (Theorem 5, citing Chung [111]).
Used to certify expansion and hence distance preservation of the larger surgery and extractor gadgets where exact Cheeger computation is infeasible.
standard math Künneth formula and collapse of the Künneth spectral sequence (Appendix B.3, citing Weibel [108]).
Provides the homological derivation of the canonical logical basis under the square-invertibility condition.
domain assumption Circuit-level uniform depolarizing noise of strength p on state preparation, two-qubit gates, and measurements, with no idling noise (Section V, Fig. 2 caption).
All headline logical error rate and processing capacity claims rest on this model. It is stated openly, but it omits idle decoherence, atom loss, and movement errors that are physically relevant to the neutral-atom platform with 5-24 ms SE cycles.
domain assumption Stim simulator [80] faithfully simulates the circuit-level noise model.
Standard community assumption; all Monte Carlo numbers are generated with Stim.
domain assumption Randomized distance estimation (50M sQetch iterations + 50k BP+OSD runs) suffices to report distances ≤20, ≤22, ≤24 for the three largest instances (Table I).
Distances of 3 of 8 codes are upper-bound estimates from a randomized search for low-weight logicals, not proofs. The paper is transparent via the ≤ notation, but the claimed 'distance 18 and beyond' family-level statement leans on these estimates.
ad hoc to paper sQetch-verified SE schedules (hook-error-free or random coloration) preserve circuit-level distance (Section V, Appendix H.5).
The paper states schedules are searched to 'likely preserve' the circuit-level distance; a probabilistic estimate rather than a proof is load-bearing for the simulation results.
ad hoc to paper Full-rank condition on L(a1) and R(b1) ('square invertibility condition', Definition 16).
Defining constraint of the mitten family; it guarantees the canonical single-orbit logical basis, but restricts which non-abelian groups and entries are admissible.
domain assumption Surgery with R rounds fault-tolerantly implements the logical measurement; observed failures are timelike (Section V).
Per-quop error rates are quoted with finite R; the paper notes that increasing R suppresses the observed errors, so the quop capacity is a function of the protocol's round budget.

invented entities (2)

Mitten codes (non-abelian 1x2 lifted product code family) independent evidence
purpose: Rate-1/5, check-weight-9 quantum LDPC processor codes with a single-orbit canonical logical basis enabling low-overhead universal logic.
Explicit check matrices (Eq. 2) and construction data (Table XIII); distances computed exactly (first five) or bounded by two independent estimators (last three). Falsifiable by re-deriving the code parameters; not circular.
Magic port code LP(Rep(d_rep), B) independent evidence
purpose: Ancillary lifted product code bridging surface-code magic-state factories to the mitten processor for parallel |T> injection.
Distance exactly min(d_rep, d_B) proven in Theorem 6; explicit block check matrices in Fig. 7. The distance is proven rather than assumed, so the entity carries independent evidence.

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Cite this review

Pith. "Pith review of High-rate qLDPC processors." pith.science (2026). https://pith.science/paper/M6IBYFHE

@misc{pith2026260728795,
  author       = {Pith},
  title        = {Pith review of: High-rate qLDPC processors},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/M6IBYFHE}},
  note         = {Machine review of arXiv:2607.28795}
}

abstract

Despite significant progress on quantum low-density parity-check (qLDPC) codes, building qLDPC processors that are high-rate, high-throughput, hardware-friendly, and fast-to-decode remains a challenge. We introduce mitten codes, a family of qLDPC processor codes of encoding rate $20\%$ and check weight $9$, based on non-abelian groups. Their non-abelian structure evades distance bounds constraining abelian counterparts, allowing mitten codes to reach distance $18$ and beyond with just a few hundred data qubits. The logical operators of a mitten code are related by the group action, yielding a modular, low-overhead logical toolkit: full Clifford operations follow from bridging two reusable seed surgery gadgets or from a single fixed extractor. Furthermore, qLDPC processors based on mitten codes support high-rate surgery that executes many logical measurements in parallel, and parallel magic-state injection into all logical qubits at once. Under circuit-level noise, with our fast decoder, the $[\![300,60,14]\!]$ mitten code achieves, without extrapolation, a block logical error rate of ${\sim}10^{-11}$ per round at $0.1\%$ physical error rate (PER), while the $[\![ 975,195,\leq 24 ]\!]$ code reaches ${\sim}10^{-8}$ at $0.4\%$ PER. Decoding $15$ billion surgery experiments on the $[\![540,108,18]\!]$ code at $0.1\%$ PER, we observe only two logical failures, demonstrating a qLDPC processor capable of running ${\sim}10^{10}$ logical operations. Our decoder is compatible with sub-millisecond average latency per logical cycle, sufficient for real-time decoding on neutral atom hardware. Discovered by an end-to-end design pipeline built on sQetch, a distance estimator orders of magnitude faster than existing tools, and mapping efficiently onto near-term neutral atom and superconducting hardware, mitten codes open a practical path toward fault-tolerant quantum computation.

Figures

Figures reproduced from arXiv: 2607.28795 by the authors.

**Figure 1.** Mitten codes as fault-tolerant qLDPC processors (a) The J200, 40, 12K mitten code built from the lifted product of base matrices 𝐴 and 𝐵 defined over the group algebra 𝐹2[𝐺] of the non-abelian group 𝐺 = 𝐶4 × 𝐷10. The code consists of five blocks 𝐷1, . . . , 𝐷5 of |𝐺| = 40 physical data qubits and two blocks each of 𝑋-check and 𝑍-check ancilla qubits. Grey lines show the block-wise connectivity, while the connectivit… view at source ↗

**Figure 2.** Performance of mitten codes as qLDPC processors using our telescoping decoder. All simulations are performed under circuit-level noise with uniform depolarizing noise of strength 𝑝 applied to state preparation, two-qubit gates, and measurements, with no idling noise. (a) Memory performance of mitten codes. We plot the logical error rate per syndrome extraction round averaged over an equal number of 𝑋 and 𝑍 basis exp… view at source ↗

**Figure 3.** High-rate qLDPC processor discovery pipeline. Starting from the processor targets of Definition 3, the pipeline narrows the design space in three levels. The first level explores the space of groups and base matrices: theoretical distance bounds (Appendix G) first constrain the search space, and the fast codedistance estimator sQetch (Appendix H) then brute-force searches the remaining space to find codes with good… view at source ↗

Figures from the paper (10 more)

**Figure 4.** Figure 4: Hardware implementation. (a) In neutral atom hardware, each gate layer of syndrome extraction is implemented by entangling blocks of checks with corresponding blocks of data qubits, and permuting check qubits between layers. Here we show an example 𝑋-check qubit permut…

**Figure 5.** Figure 5: Surgery gadgets. (a) The seed graph surgery gadgets for measuring logical 𝑋¯/𝑍¯ operators constructed based on the group-structured canonical logical basis (Appendix B) where different logical operators are related by group action 𝑔 and the seed gadgets can be used to …

**Figure 6.** Figure 6: Parallel magic state injection scheme for mitten processor code [PITH_FULL_IMAGE:figures/full_fig_p049_6.png]

**Figure 7.** Figure 7: Block-labeled check matrices of LP(Rep(𝑑rep), 𝐵) Theorem 6. The distance of LP(Rep(𝑑rep), 𝐵) is the minimum of 𝑑𝐵 = 𝑑(𝑅(𝐵)) and 𝑑rep: 𝑑(LP(Rep(𝑑rep), 𝐵)) = min(𝑑rep, 𝑑𝐵). (E1) Proof. By Theorem 8, 𝑑(LP(Rep(𝑑rep), 𝐵)) ≤ min(𝑑rep, 𝑑𝐵). We therefore focus on the other dir…

**Figure 8.** Figure 8: Wall-clock time, in days on a logarithmic scale, required to screen approximately [PITH_FULL_IMAGE:figures/full_fig_p070_8.png]

**Figure 9.** Figure 9: Decoder comparison on the J144, 12, 12K gross code. We plot the logical error rate per round per logical qubit for memory experiments under uniform depolarizing circuit-level noise at physical error rates 𝑝 = 0.1% and 𝑝 = 0.2%, using the detector error models of Ref. […

**Figure 10.** Figure 10: Example atom movement in the SE cycle for the [PITH_FULL_IMAGE:figures/full_fig_p080_10.png]

**Figure 11.** Figure 11: Example atom movement in the SE cycle for the [PITH_FULL_IMAGE:figures/full_fig_p082_11.png]

**Figure 12.** Figure 12: SE cycle time for mitten codes and structured mitten codes. To represent current day hardware, [PITH_FULL_IMAGE:figures/full_fig_p083_12.png]

**Figure 13.** Figure 13: Thickness-3 decomposition of the Tanner graph of a mitten code, illustrated for the nonabelian [PITH_FULL_IMAGE:figures/full_fig_p088_13.png]

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Forward citations

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