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REVIEW 5 major objections 5 minor 25 references

A Power-Efficient Hardware Implementation of L-Mul

T0 review · 5 major / 5 minor · reviewed 2026-08-11 · deepseek-v4-flash

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Pith's one-line read This paper builds the first FPGA implementation of L-Mul, an approximate FP8 multiplier that replaces multiplication with additions and shifts, fitting in roughly 22 lookup tables with no DSP blocks.

desk verdict A credible first hardware mapping of L-Mul onto FPGA LUT/carry primitives with solid resource reporting; the headline accuracy claim overstates what Table VII actually shows. read the letter →

arxiv 2412.18948 v1 pith:MPZJ3GHS submitted 2024-12-25 cs.AR

Ruiqi Chen , Yangxintong Lyu , Han Bao , Bruno da Silva This is my paper · ORCID
classification cs.AR
keywords approximatecomputingL-MulFP8FPGAlookuptablecarrychainneuralnetworkinferenceenergy-efficienthardware
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

This paper claims to present the first FPGA-based approximate multiplier for the FP8 floating-point format, implementing the L-Mul algorithm. L-Mul replaces the mantissa product in FP8 multiplication with a shift-and-add approximation, and the authors show that this arithmetic maps onto FPGA lookup tables and carry chains using about 22 LUTs and no DSP blocks. In E4M3 format, the standalone multiplier runs at 617 MHz, consumes 1.34 mW, and keeps inference accuracy loss to 0.96% on CNNs and 3.01% on GCNs while cutting accelerator power. The paper argues this makes L-Mul practical for energy-constrained neural-network inference on FPGAs.

What carries the argument

The load-bearing object is the L-Mul identity, which replaces the mantissa product $m_x m_y$ in FP8 multiplication with the small power $2^{-\ell(m)}$, turning $(1+m_x)(1+m_y)$ into the sum $1+m_x+m_y+2^{-\ell(m)}$ while the exponents are added separately. The hardware realizes this with five LUT configurations and CARRY8 chains split into an exponent adder, a mantissa adder, and a post-processing unit; per-format constants fold the FP8 bias and mantissa-carry handling into a single $bias^*$ value, and CLB-level placement constraints keep LUT-to-carry-chain paths short.

What would settle it

A decisive check: simulate the paper's bit-level equations for all 65,536 E4M3 input pairs and compare with exact IEEE-754 FP8 multiplication. Any mismatch on inputs with exponent bits 0000 and nonzero mantissa, or exponent bits 1111, exposes the special-value handling gap; a same-target synthesis of the Verilog would independently confirm the roughly 22-LUT, no-DSP resource count.

Watch

Extended reading notes

Core claim

On its own terms, the paper establishes that L-Mul's approximate FP8 multiplication can be built entirely from standard FPGA logic primitives rather than DSP blocks. Five LUT configurations and CARRY8 chains form an exponent adder, a mantissa adder, and a post-processing unit that together compute the L-Mul result for a chosen FP8 exponent/mantissa split. For the widely used E4M3 format the result is a multiplier with about 22 LUTs, 25 flip-flops, four carry-chain units, a 4.85 ns critical path, and 1.34 mW of power. The paper further claims this is the first FPGA-based FP8 approximate multiplier, that it uses on average 10% fewer resources than previous 8-bit approximate FPGA multipliers, and that in CNN and GCN inference it removes all DSP blocks while keeping accuracy loss below 1% and around 3%, respectively.

Load-bearing premise

For the reported accuracy numbers to hold, every weight and activation entering the multiplier must be a normal finite FP8 value or exactly zero, because the hardware does not detect subnormals, infinities, or NaNs and would multiply them as if they were ordinary numbers.

Editorial extensions

If this is right

  • With the E4M3 format, the multiplier consumes 22 LUTs, 25 flip-flops, and four carry-chain units per product, with no DSP block and a 4.85 ns critical path at 617 MHz.
  • Across the six FP8 formats, resource use stays between 21 and 23 LUTs, so the same architecture covers E1M6, E2M5, E3M4, E4M3, E5M2, and E6M1 with near-identical cost.
  • In CNN inference, replacing exact INT8 multipliers with the FP8 L-Mul design removes 1,156 DSPs and cuts power from 9.46 W to 8.08 W at 250 MHz, with 0.96% accuracy loss.
  • In GCN inference, the design removes 512 DSPs and lowers power from 8.61 W to 8.23 W, with 3.01% accuracy loss.
  • Against prior 8-bit approximate FPGA multipliers, the design uses on average 10% fewer LUTs and sits on the area-latency Pareto frontier, with the second-lowest power-delay product.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • Editorial inference: the reported accuracy numbers implicitly assume flush-to-zero-like behavior, because the hardware's zero flag only detects an all-zero payload; feeding FP8 subnormals, infinities, or NaNs would produce silently wrong products.
  • Editorial inference: the 10% resource saving is measured against INT8 approximate multipliers of the same bit width, so a future subnormal-aware or exactly-specified FP8 baseline could change the comparison.
  • Editorial inference: since the FPGA circuit computes the same L-Mul arithmetic already validated on GPUs for large language models, LLM accuracy should carry over, but the subnormal blind spot may matter more for low-precision transformer activations.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

5 major / 5 minor

Summary. The manuscript presents a primitive-level FPGA implementation of the L-Mul approximate FP8 multiplier for AMD UltraScale/UltraScale+ devices, mapping the computation onto LUTs, carry chains, and CLB-level placement constraints. It reports resource, frequency, and power results for six FP8 formats, compares the E4M3 deployment with prior 8-bit approximate multipliers and an exact IP core, and evaluates DNN inference accuracy loss and accelerator-level power. The stated contributions are that this is the first FPGA-based FP8 approximate multiplier, that it reduces resource consumption by about 10% relative to previous 8-bit designs, and that it achieves the highest accuracy, energy efficiency, and lowest latency among 8-bit designs.

Significance. The underlying hardware idea is relevant and plausible: reducing FP8 multiplication to add/shift operations via L-Mul and implementing it with LUT/carry primitives yields a compact DSP-free operator (about 22 LUTs), and the error evaluation against exact FP8 is an independent, non-circular benchmark. The paper gives enough architectural detail to be reproducible, and the synthesis-based resource counts across formats are a useful data point. However, the headline comparison claims are internally inconsistent with the reported tables, and several specification gaps (subnormal handling, consistency of Eq. (5), and normalization of power comparisons) must be resolved before the significance of the hardware claims can be assessed.

major comments (5)
  1. [Section I, second contribution bullet; Section IV-D, Table VII] The claim that "among 8-bit designs, ours achieves the highest accuracy" is contradicted by Table VII: L-Mul E4M3 has average accuracy losses of -0.96% (CNN) and -3.01% (GCN), while exact INT8 has -0.10% and -2.77%, and exact FP8 E4M3 has -0.04% and -1.96%. Section IV-D itself states, "Although L-Mul exhibits the highest accuracy loss..." Please restrict the accuracy claim to approximate multipliers or remove it from the abstract and contribution list.
  2. [Section IV-C, Table VI] The latency and energy-efficiency claims are not supported by the reported data. The proposed design has a delay of 4.85 ns, whereas the AMD-Xilinx exact design reports 3.54 ns and Van Toan reports 4.65 ns. The power comparison is also not normalized: 1.34 mW at 617 MHz cannot be directly compared with 0.432 mW at 100 MHz, and the designs are on different device families (7-series versus UltraScale+). Please report energy per operation (e.g., power/frequency) under matched conditions, and include an exact FP8 multiplier baseline on the same device and at the same frequency to substantiate the FP8-specific efficiency claim.
  3. [Section III-B, zero-flag logic] The zero detection only checks whether fp8_x[6:0] == 7'b0 or fp8_y[6:0] == 7'b0. Subnormal FP8 numbers (exponent field 0000 with nonzero mantissa) and reserved exponent patterns (infinity/NaN) are therefore not detected; they are treated as normal numbers and produce incorrect outputs. Since the paper claims an FP8 implementation under IEEE-754 conventions, please either implement IEEE-754 special-case handling or explicitly state and justify a flush-to-zero/no-special-values assumption, and verify that the DNN workloads used in Section IV-D satisfy that assumption.
  4. [Section II-A, Eq. (5)] Eq. (5) does not follow from Eq. (4). The L-Mul correction term 2^{-l(m)} should appear as 2^{m-l(m)}/2^m in a numerator of the form (2^m + x + y + 2^{m-l(m)})/2^m, whereas the printed numerator "1 + x + y + 2^{l(m)}" gives a correction of 2^{l(m)-m}. The two coincide only when m = 3, so the bit-level representation as written is wrong for the other FP8 formats implemented in Table V. Please correct Eq. (5) and re-verify the synthesized arithmetic for m != 3.
  5. [Section I, first contribution bullet; Table VI] The claimed "average 10%" resource reduction is not reproducible from Table VI. Averaging the listed LUT counts for the previous 8-bit designs gives approximately 48-52 LUTs, compared with 22 for the proposed design, which is a reduction of roughly 55%, not 10%. Please specify the exact comparator set and the calculation used for the 10% figure.
minor comments (5)
  1. [Section III-B, adder description] The bit-width descriptions of the Exponent-Adder and Mantissa-Adder appear swapped: for a format with e exponent bits and m mantissa bits, the exponent adder should be e/e+1 bits and the mantissa adder should be m/m+1 bits, not the reverse as written.
  2. [Section II-A, Eq. (4)] The piecewise definition of l(m) is contradictory at m = 4: it says both "3 if m = 4" and "4 if m >= 4". The last case should presumably be "m > 4".
  3. [Section IV-A, Eq. (12)] The definition of NED as an average of ED_i/max(ED) is not the standard normalized error distance; please clarify the definition or rename the metric to avoid confusion.
  4. [Section IV-D, Table VIII] The accelerator comparison would be stronger if it reported measured inference accuracy and throughput for the deployed accelerators, not only resource and power, since Table VII reports software-evaluated accuracy rather than end-to-end hardware accuracy.
  5. [Section II-A] Minor language issues include "a real numbers is encoded" and "implicit" in place of "implicit"; please copyedit the manuscript.

Circularity Check

0 steps flagged · score 0.0 of 10

No significant circularity: the L-Mul approximation is imported from external prior work, hardware metrics come from synthesis, and accuracy is benchmarked against exact FP8/FP32 baselines.

full rationale

The paper's derivation chain is self-contained with respect to circularity. The L-Mul approximation in Eq. (4), including the piecewise term l(m), is taken directly from the external prior work [2] (Luo and Sun), not derived from the paper's own hardware results. The hardware design in Section III-B implements Eq. (5), which is a bit-level transcription of Eq. (4) combined with the IEEE-754 FP8 encoding formulas Eqs. (1)-(2); the output is therefore not fed back into the design as an input. The error evaluation in Table IV is computed against exact FP8 multiplication using the standard metrics defined in Eqs. (8)-(12), which are independent of the presented synthesis results. The hardware resource, frequency, delay, and power numbers in Tables V, VI, and VIII are obtained from AMD Vivado synthesis, placement, and power analysis, and from previously published external designs; no free parameter is fitted to force the comparisons. The DNN accuracy results in Table VII are measured against FP32, FP8, and INT8 baselines on standard CNN and GCN datasets using external accelerators. There is an internal inconsistency between the abstract's claim of 'highest accuracy' and Table VII, where L-Mul has the largest accuracy loss, but this is a correctness and consistency concern, not a circular-reasoning step. No load-bearing self-citation is present, and no prediction reduces by construction to a fit or to an author-imported ansatz.

Assumptions & free parameters 0 free parameters · 5 assumptions · 0 invented entities

No free parameters are introduced by this paper; the numerical choices are inherited from the L-Mul algorithm and IEEE-754. The central claim rests on four domain assumptions: the approximation quality of L-Mul, normal-only FP8 inputs, correct FPGA primitive behavior, and the validity of Vivado resource/power estimates.

assumptions (5)
  • domain assumption L-Mul's piecewise constant l(m)=m if m<=3, 3 if m=4, 4 if m>=4 approximates the mantissa product adequately for neural network workloads.
    Eq. 4 is taken directly from Luo and Sun [2] and is not derived or validated here; all reported hardware accuracy inherits this approximation.
  • domain assumption Inputs to the multiplier are normal FP8 numbers or exact zero; subnormals, infinities, and NaNs do not occur in the evaluated workloads.
    The zero detection and normalization logic in Section III-B and Eq. 6 only handle the all-zero encoding; subnormals and reserved exponent patterns would be miscomputed.
  • standard math FP8 follows IEEE-754 with hidden bit 1 for nonzero exponent and bias=2^(e-1)-1.
    Used to derive Eq. 5 and the bias* table in Section III-B.
  • domain assumption AMD UltraScale/UltraScale+ CLB primitives (LUT6_2, CARRY8) behave as documented by the CLB user guide.
    The resource counts, timing, and the claimed placement optimization depend on the documented LUT and carry-chain structures.
  • domain assumption Vivado synthesis and power analysis provide accurate estimates of resource utilization, frequency, and dynamic power.
    All hardware metrics in Tables V, VI, and VIII come from Vivado 2022.2, not from measured board power or oscilloscope measurements.

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Pith. "Pith review of A Power-Efficient Hardware Implementation of L-Mul." pith.science (2026). https://pith.science/paper/MPZJ3GHS

@misc{pith2026241218948,
  author       = {Pith},
  title        = {Pith review of: A Power-Efficient Hardware Implementation of L-Mul},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/MPZJ3GHS}},
  note         = {Machine review of arXiv:2412.18948}
}
read the original abstract

Multiplication is a core operation in modern neural network (NN) computations, contributing significantly to energy consumption. The linear-complexity multiplication (L-Mul) algorithm is specifically proposed as an approximate multiplication method for emerging NN models, such as large language model (LLM), to reduce the energy consumption and computational complexity of multiplications. However, hardware implementation designs for L-Mul have not yet been reported. Additionally, 8-bit floating-point (FP8), as an emerging data format, offers a better dynamic range compared to traditional 8-bit integer (INT8), making it increasingly popular and widely adopted in NN computations. This paper thus presents a power-efficient FPGAbased hardware implementation (approximate FP8 multiplier) for L-Mul. The core computation is implemented using the dynamic reconfigurable lookup tables and carry chains primitives available in AMD Xilinx UltraScale/UltraScale+ technology. The accuracy and resource utilization of the approximate multiplier are evaluated and analyzed. Furthermore, the FP8 approximate multiplier is deployed in the inference phase of representative NN models to validate its effectiveness.

Figures

Figures reproduced from arXiv: 2412.18948 by the authors.

Figure 2
Figure 2. Typical AMD FPGA configurable logic block (CLB) structure [ [PITH_FULL_IMAGE:figures/full_fig_p002_2.png] view at source ↗
Figure 1
Figure 1. The demonstration of the INT8 and FP8 (E4M3) defined in IEEE [PITH_FULL_IMAGE:figures/full_fig_p002_1.png] view at source ↗
Figure 3
Figure 3. Hardware fine-grained architecture for L-Mul. the sign bit could be omitted, as it can be handled through an XOR operation. Observing the above equation, it is evident that for hardware circuit design, only mx · my involves a multiplication operation. The remaining operations can be implemented using addition or linear operations such as shift￾ing. To alleviate the potential bottleneck caused by mantissa multiplicat… view at source ↗
Figures from the paper (2 more)
Figure 4
Figure 4. Figure 4: The normalized number of unique error occurrences under different [PITH_FULL_IMAGE:figures/full_fig_p005_4.png]
Figure 5
Figure 5. Figure 5: The Pareto analysis under area and latency. [PITH_FULL_IMAGE:figures/full_fig_p005_5.png]

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