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A cryo-CMOS predecoder can handle realistic circuit-level noise on the surface code, cutting logical error rates by up to six orders of magnitude and syndrome bandwidth by up to 3780x, all within a 0.56 mW power envelope.

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2026-08-03 17:20 UTC pith:N3ES2T3A

load-bearing objection Genuine extension of cryogenic predecoding to circuit-level noise, with a credible cryo-CMOS implementation, but the headline numbers rest on a single tuned noise model and need sensitivity analysis. the 3 major comments →

arxiv 2512.09807 v2 pith:N3ES2T3A submitted 2025-12-10 quant-ph cs.ARcs.ET

Pinball: A Cryogenic Predecoder for Surface Code Decoding Under Circuit-Level Noise

Alexander Knapen , Guanchen Tao , Jacob Mack , Tomas Bruno , Mehdi Saligane , Dennis Sylvester , Qirui Zhang , Gokul Subramanian Ravi This is my paper
classification quant-ph cs.ARcs.ET
keywords quantum error correctionsurface codecryogenic predecodingcryo-CMOScircuit-level noiselogical error ratesyndrome bandwidthminimum-weight perfect matching
verification ladder T0 review T1 audit T2 compute T3 formal T4 reserved

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper seeks to establish that a lightweight predecoder placed inside the cryostat can handle the majority of surface-code error syndromes even under realistic, circuit-level noise, not just simplified noise models used by earlier cryogenic predecoders. If true, this removes a major scaling bottleneck for fault-tolerant quantum computers: the 4K-to-room-temperature syndrome bandwidth and the power cost of streaming raw error data out of the refrigerator. The authors derive simple predecoding primitives from a detailed analysis of how errors are generated and propagate through the syndrome measurement circuits, then organize them into a nine-stage pipeline that prevents conflicting assignments. Their simulations show the design matches the logical error rate of a full room-temperature decoder for code distances of 7 and above, while reducing syndrome bandwidth dramatically.

Core claim

Pinball is the first cryogenic predecoder designed for circuit-level noise. By categorizing length-1 errors into space-like, time-like, single-qubit spacetime-like, and hook spacetime-like classes, and by deriving the correction logic for each from the actual CNOT ordering in the measurement circuits, the paper shows that a modest CMOS pipeline can decode almost all syndromes locally. Under the SI1000 noise model, this predecoder achieves a logical error rate near that of minimum-weight perfect matching without predecoding for d≥7, outperforms the state-of-the-art cryogenic predecoder Clique by nearly six orders of magnitude at p=5e-4 and d=11, and reduces total 4K-to-RT syndrome bandwidth b

What carries the argument

The central object is the Pinball predecoder: a nine-stage pipeline of predecoding primitives over a per-round subgraph of the surface-code decoding graph. Each primitive is a two-level combinational logic cell—an AND gate that checks whether a pair of adjacent syndromes is active, producing correction bits, and XOR gates that clear those syndromes afterward. The stages group conflict-free primitives covering bulk space-like, edge space-like, time-like, single-qubit spacetime-like, and hook spacetime-like edges, ordered by measured error-class frequency so that common error classes are resolved first. Clearing syndromes as corrections are assigned prevents double-counting and enables a light

Load-bearing premise

The load-bearing premise is that the error-class frequencies and error correlations used to choose the pipeline stage order—measured under the SI1000 noise model—remain representative for real devices; if a device's dominant error class differs, the ordering and coverage can degrade, undermining the claimed LER gains.

What would settle it

Run the Pinball pipeline, without re-tuning, against a second independent circuit-level noise model or measured device data with a different CNOT ordering and error-rate balance; if L1 coverage drops sharply and the logical error rate no longer tracks the no-predecoder MWPM baseline for d≥7, the claim that the derived primitives and ordering suffice under realistic noise is falsified.

Watch this falsifier — get emailed when new claim-graph text bears on it.

If this is right

  • 4K-to-RT syndrome bandwidth can drop by up to 3780.72x, enabling higher-distance surface codes to fit within a 1.5 W cryogenic power budget.
  • A predecoded system can achieve logical error rates near those of full MWPM decoding without predecoding, for code distances of 7 and above.
  • The predecoder alone reduces logical error rate by up to 6 orders of magnitude versus the prior cryogenic predecoder Clique under the SI1000 circuit-level noise model.
  • Cryo-CMOS, combined with workload-aware voltage/frequency scaling and body biasing, is a viable lower-power alternative to SFQ for cryogenic decoding, with up to 22.2x power reduction versus a fixed high-performance mode.
  • Under a 1.5 W 4 K budget, the design supports up to 2,668 logical qubits at distance 21 at p=1e-3, comfortably within the early fault-tolerant regime.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • If real-device noise differs from the SI1000 model—for example, if two-qubit gate errors become dominant relative to measurement errors—the pipeline stage ordering may need to be re-tuned; the modular design permits this, but it has not been demonstrated on a second noise model.
  • The same primitive-based, pipelined approach could likely be adapted to other topological or LDPC codes with local decoding graphs, although the error-class derivation and coverage would need to be redone per code.
  • Combining Pinball with a room-temperature predecoder such as Promatch may be bottlenecked by the RT stage's accuracy; a better RT predecoder would expose Pinball's full fidelity benefit.
  • A falsifiable test would be to run Pinball on measured syndrome data from a real device (or a second independent circuit-level noise model) and check that L1 coverage and LER remain near the no-predecoder baseline.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit.

Referee Report

3 major / 4 minor

Summary. The paper presents Pinball, a cryogenic predecoder for surface-code quantum error correction under circuit-level noise. It derives local predecoding primitives from an analysis of how errors propagate through the syndrome-measurement circuits (space-like, time-like, and spacetime-like edges, including hook errors), organizes these primitives into a nine-stage conflict-free pipeline, and implements the design in 22nm FDSOI cryo-CMOS with voltage/frequency scaling. Using Stim-generated circuit-level noise (SI1000) and Pymatching as the L2 decoder, the paper reports that Pinball substantially outperforms the prior cryogenic predecoder Clique in L1 coverage, L1 accuracy, and logical error rate (LER), reduces 4K-to-RT syndrome bandwidth by up to 3780.72x, achieves LER near parity with a no-predecoder MWPM system for d>=7, and consumes less than 0.56mW at 4K. The central claims are that realistic circuit-level errors can be largely decoded in the cryostat without sacrificing logical fidelity.

Significance. If the results hold, this is a strong systems contribution: it is the first cryo-CMOS predecoder designed for circuit-level noise, with a concrete implementation and 4K-characterized hardware evaluation. The circuit-level derivation of the predecoding primitives is non-circular and is a genuine step beyond Clique's phenomenological approach. The paper also ships source code and uses a standard simulation stack (Stim, Pymatching, large Monte Carlo samples), which aids reproducibility. The architecture-technology co-optimization, including LP/HP modes exploiting the per-round latency imbalance, is creative and well motivated. However, several load-bearing claims depend on the SI1000 noise model and on statistical evidence that is not fully reported.

major comments (3)
  1. [Sec. IV-C, Tab. II, and Sec. VI] The pipeline stage order and primitive grouping are chosen from an error-class frequency distribution measured on 10^5 SI1000 shots, and the headline LER/coverage results are then evaluated on the same SI1000 noise model. Because the stages are serialized and clear syndromes, the ordering is part of the algorithm's correctness and not merely a performance knob. The paper emphasizes modularity and freedom to reorder, but no sensitivity experiment is provided: no reordering of the B/M/ST/H/E stages, no variation of relative error source rates, and no second circuit-level noise model or alternative CNOT schedule. Without such an analysis, the 'nearly six orders of magnitude' LER improvement is a property of Pinball tuned to SI1000, not a demonstrated property of the design across plausible device variations. I request a sensitivity study, at minimum reordering stages and testing at least on
  2. [Sec. III-D, Fig. 17] The paper explicitly describes a false-negative failure mode: Pinball can clear edge syndromes after incorrectly pairing bulk edges and therefore fail to raise the 'complex' flag, so such blocks bypass the L2 MWPM decoder entirely. This is a direct path to logical error, and the near-parity LER claim in Fig. 24 depends on these events being sufficiently rare. The frequency of this failure mode is never quantified, nor is its contribution to the LER in Figs. 22-24. Please report the false-negative rate (e.g., the fraction of blocks marked non-complex that are decoded incorrectly, or the fraction of logical errors attributable to such blocks) as a function of d and p. Without this, the reader cannot assess whether the admitted failure mode is a negligible edge case or a hidden limitation of the six-orders claim.
  3. [Sec. V-B, Figs. 22-24] The central LER comparisons are reported without confidence intervals or the number of observed logical errors. With up to 10^9 syndrome blocks, a LER of 10^-7 corresponds to about 100 observed errors, and at lower LERs the sampling uncertainty is comparable to or larger than several of the reported 'orders of magnitude' gaps (e.g., the p=10^-4, d=7 'nearly seven orders' statement). Please provide confidence intervals (Wilson/binomial or exact Poisson) or at least the number of logical errors for each plotted point, and state the simulation stopping rule. This is also needed to evaluate the 'near parity' claim in Fig. 24, where small absolute LER differences are otherwise hard to interpret.
minor comments (4)
  1. [Sec. VI-A, Fig. 20] The bandwidth-savings metric is never defined precisely. The text reports finite savings (e.g., 3780.72x at d=5, p=10^-4) even in regimes where L1 coverage is near 100%, and 'full coverage' at d=3. Please state the formula used for bandwidth savings and how cases with zero complex blocks are handled.
  2. [Tab. III] The table columns for VBN/VBP are visually misaligned, especially for the supply voltages below 0.54 V, and the 'Fails to Oscillate' entry is ambiguous. Please reformat so the body-bias values are clearly associated with each supply voltage.
  3. [References] References [71] and [72] appear to be the same paper (same title, authors, and venue). Please merge or disambiguate.
  4. [Sec. VI-A] The sentence 'Note: some data points omitted in due to insufficient L1 coverage' contains a typo and should read '...omitted due to insufficient L1 coverage.' Also, the text states 'nearly six orders' and 'nearly seven orders' in different places; keeping a single terminology and tying it to the corresponding figure point would improve clarity.

Circularity Check

0 steps flagged

No significant circularity: Pinball's primitives derive from circuit-level error propagation and are evaluated with independent Stim/Pymatching simulations; the pipeline-order tuning is an in-sample robustness limitation, not a definitional circularity.

full rationale

The paper's core derivation is self-contained: Sections III-A through III-C derive space-like, time-like, spacetime-like, and hook-error primitives from the CNOT schedule in Fig. 3 and Pauli propagation through the syndrome-measurement circuits, not from the simulation results that are later reported. The only data-dependent algorithmic choice is the pipeline stage ordering in Section IV-C, where 10^5 SI1000 shots are used to rank error-class frequencies in Tab. II and the authors state 'Empirically, we observed best performance when checking time-like errors first.' This is in-sample hyperparameter selection on the same noise model later used for evaluation, which is a robustness/overfitting concern rather than a circular reduction: the headline LER, coverage, and bandwidth figures (Figs. 19-24) come from separate Stim/Pymatching Monte Carlo runs, and no equation in the paper defines those outcomes as a function of the fitted ordering. The spacetime/hook coverage gains would exist even without the tuned ordering. Baselines Clique [54] and Promatch [1] are re-evaluated under SI1000 rather than taken on faith; although [54] shares a co-author, Fig. 5 independently reproduces Clique's degradation, so the self-citation is not load-bearing. No uniqueness theorem or ansatz is imported from the authors' prior work. The admitted failure mode in Sec. III-D (Fig. 17) and the modularity discussion in Sec. IV-C explicitly document sensitivity to stage ordering, supporting a validity caveat rather than circularity.

Axiom & Free-Parameter Ledger

4 free parameters · 6 axioms · 0 invented entities

No new physical entities are postulated. The 'artificial neighbors' used for edge space-like errors are a logic-internal construct in the predecoder, not a physical object. The paper's load-bearing inputs are the SI1000 noise model, the reset-each-round assumption, and the chosen pipeline operating points; the free parameters are design choices tuned to the evaluation benchmark.

free parameters (4)
  • Pipeline stage ordering and grouping (B/M/ST/H/E order) = Time-like first; bulk space-like B(1)-B(4); then ST(1), ST(2), H, E, complex detect (Fig. 16)
    Order chosen by error-frequency analysis on 10^5 SI1000 shots and 'empirically, we observed best performance when checking time-like errors first' (Sec. IV-C, Tab. II). This is a design parameter tuned to the evaluation noise model, not derived from first principles.
  • Latency budget split for HP/LP modes = 100 ns predecode budget in last round; 800 ns LP processing in first d-1 rounds; 200 ns supply switching
    Conservative allocation from the 1 us round budget (Sec. IV-E); not fitted to LER but is an assumed design target that affects reported power/energy.
  • HP/LP supply and frequency operating points = HP: 0.8 V, 100 MHz; LP: 0.48 V, 12.5 MHz (with body bias), 0.54 V without
    Selected from 4 K ring-oscillator characterization (Tab. III) to meet latency/energy targets (Sec. V-C); hardware tuning rather than a physics parameter.
  • Physical error rate range p = 10^-4 to 10^-2
    Evaluation range chosen to span near-term to long-term hardware; not fitted, but limits generality.
axioms (6)
  • domain assumption Circuit-level noise model SI1000 [28] accurately represents real superconducting qubit noise and is the correct benchmark.
    All LER/coverage/bandwidth headlines are computed under this model; no alternative-model validation is given (Sec. V-A, Sec. VI).
  • standard math For CSS surface codes, X and Z decoding are independent and symmetric, so simulating only Z errors suffices.
    Invoked in Sec. V-B; standard in the QEC decoding literature.
  • domain assumption Ancilla qubits are reset after each measurement round, so every length-1 error chain spans at most two rounds; streaming over consecutive pairs S_{i-1}, S_i loses no accuracy.
    Invoked in Sec. III; if reset is imperfect or leakage occurs, coverage may break.
  • standard math The decoding graph and error propagation rules for the syndrome measurement circuits are as described (Pauli Z/X propagation through CNOTs, hook errors).
    Sec. II-B and Sec. III; standard stabilizer circuit analysis.
  • domain assumption Pymatching (MWPM) is a near-optimal L2 decoder, and any LER degradation with Pinball at L1 versus bare MWPM is negligible for d>=7.
    Used for L2 decoding and baseline in Sec. V-B and Fig. 24.
  • domain assumption A 1.5 W cooling budget at 4 K and 1 us syndrome generation latency are representative constraints.
    From [45], [57]; used for power/energy projections (Sec. IV-E, Sec. VI-D).

pith-pipeline@v1.3.0-alltime-deepseek · 24727 in / 16497 out tokens · 152354 ms · 2026-08-03T17:20:08.261806+00:00 · methodology

0 comments
read the original abstract

Scaling fault tolerant quantum computers, especially cryogenic systems based on the surface code, to millions of qubits is challenging due to poorly-scaling data processing and power consumption overheads. One key hurdle is the design of real-time quantum error correction (QEC) decoders, which demands high data rates for error processing; this is particularly apparent in systems with cryogenic qubits and room temperature (RT) decoders. In response, cryogenic predecoding using lightweight logic has been proposed to handle sparse errors in the cryogenic domain. However, prior work only accounts for a subset of error sources in real-world quantum systems with limited accuracy, often degrading performance below useful levels in practical scenarios. Moreover, prior reliance on SFQ logic precludes detailed architecture-technology co-optimization. To address these limitations, this paper introduces Pinball, a comprehensive design in cryogenic CMOS of a QEC predecoder for the surface code tailored to realistic, circuit-level noise. By accounting for error generation and propagation through QEC circuits, our design achieves higher predecoding accuracy, outperforming logical error rates (LER) of the current state-of-the-art (SOTA) cryogenic predecoder by nearly six orders of magnitude. Remarkably, despite operating under much stricter power and area constraints, Pinball also reduces LER by 32.58x and 5x, respectively, compared to SOTA RT predecoder and RT ensemble configurations. By increasing cryogenic coverage, we also reduce syndrome bandwidth up to 3780.72x. Through co-design with 4 K-characterized 22nm FDSOI technology, we achieve peak power consumption under 0.56 mW. Voltage/frequency scaling and body biasing enable 22.2x lower typical power consumption, yielding up to 67.4x total energy savings. Assuming a 1.5 W 4 K power budget, our predecoder supports up to 2,668 logical qubits at d=21.

Figures

Figures reproduced from arXiv: 2512.09807 by Alexander Knapen, Dennis Sylvester, Gokul Subramanian Ravi, Guanchen Tao, Jacob Mack, Mehdi Saligane, Qirui Zhang, Tomas Bruno.

Figure 1
Figure 1. Figure 1: The classical hardware landscape for QEC decoding. Relative to [PITH_FULL_IMAGE:figures/full_fig_p001_1.png] view at source ↗
Figure 2
Figure 2. Figure 2: (a) d = 5 rotated surface code lattice. (b) Corresponding decoding graph for Z errors in one QEC round. (c, d) Unit cells for the Z-error decoding graph under (c) phenomenological noise and (d) circuit-level noise. 2 1 4 3 (a) 1 2 3 4 (b) [PITH_FULL_IMAGE:figures/full_fig_p003_2.png] view at source ↗
Figure 3
Figure 3. Figure 3: Syndrome measurement circuits for detecting (a) [PITH_FULL_IMAGE:figures/full_fig_p003_3.png] view at source ↗
Figure 5
Figure 5. Figure 5: LER achieved under circuit-level noise by Clique [54]. [PITH_FULL_IMAGE:figures/full_fig_p004_5.png] view at source ↗
Figure 6
Figure 6. Figure 6: Distribution of maximum-length error chains in the SI1000 noise [PITH_FULL_IMAGE:figures/full_fig_p005_6.png] view at source ↗
Figure 7
Figure 7. Figure 7: Formation of a space-like error. is applicable for any Pauli-type error, since X errors are symmetric and Y errors can be decomposed into Z and X components. A. Space-like Errors Space-like errors correlate two syndromes within the same syndrome measurement round [PITH_FULL_IMAGE:figures/full_fig_p006_7.png] view at source ↗
Figure 8
Figure 8. Figure 8: Full coverage for space-like errors in the predecoding subgraph. Green [PITH_FULL_IMAGE:figures/full_fig_p006_8.png] view at source ↗
Figure 9
Figure 9. Figure 9: Formation of a time-like error. Round i (0, 0, i) (0, 0, i-1) Round i-1 [PITH_FULL_IMAGE:figures/full_fig_p006_9.png] view at source ↗
Figure 10
Figure 10. Figure 10: Full coverage for time-like errors in the predecoding subgraph which [PITH_FULL_IMAGE:figures/full_fig_p006_10.png] view at source ↗
Figure 11
Figure 11. Figure 11: Formation of a spacetime-like error. (0, 0, i) (0, 1, i-1) (1, 0, i) Round i Round i-1 [PITH_FULL_IMAGE:figures/full_fig_p007_11.png] view at source ↗
Figure 12
Figure 12. Figure 12: Full coverage for single-qubit, spacetime-like errors in the prede [PITH_FULL_IMAGE:figures/full_fig_p007_12.png] view at source ↗
Figure 15
Figure 15. Figure 15: By sequencing conflicting predecoding primitives and clearing [PITH_FULL_IMAGE:figures/full_fig_p008_15.png] view at source ↗
Figure 16
Figure 16. Figure 16: The hardware design for Pinball. (a) The two-level combinational logic implementing a predecoding primitive. (b) Pinball is organized into a pipeline, [PITH_FULL_IMAGE:figures/full_fig_p009_16.png] view at source ↗
Figure 17
Figure 17. Figure 17: A set of errors which Pinball would both fail to decode correctly [PITH_FULL_IMAGE:figures/full_fig_p010_17.png] view at source ↗
Figure 19
Figure 19. Figure 19: L1 coverage comparison between Pinball (solid) and Clique (dashed) [PITH_FULL_IMAGE:figures/full_fig_p011_19.png] view at source ↗
Figure 20
Figure 20. Figure 20: Bandwidth savings comparisons between Pinball and Clique, [PITH_FULL_IMAGE:figures/full_fig_p012_20.png] view at source ↗
Figure 22
Figure 22. Figure 22: Logical error rate comparison between Pinball and Clique. [PITH_FULL_IMAGE:figures/full_fig_p012_22.png] view at source ↗
Figure 23
Figure 23. Figure 23: Logical error rate comparison between Pinball, Promatch, and the [PITH_FULL_IMAGE:figures/full_fig_p013_23.png] view at source ↗
Figure 25
Figure 25. Figure 25: Area and power analysis of Pinball’s HP and LP mode with [PITH_FULL_IMAGE:figures/full_fig_p014_25.png] view at source ↗
Figure 26
Figure 26. Figure 26: Total energy savings combines the benefits of predecoding and LP [PITH_FULL_IMAGE:figures/full_fig_p014_26.png] view at source ↗

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