Paper Citation Record · LEDGER

VeriReason: Reinforcement Learning with Testbench Feedback for Reasoning-Enhanced Verilog Generation

As of 7 August 2026, this Paper Citation Record lists 0 of 0 outbound references and 9 inbound Pith citation observations for arXiv:2505.11849.

A citation records a reference. It does not transfer a finding from one paper to another.

pith.paper-citation-record.v1
2505.11849 v1

Coverage vector

measured 0 of 0 reference resolution

Typed states for the displayed outbound observations.

Source: paper_references, paper_reference_links

measured 9 of 9 standing notices

One-hop event checks from named stored sources.

Source: scholarly_work_events, retraction_status_cache, observed 2026-08-07T06:34:17.273281+00:00

measured 9 of 9 inbound itemization

Pith citing papers itemized under the disclosed page cap.

Source: paper_references, paper_reference_links, observed 2026-08-06T14:21:43.837734Z

measured 0 of 1 external citation measurements

A source-named dated measurement, never combined with another source.

Source: arxiv_reference, observed 2026-07-03T21:28:59.386612Z

Reference resolution

0 of 0 outbound references displayed

verified exact0
verified fuzzy0
unresolved0
parse uncertain0
malformed identifier0
metadata mismatch0

External citation measurements

No source-named external measurement is stored.

Outbound references

No outbound reference observations are available for this paper version.

Pith citing papers

Observation 4acb3727-4321-4a14-9ca3-ee836cc68ea5 · inbound

MCP4EDA: LLM-Powered Model Context Protocol RTL-to-GDSII Automation with Backend Aware Synthesis Optimization cites this paper.

MCP4EDA: LLM-Powered Model Context Protocol RTL-to-GDSII Automation with Backend Aware Synthesis Optimization VeriReason: Reinforcement Learning with Testbench Feedback for Reasoning-Enhanced Verilog Generation

Reference 8

Resolution: unresolved; no resolver link, observed 2026-08-06T14:21:43.837734Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation d22ec9a5-ac7c-4ddc-ab7f-d7d6c25c6458 · inbound

VeriInteresting: An Empirical Study of Model Prompt Interactions in Verilog Code Generation cites this paper.

VeriInteresting: An Empirical Study of Model Prompt Interactions in Verilog Code Generation VeriReason: Reinforcement Learning with Testbench Feedback for Reasoning-Enhanced Verilog Generation

Reference 26

Resolution: verified exact; arxiv_id, observed 2026-05-16T07:47:32.933232Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation b9ab9fe6-ff8c-4d6e-91a0-7212e979b784 · inbound

InCoder-32B-Thinking: Industrial Code World Model for Thinking cites this paper.

InCoder-32B-Thinking: Industrial Code World Model for Thinking VeriReason: Reinforcement Learning with Testbench Feedback for Reasoning-Enhanced Verilog Generation

Reference 37

Resolution: verified exact; arxiv_id, observed 2026-05-13T18:58:08.673518Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation e4db035d-c5d8-4156-a81b-7c84c5bfe948 · inbound

TOPCELL: Topology Optimization of Standard Cell via LLMs cites this paper.

TOPCELL: Topology Optimization of Standard Cell via LLMs VeriReason: Reinforcement Learning with Testbench Feedback for Reasoning-Enhanced Verilog Generation

Reference 36

Resolution: verified exact; arxiv_id, observed 2026-05-10T14:15:29.339619Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation 34f152cd-939d-4eed-b4b0-59256def6751 · inbound

COEVO: Co-Evolutionary Framework for Joint Functional Correctness and PPA Optimization in LLM-Based RTL Generation cites this paper.

COEVO: Co-Evolutionary Framework for Joint Functional Correctness and PPA Optimization in LLM-Based RTL Generation VeriReason: Reinforcement Learning with Testbench Feedback for Reasoning-Enhanced Verilog Generation

Reference 34

Resolution: verified exact; arxiv_id, observed 2026-05-10T10:34:28.916213Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation 0089bb35-1293-4792-8a69-e42e58acb428 · inbound

Interpretable and Verifiable Hardware Generation with LLM-Driven Stepwise Refinement cites this paper.

Interpretable and Verifiable Hardware Generation with LLM-Driven Stepwise Refinement VeriReason: Reinforcement Learning with Testbench Feedback for Reasoning-Enhanced Verilog Generation

Reference 44

Resolution: verified exact; arxiv_id, observed 2026-07-03T21:28:59.388119Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation 9a616aba-dc5f-4eb0-9a63-aea34be02a94 · inbound

Interpretable and Verifiable Hardware Generation with LLM-Driven Stepwise Refinement cites this paper.

Interpretable and Verifiable Hardware Generation with LLM-Driven Stepwise Refinement VeriReason: Reinforcement Learning with Testbench Feedback for Reasoning-Enhanced Verilog Generation

Reference 44

Resolution: unresolved; no resolver link, observed 2026-07-15T10:45:43.149976Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation f619fb03-c0d3-4384-a6ff-b73966b20a55 · inbound

A Progressive Approach to Synthesizable RTL Design Generation Using LLMs cites this paper.

A Progressive Approach to Synthesizable RTL Design Generation Using LLMs VeriReason: Reinforcement Learning with Testbench Feedback for Reasoning-Enhanced Verilog Generation

Reference 28

Resolution: unresolved; no resolver link, observed 2026-08-01T15:14:11.677747Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation f35c7068-2d8f-4c39-8aeb-4495c290f31a · inbound

CircuitWeave: Topology-Behavior Alignment for Executable Multimodal RTL Generation cites this paper.

CircuitWeave: Topology-Behavior Alignment for Executable Multimodal RTL Generation VeriReason: Reinforcement Learning with Testbench Feedback for Reasoning-Enhanced Verilog Generation

Reference 19

Resolution: unresolved; no resolver link, observed 2026-07-30T20:17:57.553426Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.