Pith. sign in

REVIEW 3 major objections 5 minor 34 references

Defending against ColumnDisturb can be nearly free: CODA cuts the required adjacent-subarray counter increments by 12x-1300x, eliminating the 17% slowdown of straightforward protection.

Reviewed by Pith at T0; open to challenge. T0 means a machine referee read the full paper against a public rubric. the ladder, T0–T4 →

Challenge this review Re-run · record.json Download PDF Read on arXiv ↗

CODA reduces required adjacent-counter increments for inter-subarray ColumnDisturb protection by 12x–1300x, restoring SALT/Ganged-SALT and REGA to near-zero slowdown and power overhead.

T0 review reviewed 2026-08-02 challenge →

load-bearing objection CODA is a credible, well-scoped optimization for ColumnDisturb mitigation; the headline 'zero overhead' is secure only within the 8 ms attack model, and the paper has a handful of arithmetic slips that should be fixed, but it deserves peer review. the 3 major comments →

arxiv 2607.13505 v1 pith:OTHPSQK3 submitted 2026-07-15 cs.CR cs.AR

CODA: How to Mitigate ColumnDisturb for (Almost) Free?

Moinuddin Qureshi This is my paper
classification cs.CR cs.AR
keywords ColumnDisturbRowhammerRowPressdata-disturbance errorsadjacent-counter increment (ACI)subarray-level mitigationDRAM refresh overheadCODA
verification ladder T0 review T1 audit T2 compute T3 formal T4 reserved

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

The paper targets ColumnDisturb, a DRAM disturbance where activations to one row flip bits hundreds of rows away and in adjacent subarrays. It argues that the expensive part of protection is the adjacent-counter increment (ACI): every activation forces the two neighboring subarrays to advance their mitigation counters, tripling perceived bank activity and causing 17% slowdowns. CODA attacks this increment from three angles — skip it when the neighbor is active anyway, make it fractional based on ColumnDisturb's millisecond-scale timing, and skip it when the neighbor shares a gang counter. Combined, the paper reports ACI reduction of 12x-1300x, bringing slowdown back to the 0.3% baseline and eliminating the 3x refresh-power penalty of a straightforward extension. If correct, existing subarray-granularity Rowhammer defenses can be retrofitted to handle ColumnDisturb with nearly zero added cost.

Core claim

On the paper's own terms, the central discovery is that ColumnDisturb protection does not need a one-to-one mapping between demand activations and adjacent-subarray counter increments. Because ColumnDisturb requires repeated RowPress-like stress over milliseconds, the neighboring subarray only needs to refresh all its rows once per ColumnDisturb window; a fractional increment of 1/16 to 1/2 per activation suffices. Demand activations can override pending increments, and multi-subarray gangs make many increments redundant. CODA-EFG, the full combination, cuts required ACI from 200% of demand activations to as low as 0.15%, so SALT/Ganged-SALT with CODA matches the slowdown of the no-ColumnDis

What carries the argument

The central object is the Adjacent-Counter Increment (ACI) plus the auxiliary Pending-Activation Counter (PAC) that lets increments be deferred, overridden, or made fractional. On each activation to a subarray, CODA advances the PAC of the two neighboring subarrays by a fraction f (1/16 to 1/2, set by TRHD and the 8ms ColumnDisturb window); when PAC saturates, ACTR increments; a demand activation to the neighbor decrements or resets its PAC. This converts the naive 200% ACI rate into a tunable, much smaller rate. For CODA-G, the mechanism is address-based gang membership: if the adjacent subarray shares the gang's activation counter, the ACI is skipped entirely because the gang refresh alrea

Load-bearing premise

The scheme's fractional refresh rate assumes ColumnDisturb needs about 8 milliseconds of repeated row-open stress, with 500 nanoseconds of open time counting as one activation; if real chips flip bits after fewer equivalent activations or a shorter window, neighbors go unrefreshed too long.

What would settle it

Measure on real DRAM the minimum number of equivalent activations (or minimum repeated-open time) needed to cause inter-subarray ColumnDisturb bitflips. If a neighbor subarray can be flipped with fewer equivalent activations than the ACI schedule provides a full refresh (e.g., fewer than 16K equivalent activations in an 8ms window at f=1/16), CODA-F and CODA-EFG's fractional rates are unsafe; the same measurement at 4ms and 1ms windows would bound the required f.

Watch this falsifier. Get emailed when new claim-graph text bears on it.

If this is right

  • SALT and Ganged-SALT can tolerate both intra- and inter-subarray ColumnDisturb at the same 0.3% average slowdown as no-ColumnDisturb operation, across TRHD 500-4K.
  • REGA with CODA avoids the 3x refresh-power penalty of REGA-CDP; the refresh-power increase stays within about 1% of REGA alone.
  • Designs that skip refresh coordination still benefit: CODA-EF keeps slowdown within 0.5% of the no-ColumnDisturb baseline, versus 54% for CDP.
  • The CODA principles transfer to any subarray-granularity Rowhammer mitigation, not just SALT and REGA.
  • The 4x-refresh mitigation for 8ms ColumnDisturb and PRVR-style proactive refresh become unnecessary; CODA achieves 0% slowdown where an 8ms refresh incurs 22.3%.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • If real DRAM measurements show ColumnDisturb flips bits sooner than 8ms or with fewer equivalent activations than the 500ns-per-activation assumption, the fractional rates in CODA-F would need rescaling; the paper's 4ms and 1-2ms analyses substitute a 250ns equivalence, so final safety still rests on attack-parameter measurements.
  • A natural extension would be to sweep the ColumnDisturb duration continuously and plot the resulting ACI-rate/security trade-off; the current tables sample only a few hand-picked durations, leaving the shape of that curve implicit.
  • CODA-G's benefit grows with gang size, so combining it with larger ganged mitigations at higher TRHD is a plausible scaling path; the reported ACI rates already approach 0.15% at TRHD 2K-4K.
Share X Bluesky LinkedIn Reddit HN

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit.

Referee Report

3 major / 5 minor

Summary. The paper proposes CODA, a set of mechanisms to reduce the overhead of protecting DRAM against inter-subarray ColumnDisturb. In the SALT/Ganged-SALT framework, ColumnDisturb Protection (CDP) requires two Adjacent-Counter Increments (ACIs) per demand activation, tripling the perceived activation rate and causing large slowdowns. CODA-E skips ACI when the neighboring subarray receives a demand activation; CODA-F performs fractional ACI increments at a rate f determined by the ColumnDisturb duration and row-open-time-to-activation equivalence; CODA-G skips ACI for adjacent subarrays in the same gang. The paper claims a combined reduction in ACI rate of 12x-1300x, making ColumnDisturb protection possible at near-zero performance and power overhead, and evaluates the idea with SALT, Ganged-SALT, and REGA using the SALT artifact.

Significance. If the central claim holds, this is a practically important result: it would convert an expensive DDR5-era disturbance mitigation (3x activation rate, 17% slowdown at TRHD=500) into a nearly free one, while reusing existing subarray-granularity Rowhammer defenses. The paper is clearly written, the design variants are intuitive, and the evaluation is grounded in a publicly available simulator artifact from the SALT work. The mechanisms are simple enough to be deployable, and the storage overhead (4 bits per subarray for PAC) is modest. The strongest parts are the combination of three complementary ACI-reduction ideas and the demonstration that they also apply to REGA, giving power rather than performance benefits. However, the security guarantee rests on unvalidated external attack parameters, and the internal arithmetic for CODA-F's security impact is inconsistent, so the quantitative claim cannot currently be verified from the paper alone.

major comments (3)
  1. [§1 vs §5.1/Table 6] The derivation of the fractional ACI rate is internally inconsistent. Section 1 states that with an 8 ms window, 500 ns per activation, and a 1K-activation refresh cycle, 'it would be sufficient to issue one ACI every 32 demand activations.' Section 5.1 defines f=1/16 for TRHD=500, and Table 6 reports a CODA-F ACI rate of 12.5% (an ACTR increment for a given neighbor every 16 demand activations, or one total full ACI per 8 demand activations). The factor-of-two discrepancy is not cosmetic: if an implementer used 'one per 32', the neighbor subarray would receive half the intended ACTR increments and could be unrefreshed at the bitflip time. Please correct the example and define 'ACI rate' consistently (per-neighbor versus total).
  2. [§5.5, Table 7] The security-impact table is not derivable from the stated PAC design. The text says a 4-bit fixed-point PAC 'can count 15 fractional increments to reach the maximum value.' For f=1/16, that implies a pending lag of 15 fractional increments, i.e. 15/16 of a full activation, before an ACTR transfer; Table 7 instead lists PAC-Max = 1 for TRHD=500, and values 2, 4, 8 for other thresholds. These numbers do not follow from the described representation and appear to treat the PAC as integer-valued. Since Table 7 is the only quantitative support for the claim that CODA-F/CODA-EFG has a negligible (0.1%) impact on the tolerated threshold, the counter format and the PAC-Max computation must be clarified and recomputed.
  3. [§5, §6.7] The f values, and therefore the headline ACI reductions, are anchored to a single point in the attack-parameter space: an 8 ms ColumnDisturb duration and a 500 ns row-open-time-to-activation equivalence. The paper does not validate these constants against device measurements, and the sensitivity analysis in §6.7 substitutes a different equivalence (250 ns) for the 1-2 ms case rather than exploring the joint uncertainty. If the real disturbance threshold is reached with fewer equivalent activations, CODA-F and CODA-EFG will refresh neighboring subarrays too slowly and the security guarantee breaks. Please state the guarantee explicitly as a function of (attack duration, activation equivalence, TRHD) and, if possible, provide a sensitivity range that includes realistic uncertainty in the ColumnDisturb parameters.
minor comments (5)
  1. [Abstract/Conclusion] The abstract claims 'zero performance and power overhead,' while the conclusion and Section 6.5 report a slowdown of 0.3%, identical to Ganged-SALT without CDP. Please use 'negligible' or 'near-zero' consistently, or clarify the baseline definition.
  2. [§5.1] The fixed-point PAC format is underspecified. Please specify how many integer/fraction bits the 4-bit PAC has, how the maximum value is represented, and what 'reduce PAC by 1' means when PAC is fractional.
  3. [§6.7] The 250 ns activation equivalence for the 1-2 ms analysis is introduced without justification. Even if it is only a sensitivity parameter, state explicitly that it is an assumption and not derived from a measurement.
  4. [Table 1] SALT(CDP) shows 0% slowdown at TRHD=2K and 4K while Ganged-SALT(CDP) shows ~17%. A one-sentence explanation (e.g., refresh coordination absorbs 3x activity at high TRHD only with per-subarray counters) would prevent confusion.
  5. [Figures 6-7] The bars for CODA-F and CODA-EF are too small to be visible. Please add value labels or a zoomed inset.

Circularity Check

0 steps flagged

No significant circularity: CODA's ACI reductions are explicit design-parameter choices tied to an external attack model, not fitted retroactively to its claimed outcomes.

full rationale

The paper's CODA-F rates are derived from the ColumnDisturb duration (8 ms from [31]) and an activation-equivalence assumption (500 ns per activation from [19,22]); the text states 'the adjacent subarrays need to refresh all their rows only once over the 8ms period, so their counters need to be updated at a rate of only 1/16 per demand activation.' That is a constructive security parameter, not a fit to the slowdown numbers the paper reports. CODA-E's 2x bound follows from the PAC decrement rule, CODA-G's rate follows from gang size (2/N), and the combined rates in Tables 6 and 9 are produced by the same stated formulas plus workload simulation; no predicted quantity is used to set a parameter and then re-reported as validation. The main self-citations are to SALT [19] and the RowPress-equivalence work [22]; SALT is evaluated with its public artifact and the 500 ns equivalence is an externally falsifiable device-modeling input, so these are not load-bearing circularity. The paper's dependence on unvalidated attack parameters (8 ms duration, 500 ns/250 ns equivalence) is a threat-model correctness risk, not circularity, and is partially acknowledged in Section 6.7.

Axiom & Free-Parameter Ledger

3 free parameters · 4 axioms · 1 invented entities

The headline ACI reductions are largely set by the choice of f, which is the reciprocal of the assumed attack duration normalized by TRHD, so the paper's quantitative claims are conditional on external attack-parameter measurements. The zero-overhead conclusion also depends on the benign workload mix and on the correctness of SALT/REGA as baselines.

free parameters (3)
  • Fractional ACI increment f = 1/16 (TRHD=500), 1/8 (1K), 1/4 (2K), 1/2 (4K)
    Chosen so an adjacent subarray refreshes all rows once within the assumed 8 ms ColumnDisturb duration given the 500 ns row-open = 1 activation equivalence; directly determines the reported ACI reduction factors in Tables 6, 9, and 14.
  • PAC width = 4 bits (15 pending increments)
    User-selected counter width; bounds delayed ACI to 15 increments and sets the security slack shown in Tables 5 and 7. A different width would change the reported threshold increases and storage cost.
  • Row-open-time-to-activation equivalence = 500 ns per activation (250 ns for 1–2 ms sensitivity analysis)
    Hand-set conversion from row open duration to equivalent activations, borrowed from RowPress modeling [19,22]; load-bearing for CODA-F because f is computed from this value and the 8 ms attack window.
axioms (4)
  • domain assumption Inter-subarray ColumnDisturb affects only the adjacent subarrays.
    Used throughout (Section 2.4, Figure 1): ACI updates exactly two neighboring subarrays. If disturbance reaches non-adjacent subarrays, both CDP and CODA are insecure.
  • domain assumption ColumnDisturb requires repeated RowPress-like stress over about 8 ms, corresponding to 16K equivalent activations at the assumed rate.
    Section 5 derives f from this premise, citing [31]. The security-slack tables and reported ACI reductions are computed against this window; shorter real windows would require larger f.
  • domain assumption Subarray-granularity counters (SALT/REGA) refresh all rows in a subarray before 2*TRHD activations are accumulated.
    Inherited from SALT [19] and REGA [14]; CODA's mitigation guarantee relies on this baseline behavior plus the added ACI-driven increments.
  • domain assumption DRAM uses an open-bitline architecture with bitlines shared across adjacent subarrays.
    Section 2.2/2.4: this sharing is the physical basis for inter-subarray ColumnDisturb and for the existence of adjacent-subarray disturbance at all.
invented entities (1)
  • PAC (Pending-Activation Counter) no independent evidence
    purpose: A per-subarray/gang auxiliary counter that buffers ACI increments so that demand activations can override them (CODA-E) or fractional increments can accumulate before ACTR is updated (CODA-F).
    New hardware structure proposed by this paper; demonstrated only in simulation and arithmetic analysis, with no independent implementation, measurement, or formal verification.

reviewed 2026-08-02 · how reviews work

0 comments
Cite this review

Pith. "Pith review of CODA: How to Mitigate ColumnDisturb for (Almost) Free?." pith.science (2026). https://pith.science/paper/OTHPSQK3

@misc{pith2026260713505,
  author       = {Pith},
  title        = {Pith review of: CODA: How to Mitigate ColumnDisturb for (Almost) Free?},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/OTHPSQK3}},
  note         = {Machine review of arXiv:2607.13505}
}
Share X Bluesky LinkedIn Reddit HN
read the original abstract

ColumnDisturb is a new data-disturbance error in which activations to an aggressor row cause bitflips in a victim row located hundreds of rows away (intra-subarray bitflips) and in victim rows in adjacent subarrays (inter-subarray bitflips). Intra-subarray ColumnDisturb can be tolerated by solutions (such as SALT and REGA) that operate at subarray granularity. However, to tolerate inter-subarray ColumnDisturb, such solutions must be extended with ColumnDisturb Protection (CDP), which performs additional {\em Adjacent-Counter Increment (ACI)} for the neighboring subarrays. The ACIs ensure that adjacent subarrays also undergo mitigation, even if they receive no demand activations. Unfortunately, because ACIs occur at a 200\% rate relative to demand activations, they effectively increase the activations perceived by the bank to 3x, which causes significant slowdowns (17\% at a TRHD of 500) and refresh overheads. The goal of our paper is to tolerate ColumnDisturb while incurring negligible overheads. We propose CODA, a ColumnDisturb mitigation that significantly reduces the rate of ACI required to securely tolerate ColumnDisturb. We present three variants of CODA. First, CODA-E (Evade), which leverages the insight that ACI can be skipped if the neighboring subarray receives a demand activation, and reduces ACI by 2x. Second, CODA-F (Fraction), which uses the timing duration of ColumnDisturb to do only a fractional increment for ACI, thereby reducing the rate of ACI by 2x-16x. Finally, CODA-G (Gangskip), which operates at multi-subarray granularity and skips ACI for neighboring subarrays within the same gang, further reduces overall ACI by 2x-8x. Overall, CODA reduces ACI by 12x-1300x, thereby making it possible to tolerate ColumnDisturb while incurring zero performance and power overhead.

Figures

Figures reproduced from arXiv: 2607.13505 by Moinuddin Qureshi.

Figure 1
Figure 1. Figure 1: (a) ColumnDisturb leverages shared bitlines to cause distant bitflips, both inter-subarray and intra-subarray. (b) [PITH_FULL_IMAGE:figures/full_fig_p002_1.png] view at source ↗
Figure 2
Figure 2. Figure 2: DRAM Architecture. A bank consists of subarrays. [PITH_FULL_IMAGE:figures/full_fig_p003_2.png] view at source ↗
Figure 4
Figure 4. Figure 4: Overview of ColumnDisturb Protection (CDP). On [PITH_FULL_IMAGE:figures/full_fig_p004_4.png] view at source ↗
Figure 5
Figure 5. Figure 5: Overview of CODA-E. CODA-E adds a Pending [PITH_FULL_IMAGE:figures/full_fig_p005_5.png] view at source ↗
Figure 6
Figure 6. Figure 6: Slowdown of SALT, CDP, and CODA-E at TRHD=500 compared to unprotected baseline. The average (Geometric mean) [PITH_FULL_IMAGE:figures/full_fig_p006_6.png] view at source ↗
Figure 7
Figure 7. Figure 7: Slowdown of CDP, CODA-E, CODA-F, CODA-EF at TRHD=500. The average slowdown of CDP is 17.8%, of CODA-E is [PITH_FULL_IMAGE:figures/full_fig_p007_7.png] view at source ↗
Figure 8
Figure 8. Figure 8: Overview of CODA-F. CODA-F performs fractional [PITH_FULL_IMAGE:figures/full_fig_p007_8.png] view at source ↗
Figure 9
Figure 9. Figure 9: Overview of CODA-G. CODA-G exploits the multi [PITH_FULL_IMAGE:figures/full_fig_p008_9.png] view at source ↗
Figure 10
Figure 10. Figure 10: Overview of REGA. REGA uses an auxiliary row [PITH_FULL_IMAGE:figures/full_fig_p009_10.png] view at source ↗
Figure 12
Figure 12. Figure 12: Increase in refresh power with REGA, REGA-CDP, [PITH_FULL_IMAGE:figures/full_fig_p010_12.png] view at source ↗
Figure 13
Figure 13. Figure 13: Slowdown of Different ColumnDisturb Mitigations. [PITH_FULL_IMAGE:figures/full_fig_p011_13.png] view at source ↗

discussion (0)

Sign in with ORCID, Apple, or X to comment. Anyone can read and Pith papers without signing in.

Reference graph

Works this paper leans on

34 extracted references · 2 linked inside Pith

  1. [1]

    Oğuzhan Canpolat, A Giray Yağlıkçı, Geraldo F Oliveira, Ataberk Olgun, Nisa Bostancı, İsmail Emir Yüksel, Haocong Luo, Oğuz Ergin, and Onur Mutlu. 2025. Chronus: Understanding and Securing the Cutting-Edge Industry Solutions to DRAM Read Disturbance.HPCA(2025)

    2025

  2. [2]

    Fabrice Devaux and Renaud Ayrignac. 2021. Method and circuit for protecting a DRAM memory device from the row hammer effect. Filed 2020-08-04; Priority FR2006541 (2020-06-23)

    2021

  3. [3]

    Giray Yaglikci, Haocong Luo, Onur Mutlu, and ETH Zurich

    Hasan Hassan, Ataberk Olgun, A. Giray Yaglikci, Haocong Luo, Onur Mutlu, and ETH Zurich. 2024. Self-Managing DRAM: A Low-Cost Framework for Enabling Autonomous and Efficient DRAM Maintenance Operations . In2024 57th IEEE/ACM International Symposium on Microarchitecture (MICRO)

    2024

  4. [4]

    Patrick Jattke, Victor van der Veen, Pietro Frigo, Stijn Gunter, and Kaveh Razavi

  5. [5]

    JEDEC. 2024. JESD79-5C: DDR5 SDRAM Specifications. (2024)

    2024

  6. [6]

    Dimitris Kaseridis, Jeffrey Stuecheli, and Lizy Kurian John. 2011. Minimalist open-page: A DRAM page-mode scheduling policy for the many-core era. In Proceedings of the 44th Annual IEEE/ACM International Symposium on Microar- chitecture. 24–35

    2011

  7. [7]

    Jeremie S Kim, Minesh Patel, A Giray Yağlıkçı, Hasan Hassan, Roknoddin Azizi, Lois Orosa, and Onur Mutlu. 2020. Revisiting rowhammer: An experimental analysis of modern dram devices and mitigation techniques. InISCA. IEEE, 638–651

    2020

  8. [8]

    Yoongu Kim, Ross Daly, Jeremie Kim, Chris Fallin, Ji Hye Lee, Donghyuk Lee, Chris Wilkerson, Konrad Lai, and Onur Mutlu. 2014. Flipping bits in memory without accessing them: An experimental study of DRAM disturbance errors. ISCA(2014)

    2014

  9. [9]

    Yoongu Kim, Vivek Seshadri, Donghyuk Lee, Jamie Liu, and Onur Mutlu. 2012. A case for exploiting subarray-level parallelism (SALP) in DRAM. In2012 39th Annual International Symposium on Computer Architecture (ISCA)

    2012

  10. [10]

    Stuart P. Lloyd. 1982. Least squares quantization in PCM.IEEE Trans. Inf. Theory 28, 2 (1982), 129–136

    1982

  11. [11]

    Haocong Luo, Ataberk Olgun, Abdullah Giray Yağlıkçı, Yahya Can Tuğrul, Steve Rhyner, Meryem Banu Cavlak, Joël Lindegger, Mohammad Sadrosadati, and Onur Mutlu. 2023. RowPress: Amplifying Read Disturbance in Modern DRAM Chips. In Proceedings of the 50th Annual International Symposium on Computer Architecture (Orlando, FL, USA)(ISCA ’23). Association for Com...

    arXiv 2023

  12. [12]

    Yandong Mao, Eddie Kohler, and Robert Tappan Morris. 2012. Cache craftiness for fast multicore key-value storage. 183–196

    2012

  13. [13]

    Michele Marazzi, Patrick Jattke, Flavien Solt, and Kaveh Razavi. 2022. Protrr: Principled yet optimal in-dram target row refresh. InIEEE Symposium on Security and Privacy (SP). IEEE, 735–753

    2022

  14. [14]

    Michele Marazzi, Flavien Solt, Patrick Jattke, Kubo Takashi, and Kaveh Razavi

  15. [15]

    McCalpin

    John D. McCalpin. 1995. Memory Bandwidth and Machine Balance in Current High Performance Computers.IEEE (TCCA) Newsletter(1995)

    1995

  16. [16]

    Moinuddin Qureshi. 2025. AutoRFM: Scaling Low-Cost In-DRAM Trackers to Ultra-Low Rowhammer Thresholds . InHPCA

    2025

  17. [17]

    Moinuddin Qureshi and Salman Qazi. 2025. MOAT: Securely mitigating rowham- mer with per-row activation counters.ASPLOS-2025(2025)

    2025

  18. [18]

    Moinuddin Qureshi, Salman Qazi, and Aamer Jaleel. 2024. MINT: Securely Mitigating Rowhammer with a Minimalist In-DRAM Tracker. InMICRO. IEEE

    2024

  19. [19]

    Moinuddin K. Qureshi. 2026. SALT: Track-and-Mitigate Subarrays, Not Rows, for Blast-Radius-Free Rowhammer Defense . In2026 IEEE International Symposium on High Performance Computer Architecture (HPCA)

    2026

  20. [20]

    Asanovic S

    K. Asanovic S. Beamer and D. Patterson. 2015. The GAP benchmark suite. In arXiv preprint arXiv:1508.03619

    Pith/arXiv arXiv 2015

  21. [21]

    Gururaj Saileshwar, Bolin Wang, Moinuddin Qureshi, and Prashant J Nair. 2022. Randomized row-swap: mitigating Row Hammer by breaking spatial correlation between aggressor and victim rows. InProceedings of the 27th ACM International Conference on Architectural Support for Programming Languages and Operating Systems. 1056–1069

    2022

  22. [22]

    Anish Saxena, Aamer Jaleel, and Moinuddin Qureshi. 2024. Impress: Securing dram against data-disturbance errors via implicit row-press mitigation. In2024 57th IEEE/ACM International Symposium on Microarchitecture (MICRO). IEEE, 935–948

    2024

  23. [23]

    Anish Saxena, Saurav Mathur, and Moinuddin Qureshi. 2024. Rubix: Reducing the Overhead of Secure Rowhammer Mitigations via Randomized Line-to-Row Mapping(ASPLOS ’24)

    2024

  24. [24]

    Anish Saxena, Gururaj Saileshwar, Prashant J Nair, and Moinuddin Qureshi

  25. [25]

    Hritvik Taneja, Ali Hajiabadi, Michele Marazzi, Kaveh Razavi, and Moinuddin Qureshi. 2026. MIRZA: Efficiently Mitigating Rowhammer with Randomization and ALERT. InIEEE International Symposium on High Performance Computer Architecture (HPCA). IEEE

    2026

  26. [26]

    Minbok Wi, Jaehyun Park, Seoyoung Ko, Michael Jaemin Kim, Nam Sung Kim, Eojin Lee, and Jung Ho Ahn. 2023. SHADOW: Preventing Row Hammer in DRAM with Intra-Subarray Row Shuffling. In2023 IEEE International Symposium on High-Performance Computer Architecture (HPCA). IEEE, 333–346

    2023

  27. [27]

    In2022 55th IEEE/ACM International Symposium on Microarchitecture (MICRO)

    Aqua: Scalable rowhammer mitigation by quarantining aggressor rows at runtime. In2022 55th IEEE/ACM International Symposium on Microarchitecture (MICRO). IEEE, 108–123

  28. [28]

    Jeonghyun Woo, Gururaj Saileshwar, and Prashant J Nair. 2023. Scalable and Se- cure Row-Swap: Efficient and Safe Row Hammer Mitigation in Memory Systems. In2023 IEEE International Symposium on High-Performance Computer Architecture (HPCA). IEEE, 374–389

    2023

  29. [29]

    A Giray Yağlikçi, Minesh Patel, Jeremie S Kim, Roknoddin Azizi, Ataberk Ol- gun, Lois Orosa, Hasan Hassan, Jisung Park, Konstantinos Kanellopoulos, Taha Shahroodi, et al. 2021. BlockHammer: Preventing RowHammer at Low Cost by Blacklisting Rapidly-Accessed DRAM Rows. In2021 IEEE International Sympo- sium on High-Performance Computer Architecture (HPCA). IE...

    2021

  30. [30]

    Jeonghyun Woo, Chris S Lin, Prashant J Nair, Aamer Jaleel, and Gururaj Sailesh- war. 2025. Qprac: Towards secure and practical prac-based rowhammer mitiga- tion using priority queues.HPCA(2025)

    2025

  31. [31]

    Nisa Bostancı, Haocong Luo, A

    İsmail Emir Yüksel, Ataberk Olgun, F. Nisa Bostancı, Haocong Luo, A. Giray Yağlıkçı, and Onur Mutlu. 2025. ColumnDisturb: Understanding Column-based Read Disturbance in Real DRAM Chips and Implications for Future Systems. In IEEE/ACM International Symposium on Microarchitecture (MICRO). 12

    2025

  32. [33]

    Kim, Fabrice Devaux, and Onur Mutlu

    Abdullah Giray Yağlıkçı, Jeremie S. Kim, Fabrice Devaux, and Onur Mutlu. 2021. Security Analysis of the Silver Bullet Technique for RowHammer Prevention. arXiv:2106.07084 [cs.CR] https://arxiv.org/abs/2106.07084

    Pith/arXiv arXiv 2021

  33. [2022]

    In43rd IEEE Symposium on Security and Privacy’22 (Oakland)

    BLACKSMITH: Rowhammering in the Frequency Domain. In43rd IEEE Symposium on Security and Privacy’22 (Oakland). https://comsec.ethz.ch/wp- content/files/blacksmith_sp22.pdf

  34. [2023]

    InIEEE Symposium on Security and Privacy (SP)

    REGA: Scalable Rowhammer Mitigation with Refresh-Generating Activa- tions. InIEEE Symposium on Security and Privacy (SP). IEEE

This paper was first reviewed by deepseek-v4-flash on August 2, 2026.