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REVIEW 3 major objections 6 minor 42 references

Improved T counts and active volume estimates for high-level arithmetic subroutines

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Pith's one-line read Quantum arithmetic subroutines get lower T counts and exact active-volume formulas.

desk verdict Useful new adder constructions and a first active-volume catalogue, but the arcsine active-volume formula does not follow from the paper's own parts list; treat the high-level AV numbers as provisional until the derivations are fixed. read the letter →

arxiv 2504.19626 v1 pith:RF7WELIR submitted 2025-04-28 quant-ph

Sam Heavey This is my paper · ORCID
classification quant-ph
keywords activevolumearchitecturequantumarithmeticcircuitsTcountoptimizationorientatedZXdiagramsfault-tolerantcomputingmagicstatedistillationsurfacecodespacetimeblocksreactiondepth
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

This paper claims that standard quantum arithmetic operations—controlled addition/subtraction, addition with overflow, multiplication, squaring, square root, piecewise polynomial evaluation, arcsine, and logarithm—can be built with lower T counts than prior designs and that their cost on an active-volume fault-tolerant computer is captured by explicit closed-form formulas. The significance is practical: active-volume architectures charge only for logical blocks that do work, so a catalogue of subroutine block counts turns algorithm-level resource estimation into a sum of known terms. For a reader, the paper's claim is that both gate count and circuit geometry matter, and that orientated ZX diagrams provide a way to see and optimize that geometry.

What carries the argument

The load-bearing machinery is the orientated ZX diagram (OZX): a ZX-calculus diagram whose spiders may connect only through six direction ports, with each surviving spider corresponding to one surface-code spacetime logical block. The conversion pipeline runs circuit diagram to ZX diagram to compressed ZX diagram to OZX diagram, then counts spiders and adds magic-state distillation costs. The second load-bearing gadget is the temporary AND gate, which replaces Toffoli pairs in addition-type circuits and halves the T count; when its un-compute part commutes with everything in between, a compute/un-compute pair costs the same as one Toffoli and fits in one reaction-depth layer. Long uninterrupted strings of controls and targets merge into fewer Z spiders, which is the structural mechanism behind the block-count savings.

What would settle it

Take the alternative multiplier design cited as [32], convert it to an orientated ZX diagram, and count blocks at a fixed width such as $n=8$. If its active volume comes out below Eq. (5a) even though its T count is higher, then the Section 2 assumption is false and the paper's active-volume formulas are not the minimum for that function.

Watch

Extended reading notes

Core claim

The central discovery is a collection of arithmetic circuits whose active volume is known exactly on the active-volume architecture. For example, the controlled addition/subtraction (CAS) adder costs $(25+C_{|CCZ\rangle})n-20-C_{|CCZ\rangle}$ blocks, the controlled adder with output carry used for multiplication costs $(30+2C_{|CCZ\rangle})n+15+2C_{|CCZ\rangle}$, multiplication costs $(30+2C_{|CCZ\rangle})n^{2}+(C_{|CCZ\rangle}-3)n-15-2C_{|CCZ\rangle}$, and the square-root circuit costs $\frac{1}{4}(25+C_{|CCZ\rangle})n^{2}+(39+2C_{|CCZ\rangle})n-46-6C_{|CCZ\rangle}$, with $C_{|CCZ\rangle}\approx 35$ the distillation cost of a CCZ magic state. The same designs carry T-count reductions, for example $4n-4$ for controlled add/subtract and $n^{2}+10n+8$ for square root, and the method extends to piecewise polynomial evaluation, arcsine, and logarithm.

Load-bearing premise

The load-bearing assumption is stated in Section 2: a circuit with the lowest T count, fewest qubits, and smallest baseline circuit volume will also have the smallest active volume. If that correlation fails—if a slightly bigger circuit can be arranged in a way that produces far fewer orientated ZX spiders—the reported block counts are upper bounds, not minima.

Editorial extensions

If this is right

  • The subroutine costs can be summed modularly: any algorithm built from these pieces has active volume obtained by inserting Eqs. (3a), (5a), (8a), (16a), (19a), and (23a) into the total, enabling resource estimates without re-deriving block counts.
  • The T-count reductions transfer: controlled addition/subtraction at $4n-4$, an add-with-overflow adder at $4n$, multiplication at $8n^2+4n-8$, square root at $n^2+10n+8$, and a roughly six-fold drop in the leading T-count term for arcsine.
  • The $k$-controlled NOT built from $k-1$ temporary AND gates has T count $4k-4$, about a quarter of the $16(k-2)$ baseline, and the same construction feeds the NEXT operation in polynomial evaluation.
  • Shifts are free in the active-volume architecture: a fixed-point shift is just relabelling data-qubit modules, so shift costs disappear from resource estimates.
  • Circuit structure, not just gate counts, changes active volume: the appendix exhibits two equivalent three-qubit out-of-place additions with identical gate sets that cost 21 and 17 blocks.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • A consequence the paper leaves implicit: if the Section 2 assumption is relaxed, every formula here is best read as an upper bound rather than a proven minimum, and structural search over equivalent circuits could lower these block counts further.
  • The same temporary-AND $k$-controlled NOT construction could be dropped into other multiply-controlled contexts, such as table lookups or exponentiation, where the paper does not apply it, with a similar three-quarter T-count reduction.
  • The log cost formula omits the classical cost of determining the shift parameters $l$ and $v$; an end-to-end resource estimate would need either a reversible circuit that derives those parameters or an explicit classical pre-processing budget.
  • Because reaction depths are reported as upper bounds obtained by summing component depths, a layer scheduler for a fixed number of workspace modules could yield lower actual runtimes than the depth formulas suggest.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

3 major / 6 minor

Summary. The manuscript reports new low-level arithmetic circuits (a controlled addition/subtraction CAS adder, a controlled overflow COG adder, an output-carry OG adder, incrementers, controlled shifts, and a k-controlled NOT construction) and assembles them into high-level arithmetic subroutines (square root, piecewise polynomial evaluation, arcsine, and logarithm). For each subroutine it gives a T count, a reaction depth, and an active-volume block-count formula in the Litinski active-volume architecture, using orientated ZX diagrams and the stated assumption that the cheapest baseline circuit in T count and qubit count also gives the smallest active volume. The low-level circuits are reported to have been verified by Qiskit simulation, and a link to the simulation code is provided.

Significance. If the formulas were all correct, this would be a useful catalogue: it extends active-volume accounting to several practical arithmetic blocks and gives concrete, well-defined T-count reductions over earlier designs by Häner et al. and Muñoz-Coreas and Thapliyal. The Qiskit verification of the low-level circuits and the explicit per-block costing are strengths, and the k-controlled NOT construction is a simple and genuinely useful improvement. However, the active-volume numbers are only as reliable as the component algebra, and the arcsine formula fails an internal check; a second formula in the logarithm section also does not match its own component definitions. Because the paper advertises exact logical block counts, these derivability failures are central rather than cosmetic.

major comments (3)
  1. [§4.3, Eq. (19a)] The printed arcsine active-volume formula is not derivable from the parts list given in the same section. The parts list contains n+1 CNOTs in Part 1, n CNOTs for the pi/2 initialization in Part 4, and 2n+1 CNOTs in Part 6; at the paper's own cost of 4 blocks per CNOT these contribute 16n+8 blocks, and no term for them appears in Eq. (19a). In addition, Parts 2, 3, and 5 contain n+1 temporary-AND compute gates and n+1 temporary-AND uncompute gates, so their contribution should be (n+1)(9+C|CCZ>) + (n+1)(5) = (n+1)(14+C|CCZ>), not the (2n+1)(14+C|CCZ>) used in the equation. Expanding the left-hand side of Eq. (19a) with Eqs. (3a), (8a), (13a), (2a), and (1a) also does not reproduce the right-hand side of Eq. (19a). The discrepancy therefore cannot be attributed to a missing explanatory sentence; the formula as printed is internally inconsistent, and Section C's summary table inherits the same numbers.
  2. [§4.4, Eq. (22a)] The logarithm multiplication active volume is also not derivable from the stated component costs. Eq. (22a) defines V_log_mult = (alpha-1) V_COGA + n V_Toff and then gives the result as [(27+2C|CCZ>)alpha - 23 - 2C|CCZ>]n + (18+2C|CCZ>)alpha - 18 - 2C|CCZ>. However, substituting V_COGA = (30+2C|CCZ>)n + 15 + 2C|CCZ> from Appendix A.4 and V_Toff = 12 + C|CCZ> from Section 3.4 yields [(30+2C|CCZ>)alpha - 18 - C|CCZ>]n + (15+2C|CCZ>)(alpha-1). These expressions are not equal for general alpha, so Eq. (22a) is unsupported. Since Eq. (22a) feeds Eq. (23a), the log active-volume estimate is likewise not checkable from the manuscript as written.
  3. [§2] The claim that the reported active volumes are 'optimised' rests entirely on the stated assumption that the lowest-T-count, lowest-qubit baseline circuit also has the smallest active volume. The paper explicitly identifies this as an assumption and does not test it; it never computes the active volume of a competing baseline design. The paper's own Fig. 10 shows that circuit structure beyond gate counts changes active volume, so the assumption is not a trivial consequence of gate-count minimization. The abstract and conclusion should therefore distinguish the T-count reductions, which are established by construction, from the active-volume estimates, which are resource estimates for the specific circuits presented rather than proven optima. Alternatively, the assumption should be tested on at least one subroutine for which a genuinely different baseline design is available.
minor comments (6)
  1. [§3.2] The parenthetical '(20-C|CCZ>)' in the text should presumably read '(20+C|CCZ>)', since the following formula uses a sum rather than a difference; the sign error is confusing in a cost calculation.
  2. [§4.2 and Section C] The notation C|CZZ> appears in Eqs. (14a), (15a), and the summary tables, while the rest of the paper uses C|CCZ>; please make the notation uniform.
  3. [Throughout] There are several typographical and name errors, including 'Muñoz-Coraes' for 'Muñoz-Coreas' in Section 4.1, 'appdendix' in the caption of Fig. 8, and 'Häner’s' inconsistently spelled; a careful proofreading pass is needed.
  4. [§5, Limitations] The final section honestly states that memory requirements and effective reaction depth are ignored, but the abstract and conclusion still describe the results in terms that readers may read as runtime improvements. The caveat that all comparisons are block-count/resource estimates under a fixed reaction-depth model should be stated wherever the AV reductions are summarized.
  5. [§3.3] The sentence 'This is an approximately 8% reduction in active volume' should state which baseline is being used for the percentage; the naïve block cost is given immediately before, but the comparison should be explicit.
  6. [§3.4.1] The baseline comparison against Li et al. [32] reports no active volume for the competitor and explains why; this is a fair limitation, but the table and text should make clear that the claimed advantage is in T count and reaction depth, not in demonstrated active volume.

Circularity Check

0 steps flagged · score 0.0 of 10

No circularity: the active-volume formulas are direct block-cost sums over the new circuits using Litinski's externally defined model, not fitted quantities or self-citing derivations.

full rationale

The paper's central deliverables are count formulas: it takes circuit constructions (CAS/COG/OG adders, k-controlled NOT, arcsine/log decompositions), converts them to orientated ZX diagrams, and sums per-block costs (CNOT=4, Toffoli=12+C|CCZ>, temporary-AND compute=9+C|CCZ>, uncompute=5, CCZ-distillation cost C|CCZ>) taken from Litinski's active-volume papers [7,12]. None of these costs is fitted to the paper's own outputs, and no prediction is made from a parameter that was calibrated on the target quantity. The Section 2 statement that lowest-T-count/qubit circuits will also have lowest active volume is explicitly labeled an assumption and is a heuristic for which circuits to convert; it is not used to define the AV formulas and therefore is not a circular definition. Comparison tables use independently published baseline counts [19,20,21,32] with stated conversion rules (Toffoli-to-T ratio 1:4). The paper discloses its own limitations (memory, effective reaction depth) in Section 4.4.1. Any apparent arithmetic mismatch in the assembled formulas (e.g., around Eq. 19a) would be a derivability/checking issue, not circularity, since the formulas are not equivalent to their inputs by construction.

Assumptions & free parameters 0 free parameters · 5 assumptions · 0 invented entities

No numbers are fitted to data in this paper; costs are sums of block constants imported from prior literature. The only free choices are algorithm parameters (n, q, M, p, etc.) that are part of the input problem size. The paper introduces no new physical entities. The load-bearing assumptions are the untested baseline-to-AV optimality heuristic and the imported OZX block costs.

assumptions (5)
  • domain assumption The OZX to logical block correspondence and the block costs from Litinski (CNOT = 4, Toffoli = 12 + C|CCZ>, temporary AND compute = 9 + C|CCZ>, etc.) are correct.
    Invoked in Section 2.1 and Fig. 2; every active volume formula in the paper inherits these unit costs from [7].
  • ad hoc to paper The circuit with the lowest baseline T count and qubit count also has the lowest active volume.
    Stated in Section 2: 'we make the following assumption...'; used to convert only the cheapest baseline implementation instead of comparing AV across designs.
  • domain assumption The CNOT counts of competing adder designs are similar, so Clifford gate contributions to active volume can be ignored when selecting designs.
    Section 2: 'each has a similar number of CNOT gates...'; justifies optimizing T count only.
  • domain assumption Reaction depth is upper bounded by the sum of component reaction depths when the number of workspace modules is unknown.
    Section 2.2; all reported reaction depths are these upper bounds, and the paper acknowledges they are not true depths.
  • domain assumption Each Toffoli or temporary AND gate costs exactly 4 T gates and CCZ magic state distillation costs about 35 blocks.
    Taken from Jones [28] and Litinski [7]; used to convert all T counts and to add C|CCZ> to block costs.

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Pith. "Pith review of Improved T counts and active volume estimates for high-level arithmetic subroutines." pith.science (2026). https://pith.science/paper/RF7WELIR

@misc{pith2026250419626,
  author       = {Pith},
  title        = {Pith review of: Improved T counts and active volume estimates for high-level arithmetic subroutines},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/RF7WELIR}},
  note         = {Machine review of arXiv:2504.19626}
}
read the original abstract

Surface code based quantum computers show great promise for fault-tolerant quantum computing, but most architectures needlessly increase the spacetime volume of a computation due to qubits sitting idly during a computation. Active volume architectures, with long-range connectivity, aim to remove idle spacetime volume leaving only the spacetime volume that logically contributes to a computation. In this work we optimise and derive the active volumes for several industry-leading low- and high-level arithmetic subroutines and achieve significant T-count reductions. We discuss a simple method for estimating and optimising active volumes using orientated ZX diagrams. We also demonstrate that circuit structure, beyond gate counts alone, impacts the active volume of a subroutine and therefore should be taken into consideration when designing circuits.

Figures

Figures reproduced from arXiv: 2504.19626 by the authors.

Figure 1
Figure 1. (a) The locations of each port on a orien [PITH_FULL_IMAGE:figures/full_fig_p003_1.png] view at source ↗
Figure 2
Figure 2. (a) Basic identities between circuit notation and ZX calculus. From top to bottom we have, a measurement [PITH_FULL_IMAGE:figures/full_fig_p005_2.png] view at source ↗
Figure 3
Figure 3. Here we display an example of the increment circuit on a [PITH_FULL_IMAGE:figures/full_fig_p007_3.png] view at source ↗
Figures from the paper (15 more)
Figure 4
Figure 4. Figure 4: A controlled shift-by-one circuit. The red and [PITH_FULL_IMAGE:figures/full_fig_p007_4.png]
Figure 5
Figure 5. Figure 5: The circuit design of our controlled addition or subtraction (CAS) adder [PITH_FULL_IMAGE:figures/full_fig_p009_5.png]
Figure 6
Figure 6. Figure 6: The left shows the design of a controlled addition repeating segment from [ [PITH_FULL_IMAGE:figures/full_fig_p009_6.png]
Figure 7
Figure 7. Figure 7: (P1) Circuit for the first part of the square root operation; the green box has a block cost of [PITH_FULL_IMAGE:figures/full_fig_p011_7.png]
Figure 8
Figure 8. Figure 8: The circuit for our Gidney-styler adder with [PITH_FULL_IMAGE:figures/full_fig_p012_8.png]
Figure 9
Figure 9. Figure 9: A circuit which implements a k-controlled NOT gate using k − 1 temporary AND gates. It has an active volume of (k − 1)(12 + C|CCZ⟩) + 3, T count 4k −4, reaction depth k −1, and requires k −1 ancillary qubits. cost of the polynomial evaluation circuit is: Vpoly = q · Vf…
Figure 10
Figure 10. Figure 10: Two designs for the controlled out-of-place addition of three qubits (compute) with no overflow. [PITH_FULL_IMAGE:figures/full_fig_p023_10.png]
Figure 11
Figure 11. Figure 11: (a) The circuit diagram of our increment subroutine. The start and end segments are defined by the [PITH_FULL_IMAGE:figures/full_fig_p024_11.png]
Figure 12
Figure 12. Figure 12: (a) We divide the controlled addition or subtraction (CAS) adder into four different segments, the blue [PITH_FULL_IMAGE:figures/full_fig_p028_12.png]
Figure 13
Figure 13. Figure 13: The circuit design for a cheaper CAS adder that performs [PITH_FULL_IMAGE:figures/full_fig_p029_13.png]
Figure 14
Figure 14. Figure 14: (a) The ZX diagram for the controlled output carry Gidney (COG) adder’s end segment. (b) As the [PITH_FULL_IMAGE:figures/full_fig_p030_14.png]
Figure 15
Figure 15. Figure 15: (a) The active volume calculation for the green box in part 1 of the square root circuit shows a cost of [PITH_FULL_IMAGE:figures/full_fig_p031_15.png]
Figure 16
Figure 16. Figure 16: The optimal Z spider configuration for a controlled shift’s control qubit. For an [PITH_FULL_IMAGE:figures/full_fig_p031_16.png]
Figure 17
Figure 17. Figure 17: The T count and number of ancillary qubits for all of the subroutines mentioned in this paper. [PITH_FULL_IMAGE:figures/full_fig_p032_17.png]
Figure 18
Figure 18. Figure 18: The active volumes and reaction depths of all subroutines mentioned in this paper. [PITH_FULL_IMAGE:figures/full_fig_p033_18.png]

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Pith tools

Reviewed August 16, 2026 · model on record in the stance chip above.