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A fixed pixel budget lets a sparse CNN run at 0.665 microseconds on an FPGA, 73x faster than a dense CNN of the same architecture.

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2026-08-03 18:12 UTC pith:RHZDLLQB

load-bearing objection Genuine FPGA sparse-convolution contribution with constant-latency kernel, but the speed-accuracy claim rests on untested row-major truncation. the 3 major comments →

arxiv 2512.06208 v3 pith:RHZDLLQB submitted 2025-12-05 cs.AR cs.LGhep-ex

SparsePixels: Efficient Convolution for Sparse Data on FPGAs

Ho Fung Tsoi , Dylan Rankin , Vladimir Loncar , Philip Harris This is my paper
classification cs.AR cs.LGhep-ex
keywords sparse convolutionFPGAlow-latency inferencesparsity-preserving convolutionactive pixel budgetLArTPC neutrino classificationjet taggingCNN acceleration
verification ladder T0 review T1 audit T2 compute T3 formal T4 reserved

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

SparsePixels claims that for images where most pixels carry no information, a convolutional network can be restructured so that only a small fixed number of active pixels are ever computed. The key idea is a sparsity-preserving convolution: an output pixel is computed only if the same spatial location was active at the input, so the set of active pixels stays fixed and no dilation occurs. Because the number of retained pixels is capped at a hardware budget, inference latency is constant and known at compile time, independent of how sparse a given input is. On LArTPC neutrino images with about 4000 pixels, retaining at most 20 active pixels yields a 73x speedup over a standard CNN (0.665 microseconds vs 48.665 microseconds) with less than a 2% drop in ROC AUC; similar order-of-magnitude speedups appear for handwritten digits and jet tagging.

Core claim

The central claim is that sparse convolution can be made hardware-friendly by fixing the active-pixel budget. The framework extracts up to N_max active pixels from the input using a recursive binary reduction that avoids data-dependent write addresses, stores them in compact feature and coordinate arrays, and then performs all convolution, activation, pooling, and flattening on those arrays only. Because the convolution preserves the active set, the coordinate array never changes; only the features update. The result is FPGA inference whose latency is set by the fixed budget rather than the input size, demonstrated at 133 clock cycles (0.665 microseconds) for a 20-active-pixel model on LArTP

What carries the argument

The load-bearing mechanism is the sparsity-preserving convolution combined with a fixed active-pixel budget N_max. An output pixel is active if and only if the input at the same location is active, so the active set never dilates. Active pixels are gathered by a recursive binary reduction tree into two compact arrays—features and (height,width) coordinates—and convolution becomes nested loops over active pixels with offset checks into a KxK weight window, so the iteration count does not scale with kernel size. This turns a data-dependent push-back readout into fixed-shape hardware and makes latency constant and pre-schedulable.

Load-bearing premise

The whole result rests on the assumption that thresholding the input and keeping the first N_max row-major active pixels preserves the information needed for the task, and that a convolution which never lets computation spread to inactive pixels can still transport that information through the network.

What would settle it

Run the same framework on a sparse-image task where the pixels that determine the label are deliberately placed after the first N_max positions in row-major order; if accuracy drops sharply while the dense baseline stays high, the row-major truncation is the culprit. Alternatively, scan N_max upward and find a task where accuracy never approaches the dense baseline, indicating the sparsity-preserving convolution cannot propagate the needed context.

Watch this falsifier — get emailed when new claim-graph text bears on it.

If this is right

  • Microsecond-level inference becomes possible for sparse detector images, making CNN-based triggers feasible where dense CNNs are too slow.
  • Latency is independent of input sparsity, so worst-case timing is guaranteed at design time, which matters for real-time systems.
  • Larger kernels no longer increase the convolution iteration count, so long-range context can be added without extra loop iterations.
  • The accuracy/cost trade-off is controlled by one hyperparameter, N_max, and can be tuned per dataset.
  • The same framework is demonstrated on three sparse-image tasks (digits, neutrino detection, jet tagging), supporting its use on other spatially sparse imagery.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • The row-major truncation implicit in the readout means the method works best when informative pixels appear early in scan order; a task whose discriminative pixels consistently appear late would need a different selection rule.
  • If accuracy degrades gracefully with N_max, the same budget could be exposed as a compile-time knob for trading resources and latency, possibly enabling streaming implementations for larger budgets.
  • One could test the limits of the sparsity-preserving assumption by applying the method to images with moderate activity (e.g., 10-30%), where the fixed budget may drop too much information.
  • The constant-latency property also suggests a natural extension to trigger systems that require a strict worst-case decision time, since the design can be scheduled before deployment.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit.

Referee Report

3 major / 4 minor

Summary. The paper presents SparsePixels, an FPGA framework for sparse 2D convolution. The key idea is to retain at most N_max_active pixels from a large, spatially sparse input using a fixed, row-major reduction tree, then perform all subsequent convolution, activation, pooling, and flattening operations on compact sparse arrays with a fixed active set. This makes inference latency independent of input sparsity and bounded by the pixel budget. The authors implement the sparse layers in HLS, provide a Python library for quantization-aware training, and release the code. They compare sparse CNNs against standard hls4ml stream-I/O CNNs on MNIST, MicroBooNE neutrino images, and LHC jet tagging, reporting large speedups on an Alveo FPGA. For MicroBooNE, the sparse-large model achieves 133 cycles (0.665 us) versus 9733 cycles (48.665 us) for the standard CNN, a factor-73 speedup, with ROC AUC 0.927 versus 0.943. The central claim is that this speed-accuracy trade-off is practically useful for low-latency scientific data readout.

Significance. If the reported accuracy results are robust, this is a useful and timely contribution. The paper provides detailed pseudocode for all sparse layers, a public code release, careful latency and resource scaling studies, and concrete FPGA measurements on realistic high-energy physics datasets. The constant-latency property enforced by N_max_active is an important practical feature for trigger systems with hard latency bounds. The sparse-convolution formulation is well grounded in prior submanifold sparse convolution work, and the FPGA implementation is nontrivial. However, the significance is currently conditional: the headline "<2% AUC drop" is established for a single crop/vertex distribution and a single baseline, and the row-major active-pixel truncation is not tested for spatial-order sensitivity. If the requested robustness experiments are added and the accuracy differences are confirmed with uncertainty quantification, the paper would be a strong systems contribution.

major comments (3)
  1. [Secs. 3.2.1 and 4.2.1, Algorithm 1, Fig. 10] The row-major truncation of active pixels is load-bearing for the main accuracy claim but is not tested for robustness to input translation or alternative selection order. Algorithm 1 retains the first N_max_active active pixels in row-major order, and for MicroBooNE sparse-large this is only 20 of 3969 pixels. The paper itself shows in Fig. 10 that row-major truncation can change a digit 9 into a 0 at small N_max_active. Since the motivating LArTPC application must handle neutrino interactions occurring anywhere in the detector, the reported 0.927 versus 0.943 AUC in Table 1 may depend on the particular crop/vertex placement in the signal windows. I request an ablation that translates or re-crops MicroBooNE signal windows and/or uses a different active-pixel ordering (e.g., sorted by intensity, top-k by feature value) and reports AUC versus N_max_active for each condition. Without this,
  2. [Sec. 4.2.2 and Table 1] All accuracy/AUC values are single-run point estimates without repeated-seed variance. The differences being cited, such as MicroBooNE 8-bit sparse-large AUC 0.927 versus standard 0.943, are small enough that seed-induced variability could change the conclusion. Additionally, N_max_active is selected from a scan, and the reported numbers are the favorable operating points; while this is a standard hyperparameter choice, the selection should be based on validation and the test-set result should be reported with mean and standard deviation over multiple training runs. Please add this information, at least for the three datasets in Table 1.
  3. [Sec. 4.2.2] The standard and sparse CNNs are synthesized with different HLS toolchains: standard CNNs with Vivado HLS 2020.1 and sparse CNNs with Vitis HLS 2023.1. Since the headline speedup is a ratio of latencies measured from these two toolchains, the comparison would be cleaner if both designs were synthesized with the same tool version (or if the authors justify that the difference is immaterial for the stream-I/O versus parallel-I/O contrast). At minimum, the paper should state whether this choice was driven by hls4ml stability and whether any cross-tool latency differences were observed for the same design.
minor comments (4)
  1. [Sec. 4.2.1] Typos: 'boarders' should be 'borders' in the MNIST and jet preprocessing descriptions; 'gloun' should be 'gluon' in the jet tagging dataset description.
  2. [Table 1 and figure captions] 'Latancy' is misspelled 'Latency' in the Table 1 caption and in Figs. 16, 17, 21, and 22. Also, 'Fig. 17 Fig. 22' in Sec. 4.2.3 should be 'Fig. 17 and Fig. 22'.
  3. [Algorithm 2, line 21] The condition 'if pixel p_out is padded' is not defined in the algorithm or in the surrounding text. Since the convolution uses 'same' padding and the active set is fixed, it should be clarified what 'padded' means for a sparse output pixel and how the HLS implementation detects it.
  4. [Sec. 4.2.1, MicroBooNE preprocessing] Please state explicitly whether the 256x512 signal windows are centered or aligned on the neutrino vertex or are cropped at fixed coordinates. This detail is important for interpreting the row-major truncation behavior in the accuracy results.

Circularity Check

0 steps flagged

No significant circularity: N_max_active is an openly scanned hyperparameter; speedups and accuracy are direct benchmarks on public data.

full rationale

The paper's central claimed result—a x73 FPGA speedup with <2% AUC drop on MicroBooNE—is not a prediction obtained from fitted parameters. SparsePixels' core sparsity-preserving convolution is defined in Sec. 3.1 and explicitly attributed to external prior work [32] (Graham et al.), not to a self-cited uniqueness theorem or ansatz. N_max_active is explicitly called a hyperparameter in Sec. 3.2.1, and Sec. 4.2.1 says an N_max_active scan is necessary to balance accuracy and hardware cost; Table 1 reports measured results for the scanned values {8,12,16,20}, so accuracy is not a fitted quantity renamed as a prediction. The constant-runtime property is a design guarantee following from fixed sparse-array sizes, not an empirical discovery derived from data. The hls4ml baseline is measured with released code, and the paper's self-citations (e.g., hls4ml, FastML team) support tooling and related work rather than bearing the load of the trade-off claim. The acknowledged limitation that row-major truncation can discard discriminative pixels (Sec. 4.2.1, Fig. 10) is a correctness/robustness concern about order dependence, not a circular step: no equation in the paper reduces to its own input by construction. Overall, the derivation chain is self-contained as an engineering benchmark.

Axiom & Free-Parameter Ledger

4 free parameters · 4 axioms · 0 invented entities

The central contribution is an HLS engineering framework: the main free parameter is the fixed active-pixel budget N_max_active, plus dataset-specific thresholds and preprocessing. The key unproved assumptions are that thresholded/top-N_max pixels are information-sufficient and that sparsity-preserving convolution retains enough expressiveness; both are empirically checked only on three processed datasets. No new physical entities are introduced.

free parameters (4)
  • N_max_active = 8, 12, 16, 20 (per dataset/model)
    User-set upper bound on number of active pixels retained; sets array sizes, latency, and parallelism. Chosen by scanning values to trade accuracy vs hardware cost (Sec. 3.2.1, Sec. 4.2.2).
  • Active-pixel threshold(s) = MNIST 0.4; MicroBooNE 700 (denoised); LHC jet 0.003 after normalization
    Defines which pixels count as active and are passed to sparse layers; hand-set per dataset during preprocessing (Sec. 4.2.1).
  • Input preprocessing / image shaping = MNIST 48x48 after pool-3 and inflation; MicroBooNE 63x63 by summing 256x512 windows; jet crop to 56x56 with radial infla
    Data-specific resizing, masking, and inflation steps create the sparse images the experiments measure; results apply to these processed representations rather than raw detector images (Sec. 4.2.1).
  • Total bit-width (quantization) = 8 or 16 bits
    Fixed-precision choice; separately trained/evaluated; affects DSP usage and accuracy (Sec. 4.2.2).
axioms (4)
  • domain assumption Thresholded active pixels carry the discriminative information; inactive pixels can be discarded without material accuracy loss.
    Central to sparse input reduction and the claim that computing on <=1% of pixels preserves performance; validated empirically only on the three processed datasets (Sec. 3.1, Sec. 4.2.1).
  • domain assumption Submanifold sparsity preservation -- an output pixel is active iff the corresponding input pixel is active -- is expressive enough for classification after stacking layers/kernels.
    Adopted from [32] and built into Alg. 2; limits information flow to active locations, so accuracy parity depends on this constraint (Sec. 3.1, Sec. 4.2.3).
  • domain assumption Row-major top-N_max truncation of active pixels is an acceptable information-loss mechanism for sparse images.
    When more than N_max pixels are active, selection keeps the leftmost ones; Fig. 10 shows this can discard semantic content, so the N_max scan is required (Sec. 4.2.1).
  • domain assumption HLS synthesis (Vitis/Vivado) correctly models FPGA latency and resource usage at 200 MHz; logic-synthesis numbers for full models are reliable.
    All latency/resource claims rely on tool reports rather than on-board measurements (Sec. 4.1, Sec. 4.2.2).

pith-pipeline@v1.3.0-alltime-deepseek · 20664 in / 18024 out tokens · 174178 ms · 2026-08-03T18:12:21.094338+00:00 · methodology

0 comments
read the original abstract

Inference of standard convolutional neural networks (CNNs) on FPGAs often incurs high latency and a long initiation interval due to the deep nested loops required to densely convolve every input pixel regardless of its feature value. However, input features can be spatially sparse in some image data, where semantic information may occupy only a small fraction of the pixels and most computation would be wasted on empty regions. In this work, we introduce SparsePixels, a framework that implements sparse convolution on FPGAs by selectively retaining and computing on a small subset of active pixels while ignoring the rest. Because computation always runs over a single pre-specified pixel budget, the inference latency is independent of the input sparsity and is constant at runtime. We show that, for identifying neutrino interactions in naturally sparse LArTPC images with 4k pixels, a standard CNN with a compact size of 4k parameters incurs an inference latency of 48.665 $\mu$s on an FPGA, whereas a sparse CNN of the same base architecture, computing on less than 1% of the input pixels, achieves a $\times 73$ speedup to 0.665 $\mu$s with resource utilization well within on-chip budgets, trading only a small percent-level performance loss. This work aims to benefit future algorithm development for efficient data readout in modern experiments with latency requirements of microseconds or below.

Figures

Figures reproduced from arXiv: 2512.06208 by Dylan Rankin, Ho Fung Tsoi, Philip Harris, Vladimir Loncar.

Figure 1
Figure 1. Figure 1: Dilation of active pixels under standard convolution versus sparsity-preserving convolution, where the active set is fixed. [PITH_FULL_IMAGE:figures/full_fig_p005_1.png] view at source ↗
Figure 2
Figure 2. Figure 2: Schematic diagram of SparsePixels. The framework consists of five main layers sufficient to build sparse CNNs that selectively compute on active pixels only. Sparse arrays are produced and consumed within the HLS implementation. The sparse input reduction layer dynamically retains up to 𝑁 max active (a hyperparameter) active pixels into two sparse arrays: the feature array 𝑎feat (features) and the hash arr… view at source ↗
Figure 3
Figure 3. Figure 3: Identification of active pixels through thresholding. Only active pixels are stored in the sparse arrays: [PITH_FULL_IMAGE:figures/full_fig_p006_3.png] view at source ↗
Figure 4
Figure 4. Figure 4: Schematic diagram of the recursive tree splitting and pairwise combiner used in the sparse input reduction layer. [PITH_FULL_IMAGE:figures/full_fig_p007_4.png] view at source ↗
Figure 5
Figure 5. Figure 5: Schematic diagram of sparse convolution implemented in HLS. Active pixel locations are unchanged. Only the feature array is [PITH_FULL_IMAGE:figures/full_fig_p007_5.png] view at source ↗
Figure 6
Figure 6. Figure 6: Scaling of the sparse input reduction layer for different input sizes and [PITH_FULL_IMAGE:figures/full_fig_p011_6.png] view at source ↗
Figure 7
Figure 7. Figure 7: Latency scaling of the sparse convolutional layer for varying channels and [PITH_FULL_IMAGE:figures/full_fig_p011_7.png] view at source ↗
Figure 8
Figure 8. Figure 8: Resource scaling of the sparse convolutional layer for varying channels and [PITH_FULL_IMAGE:figures/full_fig_p012_8.png] view at source ↗
Figure 9
Figure 9. Figure 9: Example MNIST image before (left) and after (right) preprocessing. [PITH_FULL_IMAGE:figures/full_fig_p013_9.png] view at source ↗
Figure 10
Figure 10. Figure 10: Effect of 𝑁 max active on retained semantics. From left to right: 𝑁 max active = 4, 8, 12, 16. spatial sparsity of a given dataset. In [PITH_FULL_IMAGE:figures/full_fig_p013_10.png] view at source ↗
Figure 11
Figure 11. Figure 11: Example MicroBooNE neutrino image. Top: original view with signal (red) and background (orange) windows indicated. [PITH_FULL_IMAGE:figures/full_fig_p014_11.png] view at source ↗
Figure 12
Figure 12. Figure 12: Example jet images for classes g, q, W, Z, and t (left to right). Top: original [PITH_FULL_IMAGE:figures/full_fig_p015_12.png] view at source ↗
Figure 13
Figure 13. Figure 13: Base architectures for constructing both standard and sparse CNNs for the MNIST (top), neutrino (middle), and jet tagging [PITH_FULL_IMAGE:figures/full_fig_p015_13.png] view at source ↗
Figure 14
Figure 14. Figure 14: Illustration of sparse convolution on an example neutrino image from the MicroBooNE dataset. Top: single-channel input. [PITH_FULL_IMAGE:figures/full_fig_p016_14.png] view at source ↗
Figure 15
Figure 15. Figure 15: Model performance comparing the standard CNNs and the sparse CNNs for MNIST (upper left), neutrino (upper right), and [PITH_FULL_IMAGE:figures/full_fig_p017_15.png] view at source ↗
Figure 16
Figure 16. Figure 16: Synthesis results of standard (purple) and sparse (red) CNNs at 8-bit for MNIST (top), neutrino (middle), and jet tagging [PITH_FULL_IMAGE:figures/full_fig_p019_16.png] view at source ↗
Figure 17
Figure 17. Figure 17: Per-layer resource breakdown for 8-bit sparse CNNs on MNIST (top), neutrino (middle), and jet tagging (bottom). Latancy is [PITH_FULL_IMAGE:figures/full_fig_p019_17.png] view at source ↗
Figure 18
Figure 18. Figure 18: Scalings of the sparse activation layer on an FPGA for different [PITH_FULL_IMAGE:figures/full_fig_p023_18.png] view at source ↗
Figure 19
Figure 19. Figure 19: Scalings of the sparse pooling layer on an FPGA for different number of channels and [PITH_FULL_IMAGE:figures/full_fig_p024_19.png] view at source ↗
Figure 20
Figure 20. Figure 20: Scalings of the sparse flattening layer on an FPGA for different flat output array size and [PITH_FULL_IMAGE:figures/full_fig_p025_20.png] view at source ↗
Figure 21
Figure 21. Figure 21: Synthesis results of standard (purple) and sparse (red) CNNs at 16-bit for MNIST (top), neutrino (middle), and jet tagging [PITH_FULL_IMAGE:figures/full_fig_p026_21.png] view at source ↗
Figure 22
Figure 22. Figure 22: Per-layer resource breakdown for 16-bit sparse CNNs on MNIST (top), neutrino (middle), and jet tagging (bottom). Latancy is [PITH_FULL_IMAGE:figures/full_fig_p026_22.png] view at source ↗

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