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REVIEW 2 major objections 5 minor 32 references

A superconducting soliton DAC converts a digital pulse into held flux and runs 5.6 ns S-gates on transmons while filtering control noise.

Reviewed by Pith at T0; open to challenge. T0 means a machine referee read the full paper against a public rubric. the ladder, T0–T4 →

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T0 review · grok-4.5

2026-07-11 09:14 UTC pith:S6XNS6OR

load-bearing objection Solid first demo of a soliton-hold DAC doing 5.6 ns transmon S-gates with real noise filtration; the 1.6% multi-DAC EMI is measured honestly but remains the unmodeled scaling risk. the 2 major comments →

arxiv 2607.05072 v1 pith:S6XNS6OR submitted 2026-07-06 quant-ph

Transmon Phase Gates Controlled by Superconducting Soliton DAC

Derek Reitz , Tony X. Zhou , Aditya Sharma , Ryan Bilotta , John McFarland , Aref Fouladi , Jacob Glasby , Aruna Ramanayaka
show 5 more authors
Zachary Stegen Aaron Pesetski Mark Covington Gregory Boyd Jeremy Clark
This is my paper
classification quant-ph PACS 03.67.Lx85.25.Cp
keywords soliton DACJosephson transmission linetransmon S-gateflux controlnoise filtrationinterleaved randomized benchmarkingsuperconducting electronicscryogenic multiplexing
verification ladder T0 review T1 audit T2 compute T3 formal T4 reserved

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

This paper shows that a chain of Josephson junctions can turn a simple trapezoidal drive into a superconducting soliton that is parked in a load loop, thereby applying a controlled flux pulse to a nearby transmon. The resulting device acts as a digital-to-analog converter that both filters classical control noise and natively multiplexes many gates from a single line. In the first chip demonstration, the DAC executes 5.6-nanosecond S-gates with only 0.05 percent excitation per gate and no added relaxation beyond the qubit’s own T1. The same measurements reveal that the dominant error when thirty DACs fire together is a 1.6 percent non-local phase error felt even by uncoupled spectator qubits. The authors argue that modest resistive damping of the middle junctions plus a DC-tunable coupler will push the gate error well below surface-code thresholds, giving a path to CMOS-driven, noise-buffered control of large superconducting processors.

Core claim

A superconducting soliton DAC can launch, hold, and annihilate a flux soliton so that a single trapezoidal input produces a clean, fixed-duration flux pulse that performs a high-fidelity S-gate on a mutually coupled transmon in 5.6 ns; the measured per-gate excitation is 0.05 percent and the induced relaxation stays below the qubit’s intrinsic T1, while simulations show that overdamping the load junction can cut the excitation another factor of ten.

What carries the argument

The Josephson-transmission-line soliton: a stable flux kink that propagates ballistically down a chain of grounded junctions and is captured in a load loop, converting a noisy digital edge into a smooth analog flux waveform whose amplitude and duration set the qubit phase.

Load-bearing premise

The non-local phase errors seen on spectator qubits come only from high-frequency ringing of the middle junctions and can be removed by modest resistive shunts without creating new decoherence or slowing the gate.

What would settle it

Fabricate a multi-DAC chip with 50–100 ohm shunts on every middle junction, repeat the interleaved randomized benchmarking on both a directly coupled qubit and an uncoupled ancilla, and check whether the 1.6 percent non-local phase error disappears while the 5.6 ns S-gate fidelity improves to the simulated 4e-6 level.

Watch this falsifier — get emailed when new claim-graph text bears on it.

If this is right

  • A single noisy CMOS or room-temperature line can drive many independently timed gates without degrading qubit T2 once the drive stays below the soliton threshold.
  • Adding a DC-biased tunable coupler between each DAC and its qubit allows fixed-time gates that correct fabrication scatter and flux offsets by a simple bias voltage.
  • Multiplexing those DC biases with existing superconducting flux memory removes the microwave-wiring bottleneck for large processors.
  • Overdamping the load junction alone is predicted to drop the residual excitation rate another order of magnitude, placing single-DAC error well below the surface-code threshold.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • If the EMI is truly localizable to the middle junctions, the same soliton DAC layout can be reused for fluxonium or flux-qubit control without redesign of the quantum chip.
  • The observed interference pattern versus drive amplitude offers a built-in diagnostic for soliton timing jitter that could be turned into an on-chip calibration tone.
  • Combining the DAC with cryo-CMOS at 10 K would place the entire classical control stack inside the cryostat while the soliton buffer still isolates the millikelvin qubits from CMOS noise.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit.

Referee Report

2 major / 5 minor

Summary. The manuscript introduces a superconducting soliton DAC based on a Josephson transmission line that converts a trapezoidal drive into a held soliton, applying flux to a mutually coupled transmon (or coupler) for nanosecond phase gates. It reports a 5.6 ns S-gate demonstration on a 30-DAC chip, with measured peak DAC-induced |0 angle o|1 angle excitation of 0.05% per gate, DAC-induced relaxation below the intrinsic T1 limit, and strong passive noise filtration (no T2* degradation until the soliton injection threshold). WRS+Circuitizer simulations reproduce the qualitative excitation interference pattern and predict single-DAC gate errors as low as ~4 imes10^{-6} for optimized load-loop damping. IRB, however, shows that the dominant error when all 30 DACs share a drive line is a ~1.6% non-local phase error on uncoupled ancillae, which the authors attribute to underdamped middle-JJ plasma oscillations and propose to mitigate with resistive shunts plus a DC-tunable coupler.

Significance. If the architecture works as claimed, it offers a practical path past the microwave-wiring bottleneck for flux-tunable superconducting qubits: a single noisy digital line (compatible with cryo-CMOS) can address many gates while providing strong noise filtration and native multiplexing. The experimental demonstration of 5.6 ns S-gates, quantitative excitation/relaxation data, and clear T2* protection measurements are concrete and valuable. The single-DAC Circuitizer noise sampling (Fig. 8) supplies a falsifiable design target (~4 imes10^{-6}). The work is therefore of genuine interest for scalable control, provided the multi-DAC EMI channel can be brought under control.

major comments (2)
  1. §IV and Fig. 6b: The IRB data establish a ~1.6% non-local phase error on ancillae that are not galvanically or mutually coupled to any DAC, appearing only when the shared drive exceeds the soliton threshold. This is the dominant measured error and is load-bearing for any multi-qubit scaling claim. All Circuitizer results (Fig. 8) model only a single DAC; multi-DAC EMI is omitted. The proposed fix—50–100 Ω shunts on middle JJs—is stated as a hypothesis without a quantitative residual-EMI estimate or a measurement on a shunted multi-DAC device. Either a simulation of residual phase error after shunting or an explicit statement that the present fidelity floor is set by this unmodeled channel is required before the architecture can be claimed to approach the simulated 4 imes10^{-6}.
  2. §IV (hold-time resolution paragraph) and conclusion: The 200 ps AWG resolution already implies a ~0.1% phase-error floor for a 5.6 ns S-gate. The manuscript correctly notes that a DC-tunable DAC–qubit coupler (or 20 ps timing) is needed to reach the simulated fidelity, yet no experimental demonstration or even a circuit-level estimate of that coupler’s residual error is provided. Because the abstract and conclusion present the soliton DAC as enabling “high-fidelity” fixed-time gates robust to fabrication variance, the gap between the measured ~2% IRB error and the simulated single-DAC limit must be quantified more carefully, including the contribution of hold-time jitter.
minor comments (5)
  1. Abstract: the sentence beginning “may be limited by a Interleaved Randomized Benchmarking…” is grammatically broken and appears to be a paste artifact; rewrite for clarity.
  2. Fig. 5 caption and §IV: the experimental excitation probability (0.05%) is stated to be higher than the single-DAC simulation in part because of the 30 simultaneously triggered DACs; a quantitative estimate of that contribution (even an upper bound) would strengthen the comparison.
  3. §II: the continuum Sine-Gordon derivation (Eqs. 1–4) is standard, but the discrete-to-continuum mapping for the chosen eta=0.5, 10-spoke design could be stated more explicitly so that readers can reproduce the soliton size (~1.5 JJs).
  4. Fig. 2: the noise-transfer-function curves would be clearer if the qubit-frequency band (5–12 GHz) were shaded and the units of the vertical axis made explicit.
  5. References: a few recent SFQ-control and cryo-CMOS works are cited; adding the most recent multi-chip SFQ–qubit demonstrations would help place the soliton approach in context.

Circularity Check

0 steps flagged

No circularity: experimental gate metrics and noise-protection results are direct measurements; simulations are independent circuit models used for design optimization and qualitative comparison, not re-labeled fits of the same data.

full rationale

The paper's load-bearing claims (5.6 ns S-gates, 0.05% peak DAC-induced excitation per gate, sub-T1 relaxation, T2 protection below Icrit, and 1.6% non-local ancilla phase error) are obtained from Ramsey, excitation/relaxation, and IRB sequences on fabricated devices (Figs. 3, 5, 6). The soliton description is the standard continuum Sine-Gordon limit of the discrete JTL (Eqs. 1-4, citing McLaughlin & Scott 1978), not a self-derived uniqueness theorem. Circuitizer/WRS simulations generate waveforms and sample Johnson-Nyquist noise to compute leakage + phase-error infidelity for varied L/R; the mutual is set so the noise-free phase equals π/2 by design (standard device sizing), then the resulting ensemble-averaged error (min ~4e-6) is reported as a prediction for a future overdamped layout. This is not a fit-to-data re-labeled as prediction, nor does any central claim reduce by construction to an input parameter or self-citation chain. Citations are to external literature (surface codes, SFQ control, cryo-CMOS, flux memory). The multi-DAC EMI hypothesis and proposed middle-JJ shunts are explicitly future work, not used to force the present experimental numbers. The derivation chain is therefore self-contained against external benchmarks.

Axiom & Free-Parameter Ledger

4 free parameters · 3 axioms · 1 invented entities

The work rests on standard Josephson-circuit physics (Sine-Gordon solitons, RCSJ model) plus a handful of design inequalities verified by WRS Monte Carlo. Free parameters are ordinary circuit values chosen for fabrication and gate timing; no new particles or forces are postulated. The main unproven extrapolation is that resistive damping of middle JJs will eliminate the observed non-local EMI without side effects.

free parameters (4)
  • soliton hold time = 5.6 ns
    Set to 5.6 ns by AWG resolution and desired S-gate angle; directly controls accumulated phase.
  • final-JJ shunt resistance = 10 Ω
    Chosen (10 Ω, three-shunt variant) to set L/R slew rate; varied in simulation to optimize leakage vs. resistor noise.
  • DAC-qubit mutual inductance M = 4.6 pH
    Fixed at 4.6 pH in the fabricated chip; set in simulation so noise-free flux yields exactly π/2.
  • spoke β = L/LJJ = ≈0.5
    Design window 0.3–0.9 required for clean soliton propagation; used β≈0.5.
axioms (3)
  • domain assumption Continuum Sine-Gordon equation (Eq. 3) adequately describes the discrete 10-spoke JTL when soliton size ≪ number of spokes.
    Invoked in §II to justify soliton solutions and noise filtration; verified only by WRS continuum-limit comparison.
  • domain assumption 10% overdrive above Icrit plus small negative DC bias prevents soliton pinning by Ic disorder.
    Stated after Monte Carlo WRS runs in §II; assumed true for all fabricated devices.
  • ad hoc to paper Non-local phase errors observed on ancillae originate from underdamped plasma oscillations of middle JJs and can be suppressed by 50–100 Ω shunts.
    Hypothesis advanced in §IV and conclusion; not independently measured or simulated for the multi-DAC layout.
invented entities (1)
  • soliton DAC (JTL + damped load loop held for gate time) independent evidence
    purpose: Transduce digital trapezoidal pulse into analog flux waveform for qubit phase control while filtering noise and enabling multiplexing.
    The combination of soliton injection, hold, and anti-soliton removal for a fixed-time gate is the paper’s central device concept; independent evidence is the experimental gate data themselves.

pith-pipeline@v1.1.0-grok45 · 16704 in / 2809 out tokens · 25470 ms · 2026-07-11T09:14:03.827084+00:00 · methodology

0 comments
read the original abstract

We introduce a superconducting digital-to-analog converter (DAC) that filters control noise, provides native multiplexing, performs quantum gates in nanoseconds, and can be controlled by CMOS. This is achieved by transducing a trapezoidal drive pulse into a superconducting soliton, which is then held in the DAC load loop, applying flux to a mutually-coupled superconducting qubit or gate coupler. The analog flux output by the DAC can be easily controlled by varying the soliton hold time, or with a DC-biased tunable DAC-qubit coupler, allowing the DAC to perform a fixed-time, high-fidelity gate that's robust to fabrication variance or flux offsets in the quantum circuit. Our initial demonstration shows that the DAC can successfully perform 5.6 ns S-gates on transmons. We measure the DAC-induced quantum state excitation probability per gate to be 0.05%, and find that the DAC-induced relaxation rate from the qubit 1 state is below the intrinsic T1 rate limit of the transmon. Quantum simulations show qualitative agreement with the measured data, and predict that the DAC excitation rate can be lowered 10 times further by overdamping the Josephson junction (JJ) in the DAC load loop. may be limited by a Interleaved Randomized Benchmarking (IRB) sequences on an observer qubit reveal that, when scaling to many qubits, the DAC's performance may be limited by a non-local, DAC-induced phase error of 1.6% per gate, appearing in ancilla qubits that are not directly coupled to any of the 30 DACs on the chip. We discuss strategies for future layouts of multi-DAC chips that focus on mitigating the source of these non-local, high-frequency electromagnetic interactions (EMI), and how to incorporate a DC-tunable coupler for phase correction.

Figures

Figures reproduced from arXiv: 2607.05072 by Aaron Pesetski, Aditya Sharma, Aref Fouladi, Aruna Ramanayaka, Derek Reitz, Gregory Boyd, Jacob Glasby, Jeremy Clark, John McFarland, Mark Covington, Ryan Bilotta, Tony X. Zhou, Zachary Stegen.

Figure 1
Figure 1. Figure 1: FIG. 1. Schematic showing the soliton DAC with mutually [PITH_FULL_IMAGE:figures/full_fig_p002_1.png] view at source ↗
Figure 3
Figure 3. Figure 3: FIG. 3. Soliton DAC qubit protection demonstration via [PITH_FULL_IMAGE:figures/full_fig_p003_3.png] view at source ↗
Figure 2
Figure 2. Figure 2: FIG. 2. Square of the current transfer function that relates [PITH_FULL_IMAGE:figures/full_fig_p003_2.png] view at source ↗
Figure 4
Figure 4. Figure 4: FIG. 4. Four trapezoidal waveforms with varied amplitudes [PITH_FULL_IMAGE:figures/full_fig_p004_4.png] view at source ↗
Figure 6
Figure 6. Figure 6: FIG. 6. Measured Character IRB data for a) soliton DAC [PITH_FULL_IMAGE:figures/full_fig_p005_6.png] view at source ↗
Figure 7
Figure 7. Figure 7: FIG. 7. WRSpice simulation of the DAC waveforms for varied [PITH_FULL_IMAGE:figures/full_fig_p006_7.png] view at source ↗
Figure 8
Figure 8. Figure 8: FIG. 8. 500 Circuitizer simulations for varied DAC load loop [PITH_FULL_IMAGE:figures/full_fig_p007_8.png] view at source ↗

discussion (0)

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