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Tensor-Compressed Back-Propagation-Free Training for (Physics-Informed) Neural Networks

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arxiv 2308.09858 v2 pith:T6SGQEKC submitted 2023-08-18 cs.LG cs.AI

classification cs.LGcs.AI
keywords trainingapproachbp-freeneuralnetworksframeworkimprovenetwork
verification ladder T0 review T1 audit T2 compute T3 formal
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Backward propagation (BP) is widely used to compute the gradients in neural network training. However, it is hard to implement BP on edge devices due to the lack of hardware and software resources to support automatic differentiation. This has tremendously increased the design complexity and time-to-market of on-device training accelerators. This paper presents a completely BP-free framework that only requires forward propagation to train realistic neural networks. Our technical contributions are three-fold. Firstly, we present a tensor-compressed variance reduction approach to greatly improve the scalability of zeroth-order (ZO) optimization, making it feasible to handle a network size that is beyond the capability of previous ZO approaches. Secondly, we present a hybrid gradient evaluation approach to improve the efficiency of ZO training. Finally, we extend our BP-free training framework to physics-informed neural networks (PINNs) by proposing a sparse-grid approach to estimate the derivatives in the loss function without using BP. Our BP-free training only loses little accuracy on the MNIST dataset compared with standard first-order training. We also demonstrate successful results in training a PINN for solving a 20-dim Hamiltonian-Jacobi-Bellman PDE. This memory-efficient and BP-free approach may serve as a foundation for the near-future on-device training on many resource-constraint platforms (e.g., FPGA, ASIC, micro-controllers, and photonic chips).

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Forward citations

Cited by 3 Pith papers

Reviewed papers in the Pith corpus that reference this work. Sorted by Pith novelty score. Full citation record

  1. Ultra Memory-Efficient On-FPGA Training of Transformers via Tensor-Compressed Optimization

    cs.LG 2025-01 conditional novelty 6.0 of 10

    A tensor-compressed transformer training accelerator on FPGA that stores all parameters on-chip, claiming 20-51x memory reduction and up to 4x energy savings per epoch versus an RTX 3090.

  2. Scaling of hardware-compatible perturbative training algorithms

    cs.LG 2025-01 conditional novelty 5.0 of 10

    Training time to a fixed accuracy for perturbative gradient methods grows far slower than linearly with network size, challenging a long-standing scaling objection.

  3. Experimental Demonstration of an Optical Neural PDE Solver via On-Chip PINN Training

    cs.LG 2025-01 reject novelty 4.0 of 10

    This paper reports a hardware demo in which a 1x4 microring weight bank is trained with zeroth-order optimization to solve a 1D heat equation to 5e-3 error.

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