REVIEW 1 major objections 5 minor 5 references
Performance of Devito on HPC-Optimised ARM Processors
T0 review · 1 major / 5 minor · reviewed 2026-08-14 · deepseek-v4-flash
Pith's one-line read ARM ThunderX2 matches Intel Xeon on seismic imaging kernels
desk verdict A clean, narrow ARM-vs-Xeon stencil benchmark whose 'seismic inverse problems' claim overreaches the two kernels actually measured. read the letter →
The pith
A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.
The reading
What carries the argument
The central object is Devito, a domain-specific language and compiler for finite-difference stencils, which turns symbolic equations into C++ code through a lowering pipeline. It applies several optimisation passes — the paper names basic, aggressive, and DSE modes — that handle cache reuse, register pressure, and loop structure. This machinery matters because the TTI stencil has high arithmetic intensity and high register pressure, while the acoustic kernel is memory-bound; Devito's job is to generate code that lets the ARM's 32 cores and high memory bandwidth express themselves without hand tuning. The paper's comparison therefore tests the combination of a portable DSL and an emerging hardware architecture, not just raw processor speed.
What would settle it
Run the same acoustic and TTI kernels with one common compiler (or matched optimisation levels) on a fully loaded ThunderX2 socket and a Xeon Gold socket at $768^{3}$ and $1024^{3}$ grids, and also in a multi-node MPI configuration; if the ARM wall-clock time grows to, say, more than 1.5 times the Xeon time on these larger production-sized runs, the claim of competitive performance on seismic inverse problems would be refuted.
Extended reading notes
Core claim
On the paper's own terms, the discovery is that a first-generation HPC-optimised ARM processor, the Marvell ThunderX2, delivers performance comparable to state-of-the-art Intel Xeon Gold processors when running Devito-generated finite-difference kernels for seismic imaging. At a $512^{3}$ grid with fourth-order stencils, the ThunderX2 executes the acoustic kernel in 11.0 seconds with 32 threads, against 14.7 seconds on a Xeon Gold 5120 and 13.6 seconds on a higher-clocked Xeon Gold, and runs the TTI kernel in 67.3 seconds versus 69.2 and 61.4 seconds. The ARM chip reaches 157.7 GFLOPS on acoustic and 212.3 GFLOPS on TTI, close to the Intel results, because the kernels are memory-bound and the ThunderX2 provides roughly double the measured memory bandwidth of the Intel sockets. The achieved fraction of peak performance falls from 63% to 25% as the acoustic space order rises from 4 to 16, confirming that memory bandwidth, not compute, sets the ceiling.
Load-bearing premise
The conclusion depends on two single-socket kernel benchmarks on one ARM processor standing in for production seismic inverse workloads, and on the different compiler versions used on each architecture not biasing the comparison.
Editorial extensions
If this is right
- A system with many ARM cores can match a Xeon socket on memory-bound stencil workloads, so core count and memory bandwidth can substitute for per-core vector throughput.
- Devito's generated code is portable: the same high-level equations compile into efficient code on both x86 and ARM without architecture-specific rewrites.
- Seismic imaging workloads of the acoustic and TTI type can run on ARM-based HPC nodes with wall-clock times competitive with current Intel servers.
- Because the kernels are memory-bound, the ARM advantage should be largest when the working set saturates memory bandwidth; increasing space order reduces achieved efficiency on both platforms.
- The measured GFLOPS values remain far below peak (63% at SO=4 down to 25% at SO=16), indicating that further gains must come from improving memory access patterns rather than raw floating-point capability.
Reading between the lines
- If the single-socket pattern extends to multi-node runs, ARM-based systems could offer comparable seismic throughput per dollar, but the paper's data do not cover MPI scaling, so that extension is unproven.
- The compiler mismatch (GCC 8.2 and CCE on ARM, GCC 7.4 on Intel) means part of the measured balance could reflect compiler maturity rather than hardware; a matched-compiler experiment would separate the two.
- The memory-bound explanation predicts that a compute-bound variant of the same kernels, or a smaller grid that fits in cache, would swing the comparison back toward the Xeons; that is a direct, testable consequence of the paper's mechanism.
- The paper tests only single-socket performance; on a production system the interconnect and MPI overheads could change the ranking, so the broad 'seismic inverse problems' claim is a hypothesis at node level.
Signed reviews
Editorial analysis
A structured set of objections, weighed in public.
Referee Report
Summary. This manuscript reports a single-socket performance study of the Devito finite-difference DSL on a Marvell ThunderX2 ARM processor, comparing execution times and achieved GFLOP/s against two Intel Xeon Gold processors (5120 and 6126) for two seismic stencil kernels: the acoustic wave equation and the TTI wave propagator. Experiments vary thread count, grid size, space order, compiler (GCC 8.2 and CCE 8.7.9 on ARM; GCC 7.4 on Intel), and Devito optimisation mode. The headline finding, stated in Section 4, is that ARM processors are capable of delivering performance similar to state-of-the-art Intel Xeon processors for seismic inverse problems, and that Devito can generate efficient code for ARM without architecture-specific tuning. The paper is a short empirical note that presents no new algorithmic or systems contribution beyond the measurement data itself.
Significance. If the reported results are taken at face value, the manuscript provides useful evidence that ARM server processors can reach competitive single-socket performance on memory-bound seismic stencil kernels when the full socket is used, and that a high-level DSL such as Devito can target ARM without manual refactoring. The strengths of the paper are that it uses real HPC hardware (Isambard/ThunderX2), reports a substantial sweep of kernel/grid/optimization combinations, and follows a deterministic thread-pinning and single-thread-per-core configuration that aids reproducibility. The main weakness is that the evidence does not support the broad concluding claim about 'seismic inverse problems', since no end-to-end inversion (RTM or FWI) or multi-node/communication phase is measured. The paper also does not provide the code, exact FLOP-count formulas, or complete compiler details needed to independently verify the GFLOP/s numbers. These issues are fixable in revision either by narrowing the claims or by supplying missing methodological detail.
major comments (1)
- [Table 2, column header] The last processor column is labeled 'Xeon Gold 6128' while the hardware table and the text refer to 'Xeon Gold 6126'. This is likely a typo, but it affects the reproducibility of the data; the label should be corrected and checked against the machine configuration.
minor comments (5)
- [Section 1, references] The text says 'Recent studies compared the single node performance and multi-node scalability of Arm systems [3–5]', but reference [5] is Zhang et al., a geophysics paper on TTI reverse time migration, not a performance study of ARM systems; the citation range should be corrected to avoid implying that the TTI paper contains single-node performance data.
- [Section 3, STREAM measurement] The paper states that memory bandwidth was measured with STREAM and that 'for the Arm we used CCE' while GCC was used for the Intel processors, but does not give the STREAM version, array sizes, or number of trials; adding these details would make the Table 1 bandwidth figures reproducible.
- [Section 3, Figure 1] The labels 'ideal' and 'linpack' in Figure 1 are not defined in the text or caption. The 'linpack' point presumably refers to the measured HPL value from Table 1, but the reader should be told what the 'ideal' curve represents and how the percentage values are computed relative to it.
- [Section 3, compiler comparison] The sentence 'The results shown for the Arm processor were produced by GCC, which presented slightly better performance compared to CCE' gives no quantitative comparison between GCC and CCE on ARM; a single sentence with representative execution times would make the compiler choice more transparent.
- [Section 2, Devito description] The phrase 'a pipeline of compilers and libraries' is vague; the paper would benefit from naming the specific components of the Devito lowering pipeline (e.g., SymPy, code generation, OpenMP/MPI backends) that are relevant to the experiments, so that readers know what 'integrated with other compilers' means in Section 3.
Circularity Check
No circularity: the paper's claims rest on direct measurements of external hardware, not on inputs absorbed from its own definitions or citations.
full rationale
This paper is an empirical performance study. The central claim in Section 4 ('Arm based processors are capable of delivering performance similar to state-of-the-art Intel Xeon processors for the execution of seismic inverse problems') is supported by wall-clock execution times, GFLOPS counts, speedups, and Roofline-style efficiency measurements collected on an external Isambard ARM system and compared against two Intel Xeon systems. None of these quantities is defined in terms of the conclusion, and no parameter is fitted to a subset of the data and then renamed as a prediction. The cited Devito papers [1,2] provide the kernel implementations and model specifications, but the paper's claim is about measured hardware performance using those kernels; the citations are appropriate provenance rather than load-bearing self-citation. The paper does not invoke any uniqueness theorem, nor does it smuggle in an ansatz via citation. The only notable gap is that the experiments cover two stencil kernels on a single socket, while the Conclusion speaks of 'seismic inverse problems' broadly; that is an over-generalization or external-validity concern, not a circularity. Accordingly, no circular step is identified and the circularity score is 0.
Assumptions & free parameters
assumptions (3)
- domain assumption The acoustic and TTI kernel implementations in [1] are correct and representative of production seismic imaging workloads.
- domain assumption The measured memory bandwidth values from STREAM accurately reflect achievable bandwidth for these kernels.
- domain assumption The hardware specifications in Table 1 are accurate as reported or measured.
Cite this review
Pith. "Pith review of Performance of Devito on HPC-Optimised ARM Processors." pith.science (2026). https://pith.science/paper/TGHUYF2W
@misc{pith2026190803653,
author = {Pith},
title = {Pith review of: Performance of Devito on HPC-Optimised ARM Processors},
year = {2026},
howpublished = {\url{https://pith.science/paper/TGHUYF2W}},
note = {Machine review of arXiv:1908.03653}
}
read the original abstract
We evaluate the performance of Devito, a domain specific language (DSL) for finite differences on Arm ThunderX2 processors. Experiments with two common seismic computational kernels demonstrate that Arm processors can deliver competitive performance compared to other Intel Xeon processors.
Figures
Reference graph
Works this paper leans on
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[1]
Mathias Louboutin, Michael Lange, Felix J Herrmann, Navjot Kukreja, and Gerard Gorman. 2017. Performance prediction of finite-difference solvers for different computer architectures. Computers & Geosciences 105 (2017), 148–157
work page 2017
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[2]
Fabio Luporini, Michael Lange, Mathias Louboutin, Navjot Kukreja, Jan Hück- elheim, Charles Yount, Philipp Witte, Paul H. J. Kelly, Gerard J. Gorman, and Felix J. Herrmann. 2019. Architecture and performance of Devito, a system for automated stencil computation. ACM TOMS (accepted for publication) 1, 1 (2019). http://arxiv.org/abs/1807.03032
arXiv 2019
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[3]
Simon Mcintosh-Smith, James Price, Tom Deakin, and Andrei Poenaru. 2018. Comparative Benchmarking of the First Generation of HPC-Optimised Arm Processors on Isambard. Concurrency and Computation Practice and Experience - Special Issue on the Cray User Group (2018)
work page 2018
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[4]
Simon McIntosh-Smith, James Price, Tom Deakin, and Andrei Poenaru. 2019. A performance analysis of the first generation of HPC-optimized Arm processors. Concurrency and Computation: Practice and Experience (2 2019), e5110. https: //doi.org/10.1002/cpe.5110
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[5]
Yu Zhang, Houzhu Zhang, and Guanquan Zhang. 2011. A stable TTI reverse time migration and its implementation. Geophysics 76, 3 (2011), WA3–WA11
work page 2011
Reviewed August 14, 2026 · model on record in the stance chip above.
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