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REVIEW 3 major objections 4 minor 46 references

Large Language Models (LLMs) for Electronic Design Automation (EDA)

T0 review · 3 major / 4 minor · reviewed 2026-08-05 · deepseek-v4-flash

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Pith's one-line read LLMs can take on real chip-design chores, this survey argues, and three case studies show how.

desk verdict A useful but uneven survey of LLM-for-EDA; the only quantitative case study is too weak to support the abstract's automation claim. read the letter →

arxiv 2508.20030 v1 pith:UASJCE5U submitted 2025-08-27 eess.SY cs.AIcs.ARcs.LGcs.SY

Kangwei Xu , Denis Schwachhofer , Jason Blocklove , Ilia Polian , Peter Domanski , Dirk Pflüger , Siddharth Garg , Ramesh Karri
show 5 more authors
Ozgur Sinanoglu Johann Knechtel Zhuorui Zhao Ulf Schlichtmann Bing Li
This is my paper
classification eess.SYcs.AIcs.ARcs.LGcs.SY
keywords LLMEDAhardwaredesignhigh-levelsynthesisverificationsystem-leveltestRTLgeneration
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

This special-session paper claims that large language models can simplify, and eventually automate, much of the electronic design automation workflow because chips and the scripts that build them are text. It surveys the field and then supports the claim with three of the authors' own case studies: one repairing C/C++ code so it can run through high-level synthesis, one generating testbenches and hunting behavioral mismatches between C and RTL, and one writing C programs that maximize power consumption on a RISC-V processor for system-level test. If the claim holds, hardware teams would need far less manual effort for HDL coding, debugging, and test generation. The paper itself flags that current methods still fall short of end-to-end design synthesis and names hallucination and privacy as open problems.

What carries the argument

The unifying mechanism is the alignment between hardware description languages and the textual formats LLMs are trained on. The load-bearing technical pieces in the case studies are: (1) retrieval-augmented generation with a repair template library, verified by C-RTL co-simulation, for HLS repair; (2) backward slicing plus spectra monitoring to focus LLM-generated test inputs on behavioral discrepancies; and (3) structural chain-of-thought prompting inside an evolutionary candidate-pool loop, with temperature adaptation and Levenshtein-distance diversity pressure, for system-level test generation. Each case study closes the loop with a deterministic EDA tool (HLS compiler, simulator, FPGA po

What would settle it

Run the three case-study pipelines, with code and prompts made public, on hardware tasks outside the authors' group—e.g., HLS repair of a different benchmark suite, testbench generation for an open RISC-V core, and SLT power generation for a different processor—and measure whether LLM output is usable without human rewriting.

Watch

Extended reading notes

Core claim

The core claim is that because HDL code, HLS C/C++, and test programs are text, LLMs can serve as general-purpose assistants across the entire chip design-to-manufacturing flow, from specification to physical implementation and test. The paper presents three case studies: (i) LLM-aided repair of C/C++ programs into HLS-compatible form, using retrieval-augmented generation plus equivalence verification; (ii) LLM-driven testbench adaptation and behavioral-discrepancy testing for HLS, using backward slicing, spectra monitoring, and LLM-guided test-input generation; and (iii) an evolutionary loop that uses structural chain-of-thought prompting and temperature adaptation to generate C snippets th

Load-bearing premise

The paper's general conclusion assumes that the three case studies, all drawn from the authors' own prior work, are representative of what LLMs can do across EDA rather than selected successes.

Editorial extensions

If this is right

  • HLS designers could submit ordinary C/C++ and have LLM repair convert it to synthesizable code, reducing manual rewriting.
  • Testbench generation and behavioral discrepancy testing could be partially automated, lowering verification effort.
  • System-level test programs could be generated automatically to stress non-functional conditions like power, without deep microarchitecture knowledge.
  • The feedback-loop pattern—LLM proposes, EDA tool scores, loop repeats—could generalize to other EDA tasks such as synthesis pragma tuning or layout script generation.
  • A unified multi-modal agent spanning specification, RTL, netlist, and layout is a plausible next target, though the paper marks it as an open challenge.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • The strongest generalization of the survey is likely the closed-loop pattern, not any single case study; the three cases are all tasks where a deterministic tool can score the LLM's output, which is exactly where LLM errors are catchable. For tasks without a cheap oracle, automation gains may be far smaller.
  • The SLT power-maximization approach seems directly transferable to other non-functional targets—temperature, switching activity, or instruction throughput—and to other processors, since the loop only needs a measurable score.
  • A testable extension: feed the same evolutionary loop with assembly-level snippets as a baseline; the paper's own comparison with genetic programming suggests the LLM advantage may be in producing realistic high-level code, not in raw optimization power.
  • If the field adopts this survey's framing, the next bottleneck will be benchmark diversity: progress claims will need standard suites that are not drawn from the proposing group's own tools.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

3 major / 4 minor

Summary. This special-session paper surveys recent applications of large language models (LLMs) across the electronic design automation (EDA) flow, from specification and HDL generation through verification, high-level synthesis (HLS) repair, logic synthesis, physical design, and system-level test (SLT). It presents three case studies drawn largely from the authors' prior work: an LLM-aided C/C++ program repair framework for HLS (Section III), an LLM-guided behavioral-discrepancy testing framework for HLS (Section III), and an LLM-driven optimization loop that generates power-maximizing C code for SLT on a RISC-V processor (Section V). The paper concludes that integrating LLMs into EDA is a 'transformative opportunity' that can simplify and even automate the entire workflow, and it lists future directions such as bridging semantic gaps, expert-level HLS, and multi-modal EDA agents.

Significance. If the empirical claims held, the paper would offer a useful structured map of a fast-moving area and a concrete demonstration that LLMs can generate nontrivial hardware artifacts. The paper has several strengths: clear figures, a detailed algorithmic description of the SLT optimization loop, and an explicit acknowledgment that the LLM result was not better than the genetic-programming baseline in the single reported comparison. It also cites a broad set of recent papers. However, the central claim rests on very thin quantitative evidence: the only numerical case study is a single unreplicated optimization run with unequal compute, the fine-tuning claim is unquantified, and the two HLS frameworks are presented without evaluation metrics. The paper is therefore more persuasive as a position statement and qualitative survey than as an empirical demonstration of automation.

major comments (3)
  1. [Section V (SLT case study)] The quantitative core of the paper is one LLM optimization run (24 h, 2021 snippets, best 5.042 W) compared with one GP run (39 h, best 5.682 W). There are no error bars, no multiple seeds, and the runtimes are unequal; the text even notes that GP kept improving after 24 h. This cannot support the claim that the LLM approach is 'promising' in a measurable sense. The sentence 'Compared to the off-the-shelf model, it performs significantly better' is also unsupported: no numbers, test set, or significance test are given. Since this case study is the only quantitative evidence for the abstract's automation promise, please either add replication/statistics or explicitly reframe the result as a single anecdotal data point, and report the fine-tuning comparison quantitatively or remove the 'significantly better' claim.
  2. [Section III (HLS repair and discrepancy testing)] The two HLS frameworks are described in algorithmic detail, but no evaluation results are reported: no repair success rate, no number of benchmarks, no baseline comparison for HLS-Repair, and no coverage or discrepancy-detection rate for HLSTester. Because these are two of the three case studies invoked to support the paper's central claim, their inclusion as 'demonstrations' does not provide evidence. Please either add the key quantitative results (or point to the specific numbers in the original papers) or clearly label these sections as workflow illustrations rather than empirical demonstrations.
  3. [Section II (State of the Art)] The paper describes itself as a 'comprehensive overview,' but the survey is a selective narrative without a search protocol, inclusion criteria, or comparative evaluation tables. Strong comparative statements, e.g., 'The CodeGen models outperformed ChatGPT-3.5 and performed similarly well to GPT-4' and 'the most capable model ... was the only one to significantly benefit from feedback,' are given without benchmark numbers or confidence information. This does not invalidate the survey, but it makes the 'comprehensive' characterization hard to verify and weakens the authority of the conclusions. Please add a comparative summary table with available metrics or qualify the scope of the overview.
minor comments (4)
  1. [References [21], [25]] Reference [25] (MCP4EDA) lists the same arXiv identifier (2309.09437) as reference [21]; this is likely a typo and should be corrected.
  2. [Figure 1] The rendered text in Figure 1 is garbled in places (e.g., 'LLSM [2' and the floating 'Compiler Log' box). Please check the figure source and caption for readability.
  3. [Section V] The temperature-adaptation schedule and the number of random examples per prompt (n) are key free parameters, but no formulas or settings are given in the text; the reader is referred to [37]. Consider giving at least the functional form or a small parameter table.
  4. [Abstract and Conclusion] The abstract and conclusion repeatedly state that LLMs can 'simplify and even automate the entire workflow.' Given the evidence in Section V, we recommend softening the wording to 'may help simplify' or 'show potential to simplify' unless additional experimental support is added.

Circularity Check

0 steps flagged · score 2.0 of 10

No circular derivation; case studies are self-citations but not reduction-to-input.

full rationale

The paper is a survey/special-session overview, not a derivation chain. The central claim (LLMs can simplify/automate EDA) is supported by a literature review and three case studies, two from prior work by the same authors [28],[30] and one from [37]. No equation or result is defined in terms of another result; no fitted parameter is renamed a prediction. The SLT comparison (Section V: 'Our optimization loop ran for 24 hours and produced 2021 snippets. The best snippet in this run consumes 5.042 W' vs a 39-hour GP run at 5.682 W) is an unreplicated empirical comparison, but the paper does not claim to have predicted this number from the inputs; it explicitly calls out runtime mismatch and multiple plausible causes. The statement that the fine-tuned Code Llama 'performs significantly better' lacks quantitative support, and the HLS frameworks in Section III are described without success rates; these are correctness/evidence weaknesses, not circularity. Self-citations are prevalent, but they cite published prior work as examples and outlook, not as an unexamined premise that forces the conclusion. No 'uniqueness theorem' is imported and no ansatz is smuggled in via citation. Therefore no specific circular step can be identified; the low score reflects only the paper's heavy reliance on the authors' own prior studies as illustrative evidence.

Assumptions & free parameters 2 free parameters · 2 assumptions · 0 invented entities

As a survey, the paper introduces no new parameters or entities; the listed assumptions and hidden hyperparameters are from the case studies that carry the paper's examples.

free parameters (2)
  • LLM temperature adaptation schedule
    Section V describes a dynamic schedule based on score and Levenshtein distance but gives no numerical values; the reported power result depends on this schedule.
  • Number of random examples per prompt (n)
    Section V says the prompt is generated using 'n randomly picked examples' but n is not specified.
assumptions (2)
  • domain assumption C-RTL co-simulation correctly verifies functional equivalence of repaired HLS code.
    Section III uses co-simulation as the equivalence check; if it misses discrepancies, repair quality is overstated.
  • domain assumption FPGA power measurement is a valid proxy for marginal defect detection in system-level test.
    Section V uses power consumption to rank test programs, based on the prior result [32] that some defects need high power/temperature; if the correlation is weak, the optimization target loses meaning.

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Cite this review

Pith. "Pith review of Large Language Models (LLMs) for Electronic Design Automation (EDA)." pith.science (2026). https://pith.science/paper/UASJCE5U

@misc{pith2026250820030,
  author       = {Pith},
  title        = {Pith review of: Large Language Models (LLMs) for Electronic Design Automation (EDA)},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/UASJCE5U}},
  note         = {Machine review of arXiv:2508.20030}
}
read the original abstract

With the growing complexity of modern integrated circuits, hardware engineers are required to devote more effort to the full design-to-manufacturing workflow. This workflow involves numerous iterations, making it both labor-intensive and error-prone. Therefore, there is an urgent demand for more efficient Electronic Design Automation (EDA) solutions to accelerate hardware development. Recently, large language models (LLMs) have shown remarkable advancements in contextual comprehension, logical reasoning, and generative capabilities. Since hardware designs and intermediate scripts can be represented as text, integrating LLM for EDA offers a promising opportunity to simplify and even automate the entire workflow. Accordingly, this paper provides a comprehensive overview of incorporating LLMs into EDA, with emphasis on their capabilities, limitations, and future opportunities. Three case studies, along with their outlook, are introduced to demonstrate the capabilities of LLMs in hardware design, testing, and optimization. Finally, future directions and challenges are highlighted to further explore the potential of LLMs in shaping the next-generation EDA, providing valuable insights for researchers interested in leveraging advanced AI technologies for EDA.

Figures

Figures reproduced from arXiv: 2508.20030 by the authors.

Figure 1
Figure 1. Typical chip design flow and potential LLM applications. [PITH_FULL_IMAGE:figures/full_fig_p001_1.png] view at source ↗
Figure 2
Figure 2. Automated C/C++ program repair with LLMs for HLS. [PITH_FULL_IMAGE:figures/full_fig_p002_2.png] view at source ↗
Figure 3
Figure 3. Efficient testing of behavioral discrepancies with LLMs for HLS. [PITH_FULL_IMAGE:figures/full_fig_p002_3.png] view at source ↗
Figures from the paper (3 more)
Figure 4
Figure 4. Figure 4: AutoChip design framework with tree-search [8]. [PITH_FULL_IMAGE:figures/full_fig_p003_4.png]
Figure 5
Figure 5. Figure 5: Flow of the optimization loop. can control these non-functional properties, especially without extensive knowledge about the DUT. Automatically generating code in a high-level language such as C is highly challenging. There are methods that can reliably generate assemb…
Figure 6
Figure 6. Figure 6: LLM-aided EDA Agent: Unifying Multi-Modal Across the Full Flow [PITH_FULL_IMAGE:figures/full_fig_p005_6.png]

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Reference graph

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