Typed states for the displayed outbound observations.
Source: paper_references, paper_reference_links, observed 2026-08-14T15:17:22.493073Z
Paper Citation Record · LEDGER
As of 16 August 2026, this Paper Citation Record lists 32 of 32 outbound references and 0 inbound Pith citation observations for arXiv:1908.01466.
A citation records a reference. It does not transfer a finding from one paper to another.
Typed states for the displayed outbound observations.
Source: paper_references, paper_reference_links, observed 2026-08-14T15:17:22.493073Z
One-hop event checks from named stored sources.
Source: scholarly_work_events, retraction_status_cache, observed 2026-08-16T06:30:59.297886+00:00
Pith citing papers itemized under the disclosed page cap.
Source: paper_references, paper_reference_links
A source-named dated measurement, never combined with another source.
Source: cited_works
32 of 32 outbound references displayed
External citation measurements
No source-named external measurement is stored.
Observation 18bc3c74-8982-4e92-a5f7-f523176c88ab · outbound
PERI: A Posit Enabled RISC-V Core Cramming more components onto integrated circuits, reprinted from electronics, volume 38, number 8, april 19, 1965, pp.114 ff,
Reference 1
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-16T06:30:59.297886+00:00.
Observation 448bb0f2-f5a7-4838-9e47-3c4a46660db3 · outbound
PERI: A Posit Enabled RISC-V Core Design of ion-implanted mosfet’s with very small physical dimensions,
Reference 2
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-16T06:30:59.297886+00:00.
Observation 51ff3808-b692-4bbd-b213-5d61259362b4 · outbound
PERI: A Posit Enabled RISC-V Core Ieee standard for floating-point arithmetic,
Reference 3
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-16T06:30:59.297886+00:00.
Observation dfb249bd-f7a8-4a05-9ff0-657806c98a80 · outbound
PERI: A Posit Enabled RISC-V Core A transprecision floating-point platform for ultra-low power computing,
Reference 4
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-16T06:30:59.297886+00:00.
Observation bc9fc79f-3117-48a0-9d0a-581f805f57a4 · outbound
PERI: A Posit Enabled RISC-V Core Open-source variable-precision floating-point library for major commercial fpgas,
Reference 5
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-16T06:30:59.297886+00:00.
Observation 3d30a0d4-8aef-4a5d-9567-a9c5eea59407 · outbound
PERI: A Posit Enabled RISC-V Core Precision & performance: Floating point and ieee 754 compliance for nvidia gpus
Reference 6
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-16T06:30:59.297886+00:00.
Observation 33c06d02-74b2-4d99-81a9-7ca020be91fe · outbound
PERI: A Posit Enabled RISC-V Core Be more familiar with our enemies and pave the way forward: A review of the roles bugs played in software failures,
Reference 7
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-16T06:30:59.297886+00:00.
Observation 7034192f-7a88-4d14-9777-7882971127b4 · outbound
PERI: A Posit Enabled RISC-V Core Beating floating point at its own game: Posit arithmetic,
Reference 8
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-16T06:30:59.297886+00:00.
Observation 948fab29-9738-438f-82ba-f4ba11ed24ba · outbound
PERI: A Posit Enabled RISC-V Core Universal number posit arithmetic generator on fpga,
Reference 9
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-16T06:30:59.297886+00:00.
Observation 1b51ae02-68da-464e-b03f-0375f89f2820 · outbound
PERI: A Posit Enabled RISC-V Core Architecture generator for type-3 unum posit adder/subtractor,
Reference 10
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-16T06:30:59.297886+00:00.
Observation 73e1e20b-e840-4d69-8af9-0075af40fd73 · outbound
PERI: A Posit Enabled RISC-V Core High-level .net software implementations of unum type i and posit with simultaneous fpga implementation using hastlayer,
Reference 11
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-16T06:30:59.297886+00:00.
Observation 502d5890-49c2-4c7f-8f22-454f6ac0fcb0 · outbound
PERI: A Posit Enabled RISC-V Core Hardware implementation of posits and their application in fpgas,
Reference 12
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-16T06:30:59.297886+00:00.
Observation 026e9b24-f85f-4fea-ae62-ce7d40c3ab16 · outbound
PERI: A Posit Enabled RISC-V Core Enhancing accuracy and dynamic range of scientific data analytics by implementing posit arithmetic on fpga,
Reference 13
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-16T06:30:59.297886+00:00.
Observation d09c689e-9417-45ed-86b6-122d0b1acb6d · outbound
PERI: A Posit Enabled RISC-V Core Parameterized posit arithmetic hardware generator,
Reference 14
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-16T06:30:59.297886+00:00.
Observation b162dca2-c435-4b54-a9e6-abc3fe112061 · outbound
PERI: A Posit Enabled RISC-V Core Pacogen: A hardware posit arithmetic core generator,
Reference 15
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-16T06:30:59.297886+00:00.
Observation 0edaa1a2-52c4-42ca-98a0-3eda88f710b5 · outbound
PERI: A Posit Enabled RISC-V Core The risc-v instruction set manual. volume 1: User-level isa, version 2.0,
Reference 16
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-16T06:30:59.297886+00:00.
Observation ce6243f5-8210-440f-89d5-59b397e78d90 · outbound
PERI: A Posit Enabled RISC-V Core Shakti processors: An open-source hardware initiative,
Reference 17
Source-reported events for the cited work
Unavailable: canonical work link unavailable.
Observation e1c6cee1-349d-4035-9a05-bd0552b7a10b · outbound
PERI: A Posit Enabled RISC-V Core The rocket chip generator,
Reference 18
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-16T06:30:59.297886+00:00.
Observation ae05cbd5-6e72-4898-840e-1eb966a04053 · outbound
PERI: A Posit Enabled RISC-V Core The lowRISC project,
Reference 19
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-16T06:30:59.297886+00:00.
Observation 057c1ca7-3b9c-45e7-9951-5d793aeb8631 · outbound
PERI: A Posit Enabled RISC-V Core Pulp: A parallel ultra low power platform for next generation iot applications,
Reference 20
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-16T06:30:59.297886+00:00.
Observation 25320d08-a0f4-4a15-b976-543637774b28 · outbound
PERI: A Posit Enabled RISC-V Core RISC-V SweRV Core,
Reference 21
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-16T06:30:59.297886+00:00.
Observation a15defa8-ad13-4880-a09d-e221309eae9f · outbound
PERI: A Posit Enabled RISC-V Core Open-source RISC-V CPUs,
Reference 22
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-16T06:30:59.297886+00:00.
Observation 6259d5aa-7afa-4a04-88ce-d0ceec897459 · outbound
PERI: A Posit Enabled RISC-V Core An Introduction to the Rocket Custom Coprocessor Interface,
Reference 23
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-16T06:30:59.297886+00:00.
Observation c58f1854-9bcb-46b0-aa60-2ca41d312757 · outbound
PERI: A Posit Enabled RISC-V Core Bluespec Inc. Bluespec System Verilog,
Reference 24
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-16T06:30:59.297886+00:00.
Observation ebd1f480-ae2b-434c-bff5-37700e03985f · outbound
PERI: A Posit Enabled RISC-V Core Softposit library,
Reference 25
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-16T06:30:59.297886+00:00.
Observation eeb96cdb-9b2a-4db6-970b-60a209f0ce24 · outbound
PERI: A Posit Enabled RISC-V Core Posit Numeric Unit (PNU) Implementation by Calligo Technologies,
Reference 26
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-16T06:30:59.297886+00:00.
Observation 59871093-6038-43a6-8b93-c70cf5156ab4 · outbound
PERI: A Posit Enabled RISC-V Core Posit Implementation by VividSparks,
Reference 27
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-16T06:30:59.297886+00:00.
Observation 7bafb1cb-17a9-490c-82b9-b76238549213 · outbound
PERI: A Posit Enabled RISC-V Core Confidence interval,
Reference 28
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-16T06:30:59.297886+00:00.
Observation 0a206e62-d29c-4ec5-8f23-541a4de0032f · outbound
PERI: A Posit Enabled RISC-V Core The use of multiple measurements in taxonomic prob- lems,
Reference 29
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-16T06:30:59.297886+00:00.
Observation 4e825dce-916f-401d-911d-a059d4b067a4 · outbound
PERI: A Posit Enabled RISC-V Core Nuclear feature extraction for breast tumor diagnosis,
Reference 30
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-16T06:30:59.297886+00:00.
Observation 3404da42-5611-4854-af9f-4253b6238242 · outbound
PERI: A Posit Enabled RISC-V Core A probabilistic classification system for predicting the cellular localization sites of proteins,
Reference 31
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-16T06:30:59.297886+00:00.
Observation 0ad31b63-3fb5-4e29-be34-7119623621c5 · outbound
PERI: A Posit Enabled RISC-V Core Scikit-learn: Machine learning in Python,
Reference 32
Source-reported events for the cited work
Unavailable: canonical work link unavailable.
No inbound Pith citation observations are available.