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Superconductor bistable vortex memory for data storage and in-memory computing

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arxiv 2406.08871 v1 pith:UZLTCPP2 submitted 2024-06-13 cond-mat.supr-con cs.ET

Superconductor bistable vortex memory for data storage and in-memory computing

classification cond-mat.supr-con cs.ET
keywords memorysuperconductordesignanalogarraynonvolatileaddressescrossbar
verification ladder T0 review T1 audit T2 compute T3 formal T4 reserved
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Superconductor electronics (SCE) is a promising complementary and beyond CMOS technology. However, despite its practical benefits, the realization of SCE logic faces a significant challenge due to the absence of dense and scalable nonvolatile memory designs. While various nonvolatile memory technologies, including Non-destructive readout, vortex transitional memory (VTM), and magnetic memory, have been explored, achieving a superconductor random-access memory (RAM) crossbar array remains challenging. This paper introduces a novel, nonvolatile, high-density, and scalable VTM cell design for SCE applications. Our proposed design addresses scaling issues while boasting zero static power consumption characteristics. Our design leverages current summation, enabling analog multiply-accumulate operations -an essential feature for many in-memory computational tasks. We demonstrate the efficacy of our approach with a 32 x 32 superconductor memory array operating at 20 GHz. This design effectively addresses scaling issues and utilizes current summation that can be used for analog multiply-accumulate operations. Additionally, we showcase the accumulation property of the memory through analog simulations conducted on an 8 x 8 superconductor crossbar array.

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