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REVIEW 4 major objections 7 minor 79 references

STAGE generates realistic execution traces for distributed LLM training from a compact symbolic tensor graph, matching measured cluster behavior closely enough to serve as a stand-in for expensive real runs.

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T0 review · deepseek-v4-flash

2026-08-03 22:24 UTC pith:X2FMTQ5E

load-bearing objection A solid, well-scoped workload-generation framework with a genuinely new symbolic-tensor IR and Pull/Push collective matcher; the main weakness is that compute-time 'fidelity' is only validated in-sample on the benchmarked H100 stack. the 4 major comments →

arxiv 2511.10480 v3 pith:X2FMTQ5E submitted 2025-11-13 cs.DC cs.AI

Scalable Synthesis of distributed LLM workloads through Symbolic Tensor Graphs

Changhai Man , Joongun Park , Hanjiang Wu , Huan Xu , Srinivas Sridharan , Tushar Krishna This is my paper
classification cs.DC cs.AI
keywords symbolic tensor graphexecution trace synthesisdistributed LLM trainingparallelism strategiesmixture-of-expertsdesign space explorationworkload modelingexecution graph
verification ladder T0 review T1 audit T2 compute T3 formal T4 reserved

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

STAGE aims to make distributed-LLM workload modeling cheap and configurable by replacing real execution-trace collection with synthesis. The paper claims that a symbolic tensor graph—an intermediate representation in which tensor shapes carry distribution annotations like duplicate, partition, or partial-sum—can encode the structure of dense, mixture-of-experts, and state-space models, along with any combination of data, tensor, sequence, pipeline, and expert parallelism. From that graph, STAGE instantiates a full execution graph with per-tensor compute, memory, and communication, and validates it against traces from a 128-GPU H100 cluster: memory errors of a few percent, communication-volume errors below about 3%, and compute-time errors averaging 4.25%. If correct, system designers can explore parallelization strategies and hypothetical hardware without owning a multi-thousand-GPU cluster.

Core claim

The central claim is that a graph of symbolic tensor operations, annotated with sharding semantics, is a sufficient generative model for distributed LLM execution traces. STAGE assembles module templates (attention variants, feed-forward networks, MoE layers, normalization) into a whole model, distributes the workload across devices by rewriting tensor shapes with parallel dimensions, detects sharding mismatches between producers and consumers, inserts the corresponding collective communications, and then converts the symbolic graph to a numeric execution graph. The paper reports that this workflow reproduces operator counts, communication volumes, and peak memory within a few percent of mea

What carries the argument

The Symbolic Tensor Graph (STG), an intermediate representation where tensor shapes include symbolic dimensions and distribution markers (Duplicated, Partition, PartialSum), with all multiplications expressed as einsum. The load-bearing mechanism is the producer-consumer communication matcher: it views any sharding change as a Pull to a virtual node followed by a Push to consumers, which systematically derives the required collective (AllGather, AllReduce, ReduceScatter, AllToAll, or combinations) whenever a producer's output layout differs from what a consumer expects. This enables arbitrary hybrid parallel strategies without hand-coding each one.

Load-bearing premise

The compute-time fidelity rests on a lookup table and a roofline model calibrated on the same H100 cluster used for validation, so the reported accuracy is in-sample; if those calibration constants change on other GPUs, networks, or software stacks, the claimed tensor-level accuracy at 32K GPUs would not transfer automatically.

What would settle it

Take a standard dense LLM (say, a 70B-parameter transformer), collect fresh execution traces on a different accelerator generation without feeding them to STAGE, and compare per-operator synthesized compute times using STAGE's default calibration; if the average error rises well above the reported 4.25% on comparable workload configurations, the calibration-transfer claim is falsified.

Watch this falsifier — get emailed when new claim-graph text bears on it.

If this is right

  • Designers can generate standardized execution-trace graphs for models like GPT-3, LLaMA-3, and DeepSeek-MoE under any combination of DP, TP, SP, PP, EP, and FSDP, without running the training job.
  • At 32K GPUs, a 540B-parameter dense model's graph is synthesized in about 28 minutes, and memory usage stays under 500 MB, making large-scale design-space exploration practical on a single workstation.
  • The generated graphs preserve compute-communication dependencies, so simulators can reveal overlap opportunities; the paper shows FSDP's extra communication is often hidden by compute, and that optimal parallelism shifts with HBM capacity and network bandwidth.
  • The symbolic representation extends beyond transformers: the paper shows it can express state-space models, fully-sharded tensor parallelism (a not-yet-existing strategy), and tensor-train decomposition for non-ML workloads.
  • Validation results give concrete error bounds: communication volume errors mostly under 3%, peak-memory errors 1.3-7.4% (average ~2-3% after removing CUDA init), and compute-time errors averaging 4.25% across 12 workload configurations.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • Editorial inference: The fidelity numbers come from the same H100 cluster used to calibrate the compute model, so cross-platform transferability remains untested; a natural next experiment is generating traces for a different GPU generation with default calibration and comparing to fresh measurements.
  • Editorial inference: Because graph construction is separated from numeric instantiation, the real-data plug-in feature could be extended into a workflow that scales a small set of real kernel timings to a much larger synthetic cluster—bridging measured and synthesized traces in ways the paper only sketches.
  • Editorial inference: The communication matcher's automatic mismatch detection means STAGE could double as a feasibility oracle for hypothetical parallelization strategies (such as the fully-sharded tensor parallel example) before any implementation exists, which would be a useful contribution to parallel-strategy research.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit.

Referee Report

4 major / 7 minor

Summary. STAGE is a framework that generates Chakra-format execution graphs for distributed LLM (and MoE/SSM) workloads from a symbolic tensor-graph intermediate representation. Users specify a model template and parallelization strategy; STAGE instantiates tensor-level sharding, inserts collective communications via a producer-consumer matcher, and emits numeric execution graphs for downstream simulators such as ASTRA-Sim. The paper validates generated graphs against PyTorch/Chakra traces collected on 128 H100 GPUs, reporting peak-memory agreement of roughly 97% after excluding CUDA initialization, communication-volume errors mostly below 3% in aggregate, and compute-time errors of 0.3–15.0%. It further demonstrates generation scalability to 32K GPUs in under an hour and presents several design-space-exploration case studies. The central claim is that STAGE preserves tensor-level accuracy in compute, memory, and communication while scaling to systems far beyond those used for validation.

Significance. If established, STAGE would fill a real gap: it would let system designers generate large, realistic distributed-training workloads without access to a large cluster, and it would enable principled exploration of parallelization strategies, hardware topologies, and model variants. The paper has notable strengths: the symbolic abstraction is clean and general; the communication volumes and memory footprints are largely derived structurally rather than fit to the validation traces; the framework is released open-source; and the memory validation is strong. However, the compute-time fidelity rests on operator lookup tables and a roofline model calibrated on the same H100 software stack used for validation, and the paper itself concedes the accuracy is limited to that benchmarked system. The abstract and contributions currently overstate the evidence, especially for 32K-GPU traces where no ground truth exists. These issues are fixable, but the claims must be re-scoped or additional validation must be provided.

major comments (4)
  1. [§V-C, Table VIII, Abstract] The compute-time fidelity claim is in-sample. The compute model is calibrated on the same H100 stack (NeMo 24.07, CUDA 12.5, PyTorch 2.5.0) used for validation, and the paper concedes 'we can achieve a high accuracy that limited only to the benchmarked system.' Yet the Abstract promises tensor-level accuracy for traces spanning 32K GPUs, and §VI applies the same calibrated constants to 40/80/24 GB H100 variants and different network bandwidths without re-calibration or holdout validation. Please add a holdout validation (e.g., calibrate on a subset of models/configs and predict a held-out one, ideally on a different GPU/software stack) or explicitly restrict the fidelity claim to the benchmarked stack.
  2. [Table VI, §V-C] Operator-count fidelity for the 'Others' category is poor. For example, GPT-3-5B TP=8 shows 165,207 measured vs 21,504 synthesized 'Others' ops; DeepSeek 8E shows 46,938 vs 21,952. The authors argue these are negligible in runtime, but execution-graph fidelity also depends on dependency structure, critical paths, and overlap opportunities. Missing data-movement and memory-allocation nodes can change how ASTRA-Sim schedules communication around compute. Please report structural fidelity metrics (e.g., critical-path comparison or simulation sensitivity to the missing nodes) or narrow the claim to runtime-level fidelity for dominant operators.
  3. [Table VII, §V-D] Aggregate communication-volume errors are small, but per-type volumes can be off by an order of magnitude. For Mixtral 8x7 (128 GPUs), measured vs synthesized AllReduce is 0.329 vs 16.384 MB and ReduceScatter is 13,153 vs 17,717 MB; for DeepSeek 8E, AllGather is 142 vs 3,759 MB. The footnote attributes this to micro-batch-1 expert sparsity vs STAGE's all-experts-activated default. That is not a minor issue because §VI-C explicitly targets small-batch decoding where sparse expert activation is typical. Per-type volume determines network mix and overlap. Please either validate with a batch size that activates all experts or support sparse expert activation in STAGE and report per-type errors.
  4. [§VI-B, Fig. 13, Abstract] The 32K-GPU traces are generated but not validated, yet the Abstract states they preserve tensor-level accuracy in compute, memory, and communication. Ground truth is available only for the configurations in Tables V–VIII at up to 128 GPUs. Fidelity at 32K is an extrapolation that depends on the structural communication derivation and on compute constants calibrated at 128 GPUs. Please separate generation-time scalability, which is demonstrated, from fidelity at scale, which is not, or add validation on an intermediate cluster size.
minor comments (7)
  1. [Abstract] The provided abstract says 'spanning over 128K GPUs' while the full-text abstract and §VI say 32K GPUs. Please reconcile this inconsistency.
  2. [§I, Fig. 13] The contribution says '32K GPUs less than 30 minutes,' but Fig. 13 shows 50.79 minutes for Mixtral 8x7 at 32K GPUs. Rephrase as 'under about an hour' or describe per-model times.
  3. [§VI-B, Fig. 13] §VI-B says the scalability study spans 512 to 16K GPUs, while Fig. 13's x-axis starts at 2048 and goes to 32,768. Align the text with the figure.
  4. [Table V] The 'Error Rate*' column should state the exact formula, especially how 'after removing CUDA initialization' is applied to both measured and synthesized values.
  5. [§V-C] The sentence 'we can achieve a high accuracy that limited only to the benchmarked system, however, that is sufficient enough for our validation' is ungrammatical and should be rewritten; also 'are are negligible' appears in the same section.
  6. [Abstract and general] There are several typos and broken formatting, e.g., 'publicy available', 'emgering parallel strategies', and the GitHub URL 'https://github.com/astra-sim/symbolic tensor graph' contains a space and is not a valid link.
  7. [Fig. 4] The symbolic annotation labels in Fig. 4 are very small and hard to read in a print layout; consider higher-resolution vector graphics.

Circularity Check

0 steps flagged

No significant circularity; compute-time calibration is an acknowledged scope limitation, not a derivation from the target result.

full rationale

STAGE's central derivation is structural: symbolic tensor graphs (§IV-C) are assembled from model templates and parallelization strategies, distributed via tensor-level and graph-level distributors (§IV-D), and instantiated numerically (§IV-E). Communication operators and volumes, memory lifetimes, and operator counts are consequences of tensor sharding and dependency rules, and they are validated against real Chakra traces in Tables V–VII without being fitted to those traces. The only candidate for circularity is the compute-time model in §V-C: 'we utilized a compute model with a mixture of look-up table of benchmarked operators, as well as a calibrated roofline model based on benchmarked operators.' This calibration is performed on the same H100/NVIDIA NeMo stack used for validation, so the Table VIII error rates do not demonstrate transferability to unseen GPU/software stacks. However, the paper explicitly acknowledges the limitation: 'we can achieve a high accuracy that limited only to the benchmarked system, however, that is sufficient enough for our validation.' This is an admitted scope restriction rather than a hidden reduction of the claimed result to its own inputs. The compute model composes measured operator costs and is checked on workloads (different models, batch sizes, parallelism configurations) distinct from the calibration points, so the validation is meaningful, not tautological. Self-citations to Chakra [57] and ASTRA-Sim [66] are toolchain dependencies (output format and downstream simulator), not load-bearing evidence for accuracy; no uniqueness theorem or prior-work ansatz is used to force the central design. The 32K-GPU high-fidelity claim is extrapolated without validation at that scale, but that is a correctness-risk issue, not circularity. Overall, the graph structure, memory, and communication claims are independently grounded; the compute-time claim is honestly scoped to the benchmarked system.

Axiom & Free-Parameter Ledger

1 free parameters · 5 axioms · 0 invented entities

The central claim rests on standard math/einsum semantics plus domain assumptions about communication reducibility, DAG execution, and compute-time transferability. There are no newly postulated physical entities; the 'virtual node' in the communication matcher is an abstract modeling device, not a physical claim. The main fitted parameters are the compute-calibration constants.

free parameters (1)
  • compute calibration constants (roofline peaks and operator lookup table) = not reported
    §V-C: compute time is modeled with a 'calibrated roofline model based on benchmarked operators' on the same H100 hardware used for validation; these constants determine all compute-time fidelity numbers.
axioms (5)
  • standard math Einsum/symbolic tensor shape semantics correctly represent LLM computations.
    Used throughout §IV-C; the paper assumes tensor contractions and shape inference are faithful to real PyTorch/NVIDIA operations.
  • domain assumption Every collective communication can be decomposed into Pull then Push through a virtual node (Duplicated/Partition/PartialSum).
    §IV-D2, Fig. 6. If real systems use fused or non-composable collectives, generated graphs could miss or duplicate communication operations.
  • domain assumption The execution graph is a DAG with no dynamic control flow.
    Output is 'a directed acyclic graph (DAG) with explicit operation dependencies' (§IV-A). MoE expert routing is treated statically (all experts active by default), which the authors note diverges for micro-batch=1 in Table VII footnote.
  • ad hoc to paper Kernel timings calibrated on H100/H200 transfer to other hardware scales.
    §V-C 'calibrated roofline model based on benchmarked operators'; the 32K-GPU scalability results assume these constants remain valid at scale and on other systems.
  • domain assumption Memory lifetime follows immediate garbage collection after last use.
    §V-B 'assuming garbage collection immediately thereafter'; real allocators delay reuse, which the paper acknowledges as a source of the ~1GB discrepancy.

pith-pipeline@v1.3.0-alltime-deepseek · 29826 in / 10784 out tokens · 100724 ms · 2026-08-03T22:24:03.497784+00:00 · methodology

0 comments
read the original abstract

Optimizing the performance of large language models (LLMs) on large-scale AI training and inference systems requires a scalable and expressive mechanism to model distributed workload execution. Such modeling is essential for pre-deployment system-level optimizations (e.g., parallelization strategies) and hardware design-space explorations. While recent efforts have proposed collecting execution traces from real systems, access to large-scale infrastructure remains limited to major cloud providers. Moreover, traces capturing execution on a specific platform cannot be easily adapted to study alternate software and/or hardware configurations, especially at scale. We introduce STAGE, a framework that synthesizes high-fidelity execution graphs to accurately model distributed AI workloads (including LLMs and MoEs). STAGE supports a comprehensive set of parallelization strategies, allowing users to systematically explore a wide spectrum of model architectures and system configurations. STAGE demonstrates its scalability by synthesizing high-fidelity LLM traces spanning over 128K GPUs, while preserving tensorlevel accuracy in compute, memory, and communication. STAGE is publicy available at https://github.com/astra-sim/stage

Figures

Figures reproduced from arXiv: 2511.10480 by Changhai Man, Hanjiang Wu, Huan Xu, Joongun Park, Srinivas Sridharan, Tushar Krishna.

Figure 1
Figure 1. Figure 1: Overview of STAGE model behaviors rather than enabling exploration of diverse configurations or novel parallelization strategies. • Tied to AI Model. In the arms race of AI models, there continues to be rapid evolution of LLM architec￾tures—driven by innovations such as MoEs [12], [30], attention mechanism variants [3], [15], [62], and state space models [21], aimed at improving model accuracy and training… view at source ↗
Figure 2
Figure 2. Figure 2: An Example of Execution Trace for GPU Operations. [PITH_FULL_IMAGE:figures/full_fig_p003_2.png] view at source ↗
Figure 3
Figure 3. Figure 3: STAGE Generation Flow Overview. strategies to optimize system performance and resource uti￾lization. Common training frameworks such as Megatron [56], NeMo [24], and HuggingFace Accelerate [22] frequently integrate multi-dimensional parallelization, combining data parallelism, tensor parallelism, and pipeline parallelism. Fur￾ther optimizations, such as sequence parallelism, are also increasingly adopted i… view at source ↗
Figure 4
Figure 4. Figure 4: Using Symbolic Tensor Representation to Annotate MultiHead [PITH_FULL_IMAGE:figures/full_fig_p005_4.png] view at source ↗
Figure 5
Figure 5. Figure 5: Tensor Distribution Mismatch: After applying tensor-level distribution [PITH_FULL_IMAGE:figures/full_fig_p006_5.png] view at source ↗
Figure 6
Figure 6. Figure 6: Collective Communication can be divided into two steps: Pull + Push. [PITH_FULL_IMAGE:figures/full_fig_p006_6.png] view at source ↗
Figure 7
Figure 7. Figure 7: Timing breakdown for different operators [PITH_FULL_IMAGE:figures/full_fig_p009_7.png] view at source ↗
Figure 8
Figure 8. Figure 8: Peak Memory Usage vs Runtime across configurations. [PITH_FULL_IMAGE:figures/full_fig_p010_8.png] view at source ↗
Figure 11
Figure 11. Figure 11: Memory w/ and w/o Activation Recomputation [PITH_FULL_IMAGE:figures/full_fig_p010_11.png] view at source ↗
Figure 10
Figure 10. Figure 10: Compute-Comms Overlap vs Runtime, PaLM-540B @ 64 H100 [PITH_FULL_IMAGE:figures/full_fig_p010_10.png] view at source ↗
Figure 13
Figure 13. Figure 13: STAGE Runtime Scaling with Number of GPUs TABLE X [PITH_FULL_IMAGE:figures/full_fig_p011_13.png] view at source ↗

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