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Efficient Tabular Data Preprocessing of ML Pipelines

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arxiv 2409.14912 v1 pith:XHPZFUV5 submitted 2024-09-23 cs.AR cs.LG

classification cs.ARcs.LG
keywords preprocessingdatapipelinesperformancepipertrainingconsumptioncpus
verification ladder T0 review T1 audit T2 compute T3 formal

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abstract

Data preprocessing pipelines, which includes data decoding, cleaning, and transforming, are a crucial component of Machine Learning (ML) training. Thy are computationally intensive and often become a major bottleneck, due to the increasing performance gap between the CPUs used for preprocessing and the GPUs used for model training. Recent studies show that a significant number of CPUs across several machines are required to achieve sufficient throughput to saturate the GPUs, leading to increased resource and energy consumption. When the pipeline involves vocabulary generation, the preprocessing performance scales poorly due to significant row-wise synchronization overhead between different CPU cores and servers. To address this limitation, in this paper we present the design of Piper, a hardware accelerator for tabular data preprocessing, prototype it on FPGAs, and demonstrate its potential for training pipelines of commercial recommender systems. Piper achieves 4.7 $\sim$ 71.3$\times$ speedup in latency over a 128-core CPU server and outperforms a data-center GPU by 4.8$\sim$ 20.3$\times$ when using binary input. The impressive performance showcases Piper's potential to increase the efficiency of data preprocessing pipelines and significantly reduce their resource consumption.

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  1. RoCE BALBOA: Service-enhanced Data Center RDMA for SmartNICs

    cs.AR 2025-07 conditional novelty 6.0 of 10

    RoCE BALBOA is an open-source, 100G-capable RoCE v2 RDMA stack for FPGAs that interoperates with standard switches and NICs and supports line-rate service offloads with direct GPU memory access.

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