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Fast Virtual Gate Extraction For Silicon Quantum Dot Devices

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arxiv 2409.15181 v1 pith:YEQIMZ35 submitted 2024-09-23 cond-mat.mes-hall cs.AR

classification cond-mat.mes-hallcs.AR
keywords quantumdevicesexperimentalsiliconarrayschargeextractiongate
verification ladder T0 review T1 audit T2 compute T3 formal

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Silicon quantum dot devices stand as promising candidates for large-scale quantum computing due to their extended coherence times, compact size, and recent experimental demonstrations of sizable qubit arrays. Despite the great potential, controlling these arrays remains a significant challenge. This paper introduces a new virtual gate extraction method to quickly establish orthogonal control on the potentials for individual quantum dots. Leveraging insights from the device physics, the proposed approach significantly reduces the experimental overhead by focusing on crucial regions around charge state transition. Furthermore, by employing an efficient voltage sweeping method, we can efficiently pinpoint these charge state transition lines and filter out erroneous points. Experimental evaluation using real quantum dot chip datasets demonstrates a substantial 5.84x to 19.34x speedup over conventional methods, thereby showcasing promising prospects for accelerating the scaling of silicon spin qubit devices.

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  1. Short two-qubit pulse sequences for exchange-only spin qubits in 2D layouts

    quant-ph 2024-12 reject novelty 6.0 of 10

    A shortest-path swap-routing method produces pulse sequences for two-qubit exchange-only gates on 450 planar six-dot topologies, with experimental truth-table checks on Intel hardware.

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