Pith. sign in

REVIEW 2 major objections 4 minor 81 references

Short two-qubit pulse sequences for exchange-only spin qubits in 2D layouts

T0 review · 2 major / 4 minor · reviewed 2026-08-11 · deepseek-v4-flash

Challenge this review Re-run · record.json Download PDF Read on arXiv ↗ Review JSON

Pith's one-line read A graph-based routing method maps any exchange-only two-qubit sequence to arbitrary six-dot layouts with optimal spin-swap insertion, generating valid pulses for 450 topologies.

desk verdict Useful routing idea and a nice CXSWAP, but the central correctness proof ignores the unitary action of inserted swaps, so the pulse library is not established. read the letter →

arxiv 2412.14918 v3 pith:YMFJRAB3 submitted 2024-12-19 quant-ph cond-mat.mes-hall

Jason D. Chadwick , Gian Giacomo Guerreschi , Florian Luthi , Mateusz T. Mądzik , Fahd A. Mohiyaddin , Prithviraj Prabhu , Albert T. Schmitz , Andrew Litteken
show 4 more authors
Shavindra Premaratne Nathaniel C. Bishop Anne Y. Matsuura James S. Clarke
This is my paper · ORCID
classification quant-phcond-mat.mes-hall PACS 03.67.Lx
keywords exchange-onlyspinqubitsquantumdotarraystwo-qubitgatespulsesequenceoptimizationswapsCXSWAPsurfacecodeerrorcorrection
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

This paper claims that exchange-only two-qubit gates can be efficiently adapted to nearly any planar arrangement of six quantum dots by inserting spin-swap pulses according to a shortest-path search, rather than reoptimizing each gate from scratch. It demonstrates this on 450 unique six-dot topologies, producing pulse sequences for CX, CZ, iSWAP, and leakage-controlled variants that are up to 43% shorter than on a linear chain. The central payoff is a design rule: denser dot connectivity shortens two-qubit operations, and a CXSWAP can be produced at almost the same cost as a CX. The authors also test the generated pulses on fabricated hardware and use them to compare surface-code resource estimates, arguing that layout choice should be guided by pulse-level and error-correction considerations.

What carries the argument

The optimization graph: a layered directed acyclic graph whose nodes are reference-pulse-plus-spin-configuration pairs and whose edges are minimal sequences of spin swaps between configurations. The source fixes initial spin locations, the destination requires return to those locations (or a specified permutation), and an edge weight is the number of new pulses added after absorbing any new pulse into the most recent unblocked exchange on the same dot pair. Shortest path equals the optimal swap-inserted schedule for a fixed reference sequence, with reference sequences for CX, CZ, iSWAP, LCCX, and LCCZ derived from prior constructions.

What would settle it

Compute the full 64-dimensional unitary of any generated sequence, such as the 25-pulse CX on a linear topology with intraqubit permutations, and compare it to the reference sequence conjugated by the swap permutation; any discrepancy beyond global phase, or any leakage outside the logical subspace, would refute the claim that every path correctly implements the gate.

Watch

Extended reading notes

Core claim

The paper's central claim is that any exchange-only pulse sequence designed for all-to-all spin connectivity can be mapped to a restricted dot topology by inserting angle-pi spin swaps, and that the optimal such mapping is found as the shortest path in a layered directed acyclic graph. Each layer corresponds to one reference pulse; nodes are valid spin configurations in which the required spins sit on adjacent dots; edge weights count the additional pulses after merging new pulses with still-unblocked earlier ones. Because every path applies the reference pulses in order to correctly labeled spins and starts and ends at the same spin configuration, the paper asserts every path implements the desired logical gate. With this method the paper generates complete sequences for five two-qubit gates on 450 unique six-dot topologies, reports reductions in sequence length of up to 42.8%, and shows that relaxing final spin-location constraints shortens sequences further while a specific final permutation yields a CXSWAP gate at 7.34% average extra cost over CX. Experimental truth-table measurements on a linear six-dot device confirm the pulses act as expected.

Load-bearing premise

Inserting complete spin swaps (exchange pulses of angle pi) between the reference pulses, with all six spins returned to their starting dots, leaves the logical two-qubit gate unchanged; the paper asserts this rather than proving it.

Editorial extensions

If this is right

  • Hardware designers can choose any of the 450 planar six-dot topologies and obtain valid, near-optimal two-qubit pulses without running an expensive per-layout search.
  • Denser inter-qubit dot connections reduce pulse counts: for example, the linear-parallel class reaches a maximum of 22 CX pulses versus 28 for the fully linear class, and the densest triangular topology reaches 19 pulses.
  • Allowing the compiler to track intraqubit spin permutations shortens sequences for free, with reductions of 0 to 13% and a mean of 5.7%.
  • A CXSWAP gate costs on average only 7.34% more than a standard CX, making CXSWAP-based surface-code circuits practical without paying for a separate SWAP operation.
  • QEC resource estimates depend on parallelism restrictions, not just pulse count; denser layouts can perform worse under neighbor-based crosstalk restrictions.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • A direct test of the correctness assumption is to simulate the full six-spin unitary of a generated sequence and verify it equals the reference unitary up to spin relabeling; doing this for all 450 topologies would settle whether every path really implements the intended gate.
  • The same shortest-path formulation could be extended to optimize over pulse-order permutations within the reference sequence, something the paper leaves for future work and observes can shorten sequences by 1 to 2 pulses.
  • The routing approach could in principle scale to multi-qubit operations such as parity-check gates by constructing the search graph on demand and using heuristic pathfinding.
  • The nearly free CXSWAP suggests that QEC circuits elsewhere built from CX might be recompiled with CXSWAP as the native two-qubit gate on sparse layouts, potentially reducing circuit depth on hardware with large readout components.
Share X Bluesky LinkedIn Reddit HN

Signed reviews

No signed human review yet.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

2 major / 4 minor

Summary. The manuscript presents a swap-insertion ("swap-adding") optimization method for exchange-only two-qubit gates: starting from an all-to-all pulse sequence, it inserts π-exchange spin-swap pulses to route the six spins through a restricted dot connectivity, formulates the routing as a shortest-path problem on a layered directed acyclic graph, and generates a pulse library for CX, CZ, iSWAP, leakage-controlled CX, and leakage-controlled CZ on 450 planar six-dot topologies. The authors report sequence-length reductions across topology classes, introduce a CXSWAP operation and relaxed final-spin-permutation variants, validate selected sequences on an Intel Tunnel Falls device using truth-table overlap, and analyze teraquop footprints for four QEC layouts. The central correctness claim is that every path from source to destination in the optimization graph implements the desired operation because the reference pulses are applied in order to the correct spin labels with initial and final configurations fixed.

Significance. If the central correctness claim were established, the paper would be a useful engineering contribution: a fast topology-agnostic routing optimizer, a broad public pulse library, the CXSWAP abstraction, and a QEC-level comparison are all valuable steps for exchange-only spin-qubit architectures. The public release of the pulse library and the integration into the Intel quantum stack are concrete strengths. However, the correctness of the method is load-bearing for every reported result, and, as detailed below, the proof provided in Section IIIB2 does not establish it; the sequence lengths, the CXSWAP results, and the QEC conclusions all depend on swap-inserted sequences actually implementing the intended two-qubit unitaries. I do not see a parameter-fitting circularity; the reference-sequence dependence is acknowledged, though it should be stated more prominently.

major comments (2)
  1. [IIIB2] The proof that "any path ... correctly implements the desired operation" is not valid. A spin swap is the unitary i·SWAP_{ab} on the two spin modes, not a free relabeling; inserting such a swap between reference pulses conjugates the neighboring reference pulse and generally changes the total unitary. For example, with a reference sequence U12(θ)U34(φ), routing that requires swapping spins 2 and 3 before the second pulse and swapping back afterward yields the physical sequence S23 U34(φ) S23 U12(θ) = U24(φ) U12(θ), which is not equal to U12(θ)U34(φ) unless the factors commute. The argument that "every reference pulse is applied to the correct pair of spins in the correct order" tracks only the spin labels on which the pulses act; it omits the unitary action of the inserted swaps themselves. The destination node enforcing the identity final permutation only makes the product of the inserted swaps alone equal to identity; it does not make the swaps commute with the reference pulses. Since every generated sequence is of this form, the correctness of the pulse library and all length comparisons in Sections IV and VI rest on an unproved and generally false assertion.
  2. [V] The experimental validation does not close the correctness gap and is not sufficient to certify the generated sequences. The reported truth-table overlaps are SPAM-uncorrected classical basis-state probability overlaps; for CX they are 79.4% and for iSWAP 81.2%, compared with an identity overlap of 87.9% (Section V). Basis-state truth tables are insensitive to relative phases and can give high overlap for unitaries different from the target (for example, a CZ gate has the same Z-basis truth table as the identity), so they cannot establish that a two-qubit unitary is the intended one. Given the proof gap in Section IIIB2, the experiment does not provide independent evidence that the swap-inserted sequences realize the claimed gates. A full process-tomography or randomized-benchmarking comparison, or at minimum a numerical check of the six-spin unitary of every generated sequence, would be needed.
minor comments (4)
  1. [IVA] The acknowledged dependence of the reported "optimal" lengths on the chosen all-to-all reference sequence (e.g., the missed 22-pulse linear CX) should be stated in the abstract or conclusions, since the abstract's "up to 43% reduction" is relative to that particular reference and not an intrinsic property of the connectivities.
  2. [IIIB1 / Figure 3] In the definition of edge weights, please state explicitly that each edge weight equals the number of inserted swap pulses after merging plus one for the reference pulse of the destination node; the current text says "new pulses" and the figure example is helpful but the general rule should be written out.
  3. [V] Please report the number of experimental shots and statistical uncertainties for the truth-table overlaps, and clarify how post-selection interacts with the quoted identity overlap of 87.9%.
  4. [VIC] In Eq. (2), the units and distribution conventions for δJ_{ij} and δϵ^z_i should be given explicitly; the text says δJ is unitless, but the sampling distribution is only described informally via σ=ΔJ.

Circularity Check

1 steps flagged · score 6.0 of 10

Section IIIB2's correctness proof equates 'any path correctly implements the desired operation' with the graph-path definition, omitting the unitary action of inserted π spin-swap pulses.

  1. self definitional [Section III B 2 (Correctness and optimality), first paragraph; graph construction in Section III B 1]
    "Therefore, because every reference pulse is applied to the correct pair of spins in the correct order and the initial and final configurations are guaranteed by the definition of the source and destination node, any path from the source node to the destination node correctly implements the desired operation."

    The asserted proof takes the path bookkeeping (reference pulses on the correct spin labels, in order, with spins returning to initial dots) as the definition of correctness. It never computes the unitary effect of the inserted angle-π exchange pulses. A π exchange is U_SWAP(j,k,π), a SWAP operator that does not generally commute with exchange pulses on other spin pairs; e.g., inserting S23 between reference pulses gives S23 U34(φ) S23 U12(θ)=U24(φ) U12(θ), not U12(θ) U34(φ). Restoring the final spin configuration makes the product of isolated swaps alone equal to identity, but does not make the interleaved swaps cancel.

full rationale

Apart from the correctness proof, the paper is largely self-contained: sequence lengths are outputs of a shortest-path optimization rather than fitted parameters, and the authors explicitly acknowledge that lengths depend on the chosen all-to-all reference sequence (e.g., the known 22-pulse linear CX is not found because of the reference choice). No load-bearing self-citation chain is present: the reference sequences come from external works [32,46,47], and Intel-authored citations concern hardware, not the pulse-generation theorem. The one circular step is the correctness claim in Sec. IIIB2, where the condition defining a valid path is identified with logical correctness without accounting for the unitary action of inserted π spin-swap pulses. This is a definitional reduction of the central claim (every generated sequence is valid), so it is partial circularity; the experimental truth-table measurements provide an independent but weaker check (Z-basis overlap, no SPAM correction, acknowledged as not a full unitary characterization). Score 6 reflects that the central proof reduces by construction, while the sequence-length results and simulations otherwise have independent content.

Assumptions & free parameters 2 free parameters · 4 assumptions · 0 invented entities

No new physical entities are introduced. The CXSWAP gate is a Clifford operation, not a new particle or force. The free parameters are the noise parameters chosen for the simulation. The main axioms are standard quantum mechanics, the correctness of prior reference sequences, and the unproven swap-insertion invariance assumption.

free parameters (2)
  • T2* (dephasing time) = 3 us and 10 us (swept)
    Chosen by hand for the noisy simulation in Section VIC; affects simulated gate infidelities and teraquop footprints.
  • delta J (exchange error) = 0.001, 0.01 (and 0.005 in some plots)
    Chosen by hand for the noisy simulation; affects simulated gate infidelities.
assumptions (4)
  • standard math The exchange-only qubit encoding in a decoherence-free subspace of three spins is valid.
    Invoked throughout, citing Refs. [33,34,47].
  • domain assumption The reference all-to-all pulse sequences for CX, CZ, iSWAP, LCCX, LCCZ are correct.
    Taken from Ref. [46] and Ref. [32], as described in Appendix A; if these are wrong, all generated sequences inherit the error.
  • ad hoc to paper Inserting physical spin-swap exchange pulses between reference pulses, with spins returned to original dots, preserves the logical two-qubit gate.
    This is the load-bearing assumption in Section IIIB2; it is asserted without proof and is not generally true for arbitrary exchange sequences.
  • domain assumption The noise model in Section VIC (quasi-static Zeeman and exchange noise, high-field limit) captures the dominant error mechanisms.
    Used to compute gate infidelities for the QEC case study; the authors note the results are not exact resource estimates.

how reviews work

0 comments
Cite this review

Pith. "Pith review of Short two-qubit pulse sequences for exchange-only spin qubits in 2D layouts." pith.science (2026). https://pith.science/paper/YMFJRAB3

@misc{pith2026241214918,
  author       = {Pith},
  title        = {Pith review of: Short two-qubit pulse sequences for exchange-only spin qubits in 2D layouts},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/YMFJRAB3}},
  note         = {Machine review of arXiv:2412.14918}
}
read the original abstract

Exchange-only (EO) spin qubits in quantum dots offer an expansive design landscape for architecting scalable device layouts. The study of two-EO-qubit operations, which involve six electrons in six quantum dots, has so far been limited to a small number of the possible configurations, and previous works lack analyses of design considerations and implications for quantum error correction. Using a simple and fast optimization method, we generate complete pulse sequences for CX, CZ, iSWAP, leakage-controlled CX, and leakage-controlled CZ two-qubit gates on 450 unique planar six-dot topologies and analyze differences in sequence length (up to 43\% reduction) across topology classes. In addition, we show that relaxing constraints on post-operation spin locations can yield further reductions in sequence length; conversely, constraining these locations in a particular way generates a CXSWAP operation with minimal additional cost over a standard CX. We integrate this pulse library into the Intel quantum stack and experimentally verify pulse sequences on a Tunnel Falls chip for different operations in a linear-connectivity device to confirm that they work as expected. Finally, we explore architectural implications of these results for quantum error correction. Our work guides hardware and software design choices for future implementations of scalable quantum dot architectures.

Figures

Figures reproduced from arXiv: 2412.14918 by the authors.

Figure 1
Figure 1. FIG. 1. A 16-pulse sequence implementing a CX gate on two [PITH_FULL_IMAGE:figures/full_fig_p002_1.png] view at source ↗
Figure 2
Figure 2. FIG. 2. (a) All permutation classes of dot topologies consid [PITH_FULL_IMAGE:figures/full_fig_p004_2.png] view at source ↗
Figure 3
Figure 3. FIG. 3. The optimization graph used to find a pulse sequence for a given dot configuration, described in Section [PITH_FULL_IMAGE:figures/full_fig_p005_3.png] view at source ↗
Figures from the paper (9 more)
Figure 4
Figure 4. Figure 4: FIG. 4. Optimized CX sequence lengths, grouped by permutation equivalence class. Within each class, blue line spreads from [PITH_FULL_IMAGE:figures/full_fig_p007_4.png]
Figure 5
Figure 5. Figure 5: FIG. 5. Optimized sequence lengths for five different two-qubit operations, for a selected set of permutation equivalence classes. [PITH_FULL_IMAGE:figures/full_fig_p007_5.png]
Figure 6
Figure 6. Figure 6: FIG. 6. CX and CXSWAP sequence lengths for selected permutation equivalence classes, with and without intraqubit spin [PITH_FULL_IMAGE:figures/full_fig_p007_6.png]
Figure 7
Figure 7. Figure 7: FIG. 7. Experimental truth-table validation of pulse sequences. (a) 12 quantum dot Tunnel Falls device. Dots P4,P5,P6 and [PITH_FULL_IMAGE:figures/full_fig_p009_7.png]
Figure 8
Figure 8. Figure 8: FIG. 8 [PITH_FULL_IMAGE:figures/full_fig_p010_8.png]
Figure 11
Figure 11. Figure 11: FIG. 11. Schedule length for one full QEC cycle of CX gates, [PITH_FULL_IMAGE:figures/full_fig_p011_11.png]
Figure 10
Figure 10. Figure 10: FIG. 10. Average pulse count per CX for QEC round on each [PITH_FULL_IMAGE:figures/full_fig_p011_10.png]
Figure 12
Figure 12. Figure 12: FIG. 12. Teraquop footprints for all four layouts, under different parallelism conditions and in different noise regimes. The [PITH_FULL_IMAGE:figures/full_fig_p012_12.png]
Figure 13
Figure 13. Figure 13: FIG. 13. All-to-all sequences used as reference sequences in the optimization algorithm. [PITH_FULL_IMAGE:figures/full_fig_p017_13.png]

Discussion (0). Continue with ORCID to comment.

Reference graph

Works this paper leans on

81 extracted references · 49 canonical work pages

  1. [1]

    un- blocked exchange pulses

    Formulating swap routing as a shortest path problem There are two important considerations when deter- mining which spin swaps to insert to map a sequence to a dot topology. First, two exchange pulses that act in succession on the same dot pair can bemerged into one pulse with rotation angle equal to the sum of the original two; in effect, on a hardware w...

    work page

  2. [2]

    We now explain why our method finds theopti- mal (shortest sequence length) such schedule

    Correctness and optimality The goal of the proposed optimization method is to schedule the pulses in the same order as they appear in the all-to-all sequence, but satisfying the connectiv- ity constraints between dots by inserting spin swaps as needed. We now explain why our method finds theopti- mal (shortest sequence length) such schedule. Each node lay...

    work page

  3. [3]

    Chamberland and E

    C. Chamberland and E. T. Campbell, Universal Quan- tum Computing with Twist-Free and Temporally En- coded Lattice Surgery, PRX Quantum3, 010331 (2022)

    work page 2022

  4. [4]

    This corresponds to a qubit-level SWAP operation in addition to the original reference operation

    CXSW AP Alternatively, we can set the mapping so that spins A1 and B1 are exchanged, A2 and B2 are exchanged, and A3 and B3 are exchanged. This corresponds to a qubit-level SWAP operation in addition to the original reference operation. Using this optimization graph, the resulting pulse sequences will yield CXSWAP operations instead of CX, potentially wit...

    work page

  5. [5]

    control” qubit of the CX and magenta the “target

    Relaxing spin location constraints Alternatively, instead of modifying the default spin lo- cation constraint in the final layer, we can relax the con- straint by allowingseveral possible spin permutations in the final layer. In the search graph, we add several ad- ditional destination nodes, each of which corresponds to a different final mapping of spins...

    work page

  6. [6]

    D.Litinski,AGameofSurfaceCodes: Large-ScaleQuan- tum Computing with Lattice Surgery, Quantum3, 128 (2019), arXiv:1808.02892 [cond-mat, physics:quant-ph]

    arXiv 2019

  7. [7]

    Gidney and M

    C. Gidney and M. Ekerå, How to factor 2048 bit RSA in- tegers in 8 hours using 20 million noisy qubits, Quantum 5, 433 (2021)

    2021

  8. [8]

    Ishihara, A

    L.M.K.Vandersypen, H.Bluhm, J.S.Clarke, A.S.Dzu- rak, R. Ishihara, A. Morello, D. J. Reilly, L. R. Schreiber, and M. Veldhorst, Interfacing spin qubits in quantum dots and donors—hot, dense, and coherent, npj Quan- tum Information3, 1 (2017)

    work page 2017

Show all 81 references
  1. [9]

    I. H. Kim, Y.-H. Liu, S. Pallister, W. Pol, S. Roberts, and E. Lee, Fault-tolerant resource estimate for quantum chemical simulations: Case study on Li-ion battery elec- trolyte molecules, Physical Review Research4, 023019 (2022)

    2022

  2. [10]

    M. E. Beverland, P. Murali, M. Troyer, K. M. Svore, T. Hoefler, V. Kliuchnikov, G. H. Low, M. Soeken, A. Sundaram, and A. Vaschillo, Assessing require- ments to scale to practical quantum advantage (2022), arXiv:2211.07629 [quant-ph]

    2022 arXiv

  3. [11]

    Leblond, C

    T. Leblond, C. Dean, G. Watkins, and R. Bennink, Real- istic Cost to Execute Practical Quantum Circuits using Direct Clifford+T Lattice Surgery Compilation, ACM Transactions on Quantum Computing5, 1 (2024)

    2024

  4. [12]

    Burkard, T

    G. Burkard, T. D. Ladd, A. Pan, J. M. Nichol, and J. R. Petta, Semiconductor spin qubits, Reviews of Modern Physics 95, 025003 (2023)

    2023

  5. [13]

    Loss and D

    D. Loss and D. P. DiVincenzo, Quantum computation with quantum dots, Physical Review A57, 120 (1998)

    1998

  6. [14]

    Petit, H

    L. Petit, H. G. J. Eenink, M. Russ, W. I. L. Lawrie, N. W. Hendrickx, S. G. J. Philips, J. S. Clarke, L. M. K. Vandersypen, and M. Veldhorst, Universal quantum logic in hot silicon qubits, Nature580, 355 (2020)

    2020

  7. [15]

    C. H. Yang, R. C. C. Leon, J. C. C. Hwang, A. Saraiva, T. Tanttu, W. Huang, J. Camirand Lemyre, K. W. Chan, K. Y. Tan, F. E. Hudson, K. M. Itoh, A. Morello, M. Pioro-Ladrière, A. Laucht, and A. S. Dzurak, Oper- ation of a silicon quantum processor unit cell above one kelvin, N...

    2020

  8. [16]

    L. C. Camenzind, S. Geyer, A. Fuhrer, R. J. Warbur- ton, D. M. Zumbühl, and A. V. Kuhlmann, A hole spin qubit in a fin field-effect transistor above 4 kelvin, Nature Electronics 5, 178 (2022)

    2022

  9. [17]

    J. Y. Huang, R. Y. Su, W. H. Lim, M. Feng, B. van Straaten, B. Severin, W. Gilbert, N. Dumoulin Stuyck, T. Tanttu, S. Serrano, J. D. Cifuentes, I. Hansen, A. E. Seedhouse, E. Vahapoglu, R. C. C. Leon, N. V. Abrosi- mov, H.-J. Pohl, M. L. W. Thewalt, F. E. Hudson, C. C. Escott,...

    2024

  10. [18]

    H. C. George, M. T. Mądzik, E. M. Henry, A. J. Wag- ner, M. M. Islam, F. Borjans, E. J. Connors, J. Corrigan, M. Curry, M. K. Harper, D. Keith, L. Lampert, F. Luthi, F.A.Mohiyaddin, S.Murcia, R.Nair, R.Nahm, A.Neth- wewala, S. Neyens, R. D. Raharjo, C. Rogan, R. Savyt- skyy, T...

    2024 arXiv

  11. [19]

    Maurand, X

    R. Maurand, X. Jehl, D. Kotekar-Patil, A. Corna, H. Bo- huslavskyi, R. Laviéville, L. Hutin, S. Barraud, M. Vinet, M. Sanquer, and S. De Franceschi, A CMOS silicon spin qubit, Nature Communications7, 13575 (2016)

    2016

  12. [20]

    Veldhorst, H

    M. Veldhorst, H. G. J. Eenink, C. H. Yang, and A. S. Dzurak, Silicon CMOS architecture for a spin-based quantum computer, Nature Communications 8, 1766 (2017)

    2017

  13. [21]

    A. M. J. Zwerver, T. Krähenmann, T. F. Watson, L. Lampert, H. C. George, R. Pillarisetty, S. A. Bojarski, P. Amin, S. V. Amitonov, J. M. Boter, R. Caudillo, D. Correas-Serrano, J. P. Dehollain, G. Droulers, E. M. Henry, R. Kotlyar, M. Lodari, F. Lüthi, D. J. Michalak, B. K. Mu...

    2022

  14. [22]

    Neyens, O

    S. Neyens, O. K. Zietz, T. F. Watson, F. Luthi, A. Neth- wewala, H. C. George, E. Henry, M. Islam, A. J. Wag- ner, F. Borjans, E. J. Connors, J. Corrigan, M. J. Curry, D. Keith, R. Kotlyar, L. F. Lampert, M. T. Mądzik, K. Millard, F. A. Mohiyaddin, S. Pellerano, R. Pil- larise...

    2024

  15. [23]

    Zheng, N

    G. Zheng, N. Samkharadze, M. L. Noordam, N. Kalhor, D. Brousse, A. Sammak, G. Scappucci, and L. M. K. Vandersypen, Rapid gate-based spin read-out in silicon using an on-chip resonator, Nature Nanotechnology14, 742 (2019)

    2019

  16. [24]

    Veldhorst, J

    M. Veldhorst, J. C. C. Hwang, C. H. Yang, A. W. Leen- stra, B. de Ronde, J. P. Dehollain, J. T. Muhonen, F. E. Hudson, K. M. Itoh, A. Morello, and A. S. Dzurak, An addressable quantum dot qubit with fault-tolerant control-fidelity, Nature Nanotechnology9, 981 (2014)

    2014

  17. [25]

    Yoneda, K

    J. Yoneda, K. Takeda, T. Otsuka, T. Nakajima, M. R. Delbecq, G. Allison, T. Honda, T. Kodera, S. Oda, Y. Hoshi, N. Usami, K. M. Itoh, and S. Tarucha, A quantum-dot spin qubit with coherence limited by charge noise and fidelity higher than 99.9%, Nature Nanotech- nology 13, 102 (2018)

    2018

  18. [26]

    A. West, B. Hensen, A. Jouan, T. Tanttu, C.-H. Yang, A. Rossi, M. F. Gonzalez-Zalba, F. Hudson, A. Morello, D. J. Reilly, and A. S. Dzurak, Gate-based single-shot readout of spins in silicon, Nature Nanotechnology14, 437 (2019)

    2019

  19. [27]

    Urdampilleta, D

    M. Urdampilleta, D. J. Niegemann, E. Chanrion, B. Jadot, C. Spence, P.-A. Mortemousque, C. Bäuerle, L. Hutin, B. Bertrand, S. Barraud, R. Maurand, M. San- quer, X. Jehl, S. De Franceschi, M. Vinet, and T. Me- unier, Gate-based high fidelity spin readout in a CMOS device, Natur...

    2019

  20. [28]

    M. T. Mądzik, S. Asaad, A. Youssry, B. Joecker, K. M. Rudinger, E. Nielsen, K. C. Young, T. J. Proctor, A. D. Baczewski, A. Laucht, V. Schmitt, F. E. Hudson, K. M. Itoh, A. M. Jakob, B. C. Johnson, D. N. Jamieson, A. S. Dzurak, C. Ferrie, R. Blume-Kohout, and A. Morello, Preci...

    2022

  21. [29]

    Scappucci, and S

    A.Noiri, K.Takeda, T.Nakajima, T.Kobayashi, A.Sam- mak, G. Scappucci, and S. Tarucha, Fast universal quan- tum gate above the fault-tolerance threshold in silicon, Nature 601, 338 (2022)

    2022

  22. [30]

    X. Xue, M. Russ, N. Samkharadze, B. Undseth, A. Sam- mak, G. Scappucci, and L. M. K. Vandersypen, Quantum logic with spin qubits crossing the surface code threshold, Nature 601, 343 (2022)

    2022

  23. [31]

    A. R. Mills, C. R. Guinn, M. J. Gullans, A. J. Sigillito, M. M. Feldman, E. Nielsen, and J. R. Petta, Two-qubit silicon quantum processor with operation fidelity exceed- ing 99%, Science Advances8, eabn5130 (2022)

    2022

  24. [32]

    J. Z. Blumoff, A. S. Pan, T. E. Keating, R. W. Andrews, D. W. Barnes, T. L. Brecht, E. T. Croke, L. E. Euliss, J. A. Fast, C. A. Jackson, A. M. Jones, J. Kerckhoff, R. K. Lanza, K. Raach, B. J. Thomas, R. Velunta, A. J. Weinstein, T. D. Ladd, K. Eng, M. G. Borselli, A. T. Hunt...

    2022

  25. [33]

    D. P. DiVincenzo, D. Bacon, J. Kempe, G. Burkard, and K. B. Whaley, Universal quantum computation with the exchange interaction, Nature408, 339 (2000)

    2000

  26. [34]

    Steinacker, N

    P. Steinacker, N. D. Stuyck, W. H. Lim, T. Tanttu, M. Feng, A. Nick, S. Serrano, M. Candido, J. D. Ci- fuentes, F. E. Hudson, K. W. Chan, S. Kubicek, J. Jus- sot, Y. Canvel, S. Beyne, Y. Shimura, R. Loo, C. God- frin, B. Raes, S. Baudot, D. Wan, A. Laucht, C. H. Yang, A. Sarai...

    2024 arXiv

  27. [35]

    Tanttu, W

    T. Tanttu, W. H. Lim, J. Y. Huang, N. Dumoulin Stuyck, W. Gilbert, R. Y. Su, M. Feng, J. D. Cifuentes, A. E. Seedhouse, S. K. Seritan, C. I. Ostrove, K. M. Rudinger, R. C. C. Leon, W. Huang, C. C. Escott, K. M. Itoh, N. V. Abrosimov, H.-J. Pohl, M. L. W. Thewalt, F. E. Hudson,...

    2024

  28. [36]

    S. G. J. Philips, M. T. Mądzik, S. V. Amitonov, S. L. de Snoo, M. Russ, N. Kalhor, C. Volk, W. I. L. Lawrie, D. Brousse, L. Tryputen, B. P. Wuetz, A. Sammak, M. Veldhorst, G. Scappucci, and L. M. K. Vandersypen, Universal control of a six-qubit quantum processor in sil- icon, ...

    2022

  29. [37]

    A. J. Weinstein, M. D. Reed, A. M. Jones, R. W. An- drews, D. Barnes, J. Z. Blumoff, L. E. Euliss, K. Eng, B. H. Fong, S. D. Ha, D. R. Hulbert, C. A. C. Jack- son, M. Jura, T. E. Keating, J. Kerckhoff, A. A. Kiselev, J. Matten, G. Sabbir, A. Smith, J. Wright, M. T. Rakher, T. ...

    2023

  30. [38]

    S. D. Ha, E. Acuna, K. Raach, Z. T. Bloom, T. L. Brecht, J. M. Chappell, M. D. Choi, J. E. Christensen, I. T. Counts, D. Daprano, J. P. Dodson, K. Eng, D. J. Fi- alkow, C. A. C. Garcia, W. Ha, T. R. B. Harris, n. hol- man, I. Khalaf, J. W. Matten, C. A. Peterson, C. E. Plesha,...

    2025 arXiv

  31. [39]

    Bacon, J

    D. Bacon, J. Kempe, D. A. Lidar, and K. B. Wha- ley, Universal Fault-Tolerant Quantum Computation on Decoherence-Free Subspaces, Physical Review Letters 85, 1758 (2000)

    2000

  32. [40]

    B. Sun, T. Brecht, B. H. Fong, M. Akmal, J. Z. Blumoff, T. A. Cain, F. W. Carter, D. H. Finestone, M. N. Fire- man, W. Ha, A. T. Hatke, R. M. Hickey, C. A. C. Jack- son, I. Jenkins, A. M. Jones, A. Pan, D. R. Ward, A. J. Weinstein, S. J. Whiteley, P. Williams, M. G. Borselli, ...

    2024

  33. [41]

    Borsoi, N

    F. Borsoi, N. W. Hendrickx, V. John, M. Meyer, S. Motz, F. van Riggelen, A. Sammak, S. L. de Snoo, G. Scap- pucci, and M. Veldhorst, Shared control of a 16 semicon- ductor quantum dot crossbar array, Nature Nanotechnol- ogy 19, 21 (2024). 15

    2024

  34. [42]

    K. Raach, Fabrication and characterization of multi-rail Si/SiGe exchange-only spin qubits in the SLEDGE ar- chitecture, in Bulletin of the American Physical Society (American Physical Society, 2024)

    2024

  35. [43]

    J. M. Boter, J. P. Dehollain, J. P. G. van Dijk, T. Hens- gens, R. Versluis, J. S. Clarke, M. Veldhorst, F. Sebas- tiano, and L. M. K. Vandersypen, A sparse spin qubit array with integrated control electronics, in2019 IEEE International Electron Devices Meeting (IEDM) (2019) p...

    2019

  36. [44]

    V. John, C. X. Yu, B. van Straaten, E. A. Rodríguez- Mena, M. Rodríguez, S. Oosterhout, L. E. A. Stehouwer, G. Scappucci, S. Bosco, M. Rimbach-Russ, Y.-M. Niquet, F. Borsoi, and M. Veldhorst, A two-dimensional 10-qubit array in germanium with robust and localised qubit con- tr...

    2025

  37. [45]

    quasi-Fredkin

    used a similar method to find CX pulse sequences for two nonlinear connectivities. Ref. [46] used a more efficient constrained search to generatelocally equivalent (correct up to single-qubit gates) pulse sequences for all- to-all connectivity and several constrained dot conne...

  38. [46]

    G. A. Oakes, V. N. Ciriano-Tejel, D. F. Wise, M. A. Fogarty, T. Lundberg, C. Lainé, S. Schaal, F. Martins, D. J. Ibberson, L. Hutin, B. Bertrand, N. Stelmashenko, J. W. A. Robinson, L. Ibberson, A. Hashim, I. Siddiqi, A. Lee, M. Vinet, C. G. Smith, J. J. L. Morton, and M. F. G...

    2023

  39. [47]

    R. Li, L. Petit, D. P. Franke, J. P. Dehollain, J. Helsen, M. Steudtner, N. K. Thomas, Z. R. Yoscovits, K. J. Singh, S. Wehner, L. M. K. Vandersypen, J. S. Clarke, and M. Veldhorst, A crossbar network for silicon quan- tum dot qubits, Science Advances4, eaar3960 (2018)

    2018

  40. [48]

    D. P. Franke, J. S. Clarke, L. M. K. Vandersypen, and M. Veldhorst, Rent’s rule and extensibility in quan- tum computing, Microprocessors and Microsystems67, 1 (2019)

    2019

  41. [49]

    X. Xue, B. Patra, J. P. G. van Dijk, N. Samkharadze, S. Subramanian, A. Corna, B. Paquelet Wuetz, C. Jeon, F. Sheikh, E. Juarez-Hernandez, B. P. Esparza, H. Ram- purawala, B. Carlton, S. Ravikumar, C. Nieva, S. Kim, H.-J. Lee, A. Sammak, G. Scappucci, M. Veldhorst, F. Sebastia...

    2021

  42. [50]

    Z. Shi, C. B. Simmons, J. R. Prance, J. K. Gamble, T. S. Koh, Y.-P. Shim, X. Hu, D. E. Savage, M. G. Lagally, M. A. Eriksson, M. Friesen, and S. N. Coppersmith, Fast HybridSiliconDouble-Quantum-DotQubit,PhysicalRe- view Letters108, 140503 (2012)

    2012

  43. [51]

    Sarma, Robust two-qubit gates for exchange-coupled qubits, Physical Review B89, 085314 (2014)

    F.Setiawan, H.-Y.Hui, J.P.Kestner, X.Wang,andS.D. Sarma, Robust two-qubit gates for exchange-coupled qubits, Physical Review B89, 085314 (2014)

    2014

  44. [52]

    B.H.FongandS.M.Wandzura,Universalquantumcom- putation and leakage reduction in the 3-qubit decoher- ence free subsystem, Quantum Information & Computa- tion 11, 1003 (2011)

    2011

  45. [53]

    R. W. Andrews, C. Jones, M. D. Reed, A. M. Jones, S. D. Ha, M.P.Jura, J.Kerckhoff, M.Levendorf, S.Meenehan, S. T. Merkel, A. Smith, B. Sun, A. J. Weinstein, M. T. Rakher, T. D. Ladd, and M. G. Borselli, Quantifying error and leakage in an encoded Si/SiGe triple-dot qubit, Natu...

    2019

  46. [54]

    J.Kempe, D.Bacon, D.A.Lidar,andK.B.Whaley,The- ory of decoherence-free fault-tolerant universal quantum computation, Physical Review A63, 042307 (2001)

    2001

  47. [55]

    Zeuch and N

    D. Zeuch and N. E. Bonesteel, Simple derivation of the Fong-Wandzura pulse sequence, Physical Review A93, 010303 (2016)

    2016

  48. [56]

    Zeuch and N

    D. Zeuch and N. E. Bonesteel, Efficient two-qubit pulse sequences beyond CNOT, Physical Review B102, 075311 (2020)

    2020

  49. [57]

    Knill, R

    E. Knill, R. Laflamme, and W. H. Zurek, Resilient Quan- tum Computation, Science279, 342 (1998)

    1998

  50. [58]

    A. Yu. Kitaev, Fault-tolerant quantum computation by anyons, Annals of Physics303, 2 (2003)

    2003

  51. [59]

    Aharonov and M

    D. Aharonov and M. Ben-Or, Fault-Tolerant Quantum Computation with Constant Error Rate, SIAM Journal on Computing38, 1207 (2008)

    2008

  52. [60]

    A. Y. Kitaev, Quantum computations: Algorithms and error correction, Russian Mathematical Surveys52, 1191 (1997)

    1997

  53. [61]

    Dennis, A

    E. Dennis, A. Kitaev, A. Landahl, and J. Preskill, Topological quantum memory, Journal of Mathematical Physics 43, 4452 (2002)

    2002

  54. [62]

    J. P. Bonilla Ataides, D. K. Tuckett, S. D. Bartlett, S. T. Flammia, and B. J. Brown, The XZZX surface code, Na- ture Communications12, 2172 (2021)

    2021

  55. [63]

    McEwen, D

    M. McEwen, D. Bacon, and C. Gidney, Relaxing Hard- wareRequirementsforSurfaceCodeCircuitsusingTime- dynamics, Quantum7, 1172 (2023)

    2023

  56. [64]

    Z. Cai, A. Siegel, and S. Benjamin, Looped Pipelines En- abling Effective 3D Qubit Lattices in a Strictly 2D De- vice, PRX Quantum4, 020345 (2023)

    2023

  57. [65]

    Strikis and L

    A. Strikis and L. Berent, Quantum Low-Density Parity- Check Codes for Modular Architectures, PRX Quantum 4, 020321 (2023)

    2023

  58. [66]

    Siegel, A

    A. Siegel, A. Strikis, and M. Fogarty, Towards early fault tolerance on a 2xN array of qubits equipped with shut- tling (2024), arXiv:2402.12599 [quant-ph]

    2024 arXiv

  59. [67]

    Hetényi and J

    B. Hetényi and J. R. Wootton, Tailoring quantum error correction to spin qubits, Physical Review A109, 032433 (2024)

    2024

  60. [68]

    G. Li, Y. Ding, and Y. Xie, Tackling the Qubit Mapping Problem for NISQ-Era Quantum Devices, inProceedings of the Twenty-Fourth International Conference on Ar- chitectural Support for Programming Languages and Op- erating Systems (ACM, Providence RI USA, 2019) pp. 1001–1014

    2019

  61. [69]

    Nannicini, L

    G. Nannicini, L. S. Bishop, O. Gunluk, and P. Jurcevic, Optimal qubit assignment and routing via integer pro- gramming (2021), arXiv:2106.06446

    2021 arXiv

  62. [70]

    M. J. Reagor, T. C. Bohdanowicz, D. R. Perez, E. A. Sete, and W. J. Zeng, Hardware optimized parity check gates for superconducting surface codes (2022), arXiv:2211.06382 [quant-ph]

    2022 arXiv

  63. [71]

    Chao and B

    R. Chao and B. W. Reichardt, Flag Fault-Tolerant Error Correction for any Stabilizer Code, PRX Quantum 1, 010302 (2020)

    2020

  64. [72]

    Short two-qubit pulse sequences for exchange-only spin qubits 16 in 2D layouts

    J. Chadwick, G. G. Guerreschi, F. Lüthi, M. Madzik, F. Mohiyaddin, P. Prabhu, A. Schmitz, A. Litteken, S. Premaratne, N. Bishop, and J. Clarke, Data for "Short two-qubit pulse sequences for exchange-only spin qubits 16 in 2D layouts" (2024)

    2024

  65. [73]

    Y. He, S. K. Gorman, D. Keith, L. Kranz, J. G. Keizer, and M. Y. Simmons, A two-qubit gate between phospho- rus donor electrons in silicon, Nature571, 371 (2019)

    2019

  66. [74]

    A. J. Sigillito, M. J. Gullans, L. F. Edge, M. Borselli, and J. R. Petta, Coherent transfer of quantum information in a silicon double quantum dot using resonant SWAP gates, npj Quantum Information5, 1 (2019)

    2019

  67. [75]

    Gidney, Stim: A fast stabilizer circuit simulator, Quantum 5, 497 (2021), arXiv:2103.02202 [quant-ph]

    C. Gidney, Stim: A fast stabilizer circuit simulator, Quantum 5, 497 (2021), arXiv:2103.02202 [quant-ph]

    2021 arXiv

  68. [76]

    Acharya, I

    Google Quantum AI, R. Acharya, I. Aleiner, R. Allen, T. I. Andersen, M. Ansmann, F. Arute, K. Arya, A. Asfaw, J. Atalaya, R. Babbush, D. Bacon, J. C. Bardin, J. Basso, A. Bengtsson, S. Boixo, G. Bortoli, A. Bourassa, J. Bovaird, L. Brill, M. Broughton, B. B. Buckley, D. A. Bue...

    2023

  69. [77]

    T. A. Baart, M. Shafiei, T. Fujita, C. Reichl, W. Wegscheider, and L. M. K. Vandersypen, Single-spin CCD, Nature Nanotechnology11, 330 (2016)

    2016

  70. [78]

    A. R. Mills, D. M. Zajac, M. J. Gullans, F. J. Schupp, T. M. Hazard, and J. R. Petta, Shuttling a single charge across a one-dimensional array of silicon quantum dots, Nature Communications10, 1063 (2019)

    2019

  71. [79]

    C. Volk, A. M. J. Zwerver, U. Mukhopadhyay, P. T. Een- debak, C. J. van Diepen, J. P. Dehollain, T. Hensgens, T. Fujita, C. Reichl, W. Wegscheider, and L. M. K. Van- dersypen, Loading a quantum-dot based “Qubyte” regis- ter, npj Quantum Information5, 1 (2019)

    2019

  72. [80]

    S. Che, S. W. Oh, H. Qin, Y. Liu, A. Sigillito, and G. Li, Fast Virtual Gate Extraction For Silicon Quantum Dot Devices (2024), arXiv:2409.15181 [cond-mat]

    2024 arXiv

  73. [81]

    Re- laxing Hardware Requirements for Surface Code Circuits using Time-dynamics

    M. McEwen, D. Bacon, and C. Gidney, Data for "Re- laxing Hardware Requirements for Surface Code Circuits using Time-dynamics" (2023). 17 FIG. 13. All-to-all sequences used as reference sequences in the optimization algorithm. Appendix A: All-to-all pulse sequences In Figure 13...

    2023

Pith tools

Reviewed August 11, 2026 · model on record in the stance chip above.