Paper Citation Record · LEDGER

LLM4DV: Using Large Language Models for Hardware Test Stimuli Generation

As of 20 August 2026, this Paper Citation Record lists 0 of 0 outbound references and 6 inbound Pith citation observations for arXiv:2310.04535.

A citation records a reference. It does not transfer a finding from one paper to another.

pith.paper-citation-record.v1
2310.04535 v2

Coverage vector

measured 0 of 0 reference resolution

Typed states for the displayed outbound observations.

Source: paper_references, paper_reference_links

measured 6 of 6 standing notices

One-hop event checks from named stored sources.

Source: scholarly_work_events, retraction_status_cache, observed 2026-08-20T06:33:59.587034+00:00

measured 6 of 6 inbound itemization

Pith citing papers itemized under the disclosed page cap.

Source: paper_references, paper_reference_links, observed 2026-08-15T19:59:24.447859Z

measured 0 of 1 external citation measurements

A source-named dated measurement, never combined with another source.

Source: pith, observed 2026-08-05T18:37:10.265891Z

Reference resolution

0 of 0 outbound references displayed

verified exact0
verified fuzzy0
unresolved0
parse uncertain0
malformed identifier0
metadata mismatch0

External citation measurements

No source-named external measurement is stored.

Outbound references

No outbound reference observations are available for this paper version.

Pith citing papers

Observation 728abd0e-68fb-4128-bc25-009cb8baea82 · inbound

Security Properties for Open-Source Hardware Designs cites this paper.

Security Properties for Open-Source Hardware Designs LLM4DV: Using Large Language Models for Hardware Test Stimuli Generation

Reference 70

Resolution: unresolved; no resolver link, observed 2026-08-11T17:39:50.058348Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 91b7475d-605b-48fa-88ea-a52c599c26dd · inbound

Comprehensive Verilog Design Problems: A Next-Generation Benchmark Dataset for Evaluating Large Language Models and Agents on RTL Design and Verification cites this paper.

Comprehensive Verilog Design Problems: A Next-Generation Benchmark Dataset for Evaluating Large Language Models and Agents on RTL Design and Verification LLM4DV: Using Large Language Models for Hardware Test Stimuli Generation

Reference 10

Resolution: unresolved; no resolver link, observed 2026-08-15T19:59:24.447859Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation db8a545c-3605-4b79-95b9-71430392503b · inbound

SV-LLM: An Agentic Approach for SoC Security Verification using Large Language Models cites this paper.

SV-LLM: An Agentic Approach for SoC Security Verification using Large Language Models LLM4DV: Using Large Language Models for Hardware Test Stimuli Generation

Reference 73

Resolution: unresolved; no resolver link, observed 2026-08-06T22:55:09.356710Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 532e0e8f-0575-4d12-aef8-10331e0c2d13 · inbound

AnalogTester: A Large Language Model-Based Framework for Automatic Testbench Generation in Analog Circuit Design cites this paper.

AnalogTester: A Large Language Model-Based Framework for Automatic Testbench Generation in Analog Circuit Design LLM4DV: Using Large Language Models for Hardware Test Stimuli Generation

Reference 9

Resolution: unresolved; no resolver link, observed 2026-08-06T17:48:52.389401Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 2d72072e-4d8f-4835-8b7e-93e9bc60ead6 · inbound

VerilogDB: The Largest, Highest-Quality Dataset with a Preprocessing Framework for LLM-based RTL Generation cites this paper.

VerilogDB: The Largest, Highest-Quality Dataset with a Preprocessing Framework for LLM-based RTL Generation LLM4DV: Using Large Language Models for Hardware Test Stimuli Generation

Reference 55

Resolution: unresolved; no resolver link, observed 2026-08-06T18:54:08.228759Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 0c1e3549-c97d-4a1f-b0e7-bd488ccd5590 · inbound

Wit-HW: Bug Localization in Hardware Design Code via Witness Test Case Generation cites this paper.

Wit-HW: Bug Localization in Hardware Design Code via Witness Test Case Generation LLM4DV: Using Large Language Models for Hardware Test Stimuli Generation

Reference 36

Resolution: verified exact; local_arxiv, observed 2026-08-05T18:37:10.273127Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-20T06:33:59.587034+00:00.