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Construction of Boolean Logic Gates Using QFT-Based Adder Architecture

T0 review · 2 major / 4 minor · reviewed 2026-08-16 · deepseek-v4-flash

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Pith's one-line read This paper presents a QFT-based adder circuit that implements AND, OR, XOR, NOR, and NAND reversibly, with an $N$-input NAND costing $N+\log_2 N$ qubits.

desk verdict The 2-input QFT-adder gates are correct but known; the N-input scaling claim is false as stated. read the letter →

arxiv 2504.17090 v1 pith:YLHBR7VO submitted 2025-04-23 quant-ph

Ayda Kaltehei , Murat Kurt , Azmi Gençten , Selçuk Çakmak This is my paper · ORCID
classification quant-ph
keywords quantumFouriertransformQFT-basedadderreversiblelogicgatesNANDgateBooleanincircuitsDeMorgan'slawshalf-adderqubitresourcereduction
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

The paper claims that a one-bit, two-input QFT-based adder behaves like a reversible half-adder: its carry-out qubit evaluates the AND of the inputs and its sum qubit evaluates the XOR. From that single circuit, AND, NAND, OR, NOR, and XOR can be produced by adding only NOT gates before or after the adder, or a SWAP, with no change to the adder core. The central resource claim is that extracting the carry-out bit makes an $N$-input NAND gate cost $N+\log_2 N$ qubits, against $2N-1$ qubits for a Toffoli-based construction. A sympathetic reader would care because, if correct, the same arithmetic block that performs addition also supplies a complete set of Boolean primitives with a qubit count that scales favorably for large input sizes.

What carries the argument

The central object is the QFT-based adder as a reversible half-adder: input qubits $|q_0\rangle$ and $|q_1\rangle$ plus ancilla $|A\rangle$ initialized to $|0\rangle$, with QFT, conditional phase gates, and inverse QFT, so that measuring $|A\rangle$ gives the carry bit and measuring $|q_0\rangle$ gives the sum bit. This one circuit carries the entire argument because every logic gate in the paper is the same adder with fixed pre- or post-processing: the carry channel already computes AND, the sum channel already computes XOR, and the NOT gates implement De Morgan's identities that convert AND into OR and NAND into NOR.

What would settle it

On a statevector simulator, build the $N=3$ QFT-adder circuit exactly as specified and feed it all eight computational basis states; if the measured ancilla does not equal the AND of the three data bits in every case, the carry-out-as-NAND construction and the $N+\log_2 N$ qubit count collapse.

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Extended reading notes

Core claim

The paper's central claim is that the QFT-based adder already contains the Boolean gates it appears to lack. Because the adder's ancillary qubit $|A\rangle$ carries the AND of the two data inputs and its first data qubit $|q_0\rangle$ carries their XOR, no new arithmetic structure is needed to realize logic: an X gate on the ancilla turns AND into NAND, X gates on both data inputs turn the carry into OR by De Morgan's law, the same two X gates without the post-processing X give NOR, and a SWAP between the ancilla and the first data qubit moves the XOR to the measured channel. The paper extends the two-input construction to $N$ inputs by reading the carry-out bit, obtaining an $N$-input NAND with $N+\log_2 N$ qubits.

Load-bearing premise

The entire gate set rests on the assumption, taken from prior QFT-adder work and checked only on a two-input composer truth table, that after the inverse transform the ancilla holds the AND (carry) and the first data qubit holds the XOR (sum); if that mapping is wrong for larger inputs, every constructed gate fails.

Editorial extensions

If this is right

  • All five basic Boolean functions are reachable from one fixed adder template by choosing which wires get an X gate or a SWAP.
  • An $N$-input NAND requires $N+\log_2 N$ qubits rather than the $2N-1$ qubits of a Toffoli-based construction, so the qubit advantage grows with input count.
  • The same circuit can serve as an arithmetic unit and a logic unit, since addition and Boolean operations share the same QFT-adder core.
  • Because the output is read from a single ancilla after a fixed set of single-qubit or SWAP gates, the method gives a uniform measurement pattern for all five gates.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • Beyond the paper, the same carry/sum extraction could be applied to a QFT-based full adder to produce multi-bit AND/XOR masks, letting the logic block scale beyond single-bit operations without a separate gate set.
  • The paper's verification is limited to two-input truth tables; a natural check is to run the stated $N$-input NAND construction for $N=3$ and $N=4$ on a statevector simulator, where any mismatch between the measured ancilla and the $N$-input AND would falsify the resource claim.
  • If the resource count survives that check, the practical trade-off worth measuring is circuit depth and gate count versus qubit savings, since QFT-based adders use more elementary gates for small inputs.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

2 major / 4 minor

Summary. The paper presents a quantum Fourier transform (QFT)-based adder circuit used as a half-adder, and it implements two-input reversible Boolean gates (AND, NAND, OR, NOR, XOR) by applying pre- and post-processing gates around that adder. The truth tables for all five two-input gates are verified on the IBM Quantum Composer. The paper further claims that an N-input NAND gate can be obtained by extracting the carry-out bit of a one-bit N-input QFT-based adder, with a total qubit count of N + log2 N, and that this scaling offers a resource advantage over Toffoli-based designs.

Significance. The two-input gate constructions are correct: the carry output of the half-adder yields AND, the sum output yields XOR, and the De Morgan based pre- and post-processing for OR and NOR is sound and matches the expected truth tables for all four input states. The IBM Quantum Composer verification provides concrete evidence for these gates. However, the paper's advertised significance rests on the N-input scaling claim, which is false as stated for general N: the carry-out of the sum of N one-bit inputs does not equal the AND of all inputs except in special cases. This undermines the claimed qubit-count advantage over Toffoli-based designs, which the abstract, Section 3, and the Conclusion all present as the main motivation. The contribution is therefore reduced to a straightforward application of the known QFT half-adder to two-input gates.

major comments (2)
  1. [Section 3 (Results and Discussion), paragraph beginning 'Quantum equivalents of classical logic gates have also been…] The claim that extracting the carry-out bit from a one-bit N-input QFT-based adder implements N-input NAND is incorrect for general N. For N=3 with input state |110> (i.e., q0=1, q1=1, q2=0), the integer sum is 2, so the most significant bit of the sum (carry-out) is 1; inverting it gives 0, whereas NAND(1,1,0)=1. The carry-out of the sum of N one-bit inputs indicates whether the sum has reached a power-of-two threshold, not whether all N inputs are 1. The equality holds only in special cases (e.g., N=2, or N=2^k with an appropriately defined carry), and the paper states no such restriction. Since the N+log2 N qubit claim and the resource-efficiency advantage over Toffoli designs rest on this construction, this is a load-bearing error.
  2. [Section 3 (Results and Discussion), same paragraph; also Section 4 (Conclusion)] The paper does not provide a definition or circuit diagram for the 'one-bit (n=1) N-input QFT-based adder', nor does it prove the carry-out mapping claimed for NAND. The N+log2 N qubit count is asserted by citing the authors' own reference [13], which is listed without volume, page, or year and is not accessible to the reader. Because this scaling claim is the central motivation of the manuscript, the construction should be fully specified and the carry-AND relation either derived or explicitly restricted to the cases where it actually holds.
minor comments (4)
  1. [Section 2.C] The sentence 'the measurement is applied on the |A⟩ qubit gives the Carry-bit encoded in c1 bit' is ungrammatical and should be revised for clarity.
  2. [Introduction and Conclusion] The claim that the approach 'reduces noise arising from interference between quantum channels' is not supported by any data or reference in the manuscript; it should be substantiated or removed.
  3. [References] Reference [13] is incomplete; full bibliographic details (volume, page, year, DOI if available) should be provided.
  4. [Section 3, N-input paragraph] The formula N + log2 N is used without stating that N must be a power of two; for non-integer log2 N the count is ill-defined, so the intended domain of the claim should be made explicit if it is retained.

Circularity Check

1 steps flagged · score 4.0 of 10

N-input NAND resource scaling is supported only by the authors' own prior work; the 2-input gate constructions are otherwise self-contained.

  1. self citation load bearing [Sec. 3 (Results and Discussion), paragraph on N-input NAND and qubit reduction, page 4]
    "By extracting the carry-out bit from a one-bit ( n = 1) N-input QFT-based adder circuit, the NAND operation can be efficiently achieved. This method reduces the total qubit requirement to N + log2 N, providing a scalable and resource-efficient solution for implementing multi-input NAND logic in quantum circuits [13]."

    The paper's main scalability advantage -- N+log2 N qubits for N-input NAND via the carry-out bit -- is nowhere derived in this manuscript; the only support is Ref. [13], whose authors overlap with the present paper. The 2-input gate implementations in Secs. 3A-3E cannot establish the N-input behavior, so the N-input claim reduces to an unverified self-citation rather than to an independent derivation. The premise that the carry-out of a one-bit N-input adder realizes NAND is likewise imported from [13] without proof or counting argument.

full rationale

The 2-input AND, NAND, OR, NOR, and XOR circuits are self-contained constructions built from the standard QFT-adder half-adder behavior (carry = AND, sum = XOR), with pre/post processing by X and SWAP gates implementing De Morgan equivalences. These are verified by direct truth tables and do not rely on any fitted parameter or on a circular definition. The only circularity found is the load-bearing N-input scaling claim: the advertised reduction to N+log2 N qubits and the identification of the carry-out with NAND are asserted with a citation to the authors' own prior work, not derived in this paper. I do not count the possible mathematical incorrectness of carry-out = NAND for N>2 as circularity; that is a correctness risk. Because the central 2-input demonstrations stand independently, the score is 4 rather than higher.

Assumptions & free parameters 0 free parameters · 3 assumptions · 0 invented entities

The paper introduces no new free parameters or entities. Its central derivation depends on the half-adder behavior of a QFT adder (from external prior work) and the N-input scaling of that adder (from the authors' own prior work). The latter is the main unexamined assumption.

assumptions (3)
  • domain assumption The QFT-based adder computes a half-adder: the ancilla |A> measures the carry (AND) and the first data qubit |q0> measures the sum (XOR).
    Assumed in Sec. II.C and used throughout Sec. III; the paper does not analytically derive this mapping here and verifies it only by IBM Quantum Composer truth tables.
  • ad hoc to paper An N-input QFT-adder-based NAND needs N + log2 N qubits and its carry-out gives the NAND of all inputs.
    Introduced in Sec. III via citation to the authors' own prior work [13]; no circuit, derivation, or N>2 data is provided in this paper. This is the basis for the claimed scaling advantage.
  • standard math De Morgan's laws allow OR and NOR to be obtained by negating inputs and/or output of an AND gate.
    Invoked in Sec. III C and D to derive OR and NOR circuits; standard Boolean algebra, though the prose states it incorrectly ('X ANDY = X OR Y').

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Cite this review

Pith. "Pith review of Construction of Boolean Logic Gates Using QFT-Based Adder Architecture." pith.science (2026). https://pith.science/paper/YLHBR7VO

@misc{pith2026250417090,
  author       = {Pith},
  title        = {Pith review of: Construction of Boolean Logic Gates Using QFT-Based Adder Architecture},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/YLHBR7VO}},
  note         = {Machine review of arXiv:2504.17090}
}
read the original abstract

In this study, we construct the quantum reversible counterparts of the logical AND, OR, XOR, NOR, and NAND gates. We utilize a quantum Fourier transform (QFT)-based adder circuit that replicates the functionality of a digital half-adder, which computes the sum and carry of two input bits using XOR and AND gates, respectively. To realize different logic gate operations, we apply pre- and post-processing to the QFT-adder using quantum gates, leveraging Boolean algebra properties to enable conversions between various logical functions. Although the number of elementary quantum logic gates increases for a small number of inputs-making the approach appear inefficient at first glance-the overall required qubit count is reduced compared to non-QFT-based designs as the number of inputs increases.

Figures

Figures reproduced from arXiv: 2504.17090 by the authors.

Figure 1
Figure 1. Two-qubit quantum Fourier transform circuit [PITH_FULL_IMAGE:figures/full_fig_p002_1.png] view at source ↗
Figure 2
Figure 2. Two-qubit inverse quantum Fourier transform circuit. The Figs. 1 and 2 show two-input QFT and IQFT cir￾cuits, respectively. In [PITH_FULL_IMAGE:figures/full_fig_p002_2.png] view at source ↗
Figure 4
Figure 4. The CP(θk ) gates for one bit two-input QFT￾adder. are reversible—unlike their classical counterparts. To im￾plement these logic functions with quantum gates, we refer to the classical half-adder circuit shown in [PITH_FULL_IMAGE:figures/full_fig_p003_4.png] view at source ↗
Figures from the paper (7 more)
Figure 5
Figure 5. Figure 5: The classical half-adder, where A and B repre￾sent the two input bits, and the Sum and Carry outputs hold the result of the addition operation. The generic form of the quantum circuit for the QFT￾based adder operation is presented in Sec. C. We apply pre- and post-proc…
Figure 3
Figure 3. Figure 3: The quantum circuit diagram of the one-bit two input QFT-based adder. The carry bit and sum bit, which hold the result of the addition operation, are stored in c1 and c0, respectively. 3. RESULTS AND DISCUSSION In this section, we construct the AND, NAND, OR, NOR, and …
Figure 8
Figure 8. Figure 8: The QFT-adder based two-input NAND gate. This circuit was tested for all input states, |00⟩,|01⟩, |10⟩ and |11⟩, and the results were verified as given in [PITH_FULL_IMAGE:figures/full_fig_p004_8.png]
Figure 7
Figure 7. Figure 7: The QFT-adder based two-input AND gate. The QFT-adder based AND circuit was tested on IBM quantum composer for all input states, |00⟩,|01⟩, |10⟩ and |11⟩ (in the |q0q1⟩ form), and the results were verified as given in [PITH_FULL_IMAGE:figures/full_fig_p004_7.png]
Figure 9
Figure 9. Figure 9: The QFT-adder based two-input OR gate [PITH_FULL_IMAGE:figures/full_fig_p005_9.png]
Figure 11
Figure 11. Figure 11: The QFT-adder based logic XOR gate. input states, |00⟩,|01⟩, |10⟩ and |11⟩, on IBM quantum composer [PITH_FULL_IMAGE:figures/full_fig_p005_11.png]
Figure 10
Figure 10. Figure 10: The QFT-adder based two-input NOR gate. The all input states (|00⟩,|01⟩, |10⟩ and |11⟩) were tested in IBM quantum composer and the results were verified that represented in [PITH_FULL_IMAGE:figures/full_fig_p005_10.png]

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