Typed states for the displayed outbound observations.
Source: paper_references, paper_reference_links
Paper Citation Record · LEDGER
Using LLMs to Facilitate Formal Verification of RTL
As of 23 August 2026, this Paper Citation Record lists 0 of 0 outbound references and 14 inbound Pith citation observations for arXiv:2309.09437.
A citation records a reference. It does not transfer a finding from one paper to another.
Coverage vector
One-hop event checks from named stored sources.
Source: scholarly_work_events, retraction_status_cache, observed 2026-08-23T06:30:58.430688+00:00
Pith citing papers itemized under the disclosed page cap.
Source: paper_references, paper_reference_links, observed 2026-08-16T10:51:12.023579Z
A source-named dated measurement, never combined with another source.
Source: pith, observed 2026-07-09T10:56:11.275114Z
Reference resolution
0 of 0 outbound references displayed
- verified exact0
- verified fuzzy0
- unresolved0
- parse uncertain0
- malformed identifier0
- metadata mismatch0
External citation measurements
No source-named external measurement is stored.
Outbound references
No outbound reference observations are available for this paper version.
Pith citing papers
Observation b75996c4-9fed-4425-808d-2c65aa721fab · inbound
FLAG: Formal and LLM-assisted SVA Generation for Formal Specifications of On-Chip Communication Protocols cites this paper.
FLAG: Formal and LLM-assisted SVA Generation for Formal Specifications of On-Chip Communication Protocols Using LLMs to Facilitate Formal Verification of RTL
Reference 46
- Resolution
- unresolved
- no resolver link, observed 2026-08-16T10:51:12.023579Z
Source-reported events for the cited work
Unavailable: canonical work link unavailable.
Observation c71d55c1-d45d-4605-b72f-6413dbf21a9f · inbound
AnalogTester: A Large Language Model-Based Framework for Automatic Testbench Generation in Analog Circuit Design cites this paper.
AnalogTester: A Large Language Model-Based Framework for Automatic Testbench Generation in Analog Circuit Design Using LLMs to Facilitate Formal Verification of RTL
Reference 8
- Resolution
- unresolved
- no resolver link, observed 2026-08-06T17:48:52.352163Z
Source-reported events for the cited work
Unavailable: canonical work link unavailable.
Observation 25bbd721-6d0b-4379-b810-863631124e72 · inbound
SVAgent: AI Agent for Hardware Security Verification Assertion cites this paper.
SVAgent: AI Agent for Hardware Security Verification Assertion Using LLMs to Facilitate Formal Verification of RTL
Reference 44
- Resolution
- unresolved
- no resolver link, observed 2026-08-06T15:22:33.051614Z
Source-reported events for the cited work
Unavailable: canonical work link unavailable.
Observation 845a783f-10c2-42d6-8e14-7da68ed15ad7 · inbound
Large Language Models (LLMs) for Electronic Design Automation (EDA) cites this paper.
Large Language Models (LLMs) for Electronic Design Automation (EDA) Using LLMs to Facilitate Formal Verification of RTL
Reference 25
- Resolution
- unresolved
- no resolver link, observed 2026-08-05T15:17:26.633827Z
Source-reported events for the cited work
Unavailable: canonical work link unavailable.
Observation 9f1c2157-b4c4-491d-8047-702421d266da · inbound
Large Lemma Miners: Can LLMs do Induction Proofs for Hardware? cites this paper.
Large Lemma Miners: Can LLMs do Induction Proofs for Hardware? Using LLMs to Facilitate Formal Verification of RTL
Reference 27
- Resolution
- verified exact
- arxiv_id, observed 2026-05-18T01:35:36.360618Z
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-23T06:30:58.430688+00:00.
Observation 0e659252-30a5-4b29-955d-b89439d500f8 · inbound
Large Lemma Miners: Can LLMs do Induction Proofs for Hardware? cites this paper.
Large Lemma Miners: Can LLMs do Induction Proofs for Hardware? Using LLMs to Facilitate Formal Verification of RTL
Reference 27
- Resolution
- unresolved
- no resolver link, observed 2026-08-04T00:14:50.087432Z
Source-reported events for the cited work
Unavailable: canonical work link unavailable.
Observation 47a9021c-23f7-462f-b67e-db13e7c94ce1 · inbound
Can LLMs Make (Personalized) Access Control Decisions? cites this paper.
Can LLMs Make (Personalized) Access Control Decisions? Using LLMs to Facilitate Formal Verification of RTL
Reference 3
- Resolution
- verified exact
- arxiv_id, observed 2026-05-17T05:34:04.979472Z
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-23T06:30:58.430688+00:00.
Observation eeac30aa-ae68-4e9e-b4cc-3f5f0dd26a70 · inbound
The 4/$\delta$ Bound: Designing Predictable LLM-Verifier Systems for Formal Method Guarantee cites this paper.
The 4/$\delta$ Bound: Designing Predictable LLM-Verifier Systems for Formal Method Guarantee Using LLMs to Facilitate Formal Verification of RTL
Reference 20
- Resolution
- unresolved
- no resolver link, observed 2026-08-03T19:22:03.930769Z
Source-reported events for the cited work
Unavailable: canonical work link unavailable.
Observation e51d573e-f3bb-4721-b316-60fdf96f2775 · inbound
ChatSVA: Bridging SVA Generation for Hardware Verification via Task-Specific LLMs cites this paper.
ChatSVA: Bridging SVA Generation for Hardware Verification via Task-Specific LLMs Using LLMs to Facilitate Formal Verification of RTL
Reference 23
- Resolution
- verified exact
- arxiv_id, observed 2026-05-13T19:08:10.050604Z
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-23T06:30:58.430688+00:00.
Observation df119a78-3e04-4785-925e-1d781d82ff49 · inbound
CoverAssert: Iterative LLM Assertion Generation Driven by Functional Coverage via Syntax-Semantic Representations cites this paper.
CoverAssert: Iterative LLM Assertion Generation Driven by Functional Coverage via Syntax-Semantic Representations Using LLMs to Facilitate Formal Verification of RTL
Reference 11
- Resolution
- verified exact
- arxiv_id, observed 2026-05-11T00:05:50.980867Z
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-23T06:30:58.430688+00:00.
Observation 67643ced-40ea-4b95-8a62-c9e710ecd14e · inbound
Automated SVA Generation with LLMs cites this paper.
Automated SVA Generation with LLMs Using LLMs to Facilitate Formal Verification of RTL
Reference 28
- Resolution
- verified exact
- arxiv_id, observed 2026-05-11T09:06:00.653582Z
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-23T06:30:58.430688+00:00.
Observation 2d5529a4-1a2c-4a60-9f8b-30ccb5ed196a · inbound
From Language to Logic: Bridging LLMs & Formal Representations for RTL Assertion Generation cites this paper.
From Language to Logic: Bridging LLMs & Formal Representations for RTL Assertion Generation Using LLMs to Facilitate Formal Verification of RTL
Reference 11
- Resolution
- verified exact
- arxiv_id, observed 2026-05-11T20:41:11.977259Z
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-23T06:30:58.430688+00:00.
Observation 7f52892c-bd35-4834-9bbc-59d666f09cb5 · inbound
LLM Assisted Verification Assertion Generation: Challenges and Future Directions cites this paper.
LLM Assisted Verification Assertion Generation: Challenges and Future Directions Using LLMs to Facilitate Formal Verification of RTL
Reference 6
- Resolution
- verified exact
- local_arxiv, observed 2026-07-09T10:56:11.276441Z
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-23T06:30:58.430688+00:00.
Observation 87eb6e08-e678-4bbf-8075-688d14557ae8 · inbound
GoGoTB: Agentic RTL Verification with Specification-Grounded Coverage Closure cites this paper.
GoGoTB: Agentic RTL Verification with Specification-Grounded Coverage Closure Using LLMs to Facilitate Formal Verification of RTL
Reference 10
- Resolution
- unresolved
- no resolver link, observed 2026-08-01T00:37:11.599274Z
Source-reported events for the cited work
Unavailable: canonical work link unavailable.