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Establishing a New Benchmark in Quantum Computational Advantage with 105-qubit Zuchongzhi 3.0 Processor

T0 review · 2 major / 6 minor · reviewed 2026-08-11 · deepseek-v4-flash

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Pith's one-line read Zuchongzhi 3.0 performs 83-qubit, 32-cycle random circuit sampling whose classical simulation would take an estimated 6.4 billion years on Frontier, a cost six orders of magnitude beyond previous results.

desk verdict A clean RCS milestone with a conditional cost headline; referee it and demand the simulation details. read the letter →

arxiv 2412.11924 v1 pith:YQPFYWPC submitted 2024-12-16 quant-ph

Dongxin Gao , Daojin Fan , Chen Zha , Jiahao Bei , Guoqing Cai , Jianbin Cai , Sirui Cao , Xiangdong Zeng
show 146 more authors
Fusheng Chen Jiang Chen Kefu Chen Xiawei Chen Xiqing Chen Zhe Chen Zhiyuan Chen Zihua Chen Wenhao Chu Hui Deng Zhibin Deng Pei Ding Xun Ding Zhuzhengqi Ding Shuai Dong Yupeng Dong Bo Fan Yuanhao Fu Song Gao Lei Ge Ming Gong Jiacheng Gui Cheng Guo Shaojun Guo Xiaoyang Guo Tan He Linyin Hong Yisen Hu He-Liang Huang Yong-Heng Huo Tao Jiang Zuokai Jiang Honghong Jin Yunxiang Leng Dayu Li Dongdong Li Fangyu Li Jiaqi Li Jinjin Li Junyan Li Junyun Li Na Li Shaowei Li Wei Li Yuhuai Li Yuan Li Futian Liang Xuelian Liang Nanxing Liao Jin Lin Weiping Lin Dailin Liu Hongxiu Liu Maliang Liu Xinyu Liu Xuemeng Liu Yancheng Liu Haoxin Lou Yuwei Ma Lingxin Meng Hao Mou Kailiang Nan Binghan Nie Meijuan Nie Jie Ning Le Niu Wenyi Peng Haoran Qian Hao Rong Tao Rong Huiyan Shen Qiong Shen Hong Su Feifan Su Chenyin Sun Liangchao Sun Tianzuo Sun Yingxiu Sun Yimeng Tan Jun Tan Longyue Tang Wenbing Tu Cai Wan Jiafei Wang Biao Wang Chang Wang Chen Wang Chu Wang Jian Wang Liangyuan Wang Rui Wang Shengtao Wang Xinzhe Wang Zuolin Wei Jiazhou Wei Dachao Wu Gang Wu Jin Wu Shengjie Wu Yulin Wu Shiyong Xie Lianjie Xin Yu Xu Chun Xue Kai Yan Weifeng Yang Xinpeng Yang Yang Yang Yangsen Ye Zhenping Ye Chong Ying Jiale Yu Qinjing Yu Wenhu Yu Shaoyu Zhan Feifei Zhang Haibin Zhang Kaili Zhang Pan Zhang Wen Zhang Yiming Zhang Yongzhuo Zhang Lixiang Zhang Guming Zhao Peng Zhao Xianhe Zhao Xintao Zhao Youwei Zhao Zhong Zhao Luyuan Zheng Fei Zhou Liang Zhou Na Zhou Naibin Zhou Shifeng Zhou Shuang Zhou Zhengxiao Zhou Chengjun Zhu Qingling Zhu Guihong Zou Haonan Zou Qiang Zhang Chao-Yang Lu Cheng-Zhi Peng XiaoBo Zhu Jian-Wei Pan
This is my paper · ORCID
classification quant-ph
keywords quantumcomputationaladvantagerandomcircuitsamplingsuperconductingqubitsZuchongzhi3.0tensor-networksimulationcross-entropybenchmarkingtransmonprocessor105
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

The paper presents Zuchongzhi 3.0, a superconducting processor with 105 transmon qubits, and uses 83 of them to run a 32-cycle random circuit sampling experiment. It reports single-qubit, two-qubit, and readout fidelities of 99.90%, 99.62%, and 99.18%, and collects around 410 million bitstrings in about 91 hours, with one million samples achievable in a few hundred seconds. The central claim is that reproducing one million samples of this 83-qubit, 32-cycle circuit on the Frontier supercomputer would take roughly $6.4\times 10^9$ years under the current tensor-network simulation cost model. That places the estimated classical cost about six orders of magnitude above the previous 67- and 70-qubit random circuit sampling experiments, which the paper presents as establishing a new benchmark in quantum computational advantage. If correct, the result substantially widens the demonstrated gap between quantum and classical processing for this carefully chosen sampling task.

What carries the argument

The load-bearing object is the random circuit itself: 83 transmon qubits from a 105-qubit, 15-by-7 lattice running 32 cycles of single-qubit gates randomly chosen from $\sqrt{X}$, $\sqrt{Y}$, and $\sqrt{W}$, interleaved with iSWAP-like two-qubit gates in the ABCD-CDAB pattern. The argument is carried by the pairing of this circuit with the tensor-network contraction cost model: the paper counts floating-point operations for one million uncorrelated noisy bitstrings under two memory scenarios, then divides by Frontier's estimated throughput to get the claimed runtime. The experimental side is anchored by patch-circuit verification, where 2-patch and 4-patch circuits with tractable classical simulation are used to confirm that the discrete error model's fidelity predictions track the experiment closely; this is what lets the full-circuit fidelity be trusted without a classical simulation of the full circuit.

What would settle it

Run the same 83-qubit, 32-cycle circuit through an independent tensor-network simulator and count the actual floating-point operations needed to produce one million uncorrelated noisy bitstrings at fidelity 0.025%; if another contraction ordering finishes on Frontier-scale hardware in far less than $6.4\times 10^9$ years, the infeasibility claim is refuted. A cheaper check is to reproduce the single-amplitude FLOP count of $5.1\times 10^{31}$ with a separate code and see whether the published cost estimate matches.

Watch

Extended reading notes

Core claim

The paper's central discovery is an experimental scaling-up of random circuit sampling beyond the previous frontier. On Zuchongzhi 3.0, the authors run an 83-qubit circuit for 32 cycles, verify fidelity through patch-circuit cross-entropy benchmarking (the measured 83-qubit 4-patch fidelity is 0.030% versus an estimate of 0.033%), and estimate the full-circuit fidelity at 0.025%. The authors then use the state-of-the-art tensor-network contraction method to estimate that generating a million uncorrelated bitstrings at that fidelity would need about $8.4\times 10^{33}$ floating-point operations under a 9.2 PB memory constraint, corresponding to about $6.4\times 10^9$ years on Frontier even assuming 20% peak FLOP efficiency; under an unrealistic 762.2 PB memory limit, the estimate is $7.5\times 10^{31}$ operations and $5.7\times 10^7$ years. Because this cost is roughly six orders of magnitude larger than their corresponding estimate for the SYC-67 and SYC-70 experiments, they claim a new quantum computational advantage benchmark.

Load-bearing premise

The central claim collapses if the tensor-network cost model used for the estimates overstates how fast a classical computer can simulate the 83-qubit, 32-cycle circuit; the 6.4-billion-year figure and the six-orders-of-magnitude margin both come from that model's assumed contraction ordering and 20% FLOP efficiency.

Editorial extensions

If this is right

  • The 83-qubit, 32-cycle circuit becomes the new reference point for random circuit sampling experiments, with an estimated classical simulation cost about six orders of magnitude above the prior 67- and 70-qubit results.
  • The validation pattern of matching 4-patch measured fidelities to discrete-error-model predictions supports using the same estimation method for even larger circuits as hardware scales.
  • The reported hardware fidelities (0.10% single-qubit Pauli error, 0.38% two-qubit Pauli error, 0.82% readout error with active reset) indicate the same processor can run further RCS configurations with more qubits or more cycles.
  • Even if one ignores realistic memory limits and assumes 762.2 PB of available memory, the estimated classical runtime remains $5.7\times 10^7$ years, so the claimed gap is not merely an artifact of the 9.2 PB memory cap.
  • The combination of high-fidelity gates and fast, stable sampling (400 µs per shot with active reset) makes the platform a candidate for near-term applications the paper lists, including optimization, machine learning, and drug discovery.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • Because the cost figures come from the paper's own tensor-network contraction model with an assumed 20% FLOP efficiency, the exact billion-year number is model-dependent; an independent contraction ordering or improved tensor-network code could change the runtime estimate by orders of magnitude without changing the experimental data.
  • The six-orders-of-magnitude margin is computed with the same model for both the new circuit and the previous experiments, so the comparison is self-consistent but not an absolute statement about all possible classical algorithms; the earlier claims made for the previous experiments are not affected by this new result.
  • A direct stress test of the advantage claim would be to release the full circuit specification and let independent groups attempt optimized tensor-network or other simulations, comparing measured FLOP counts against the paper's table of costs.
  • If the sampling advantage is to become useful rather than a benchmark, the same 83-qubit platform would need to be paired with algorithms that translate high-fidelity samples into answers for optimization or machine-learning problems; the paper gestures at these directions but does not demonstrate them.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

2 major / 6 minor

Summary. The paper reports on Zuchongzhi 3.0, a 105-qubit superconducting processor, and a random circuit sampling (RCS) experiment on an 83-qubit, 32-cycle circuit. The authors measure gate and readout fidelities, use patch circuits to estimate the fidelity of the full circuit, collect 410 million bitstrings, and estimate that reproducing one million samples on Frontier would take about 6.4e9 years, which they state is six orders of magnitude beyond Google's SYC-67 experiment. The paper concludes that this establishes a new benchmark in quantum computational advantage.

Significance. If the classical cost estimate is correct, this is an important experimental milestone for RCS-based quantum advantage. The calibration and verification effort is a strength: the 31-qubit full-circuit versus patch-circuit fidelity scaling provides a useful consistency check, the 4-patch calibration is a sensible methodology, and the supplemental material contains detailed device characterization, active reset, crosstalk correction, and stability monitoring. The paper's central quantitative claim, however, depends on a tensor-network cost model from the same collaboration with no independent validation and no uncertainty estimate, and the full 83-qubit circuit fidelity is extrapolated from patch circuits rather than directly verified. The work is therefore significant and worth publishing, but the headline claim needs stronger support before acceptance.

major comments (2)
  1. [Computational Cost Estimation, Table I] The central claim of 6.4e9 years on Frontier rests entirely on the FLOP counts in Table I, which are produced with tensor-network algorithms from refs [26,27] of the same collaboration. The text states that a 20% FLOP efficiency is 'presumed' and uses a factor of 8 machine FLOPs per complex FLOP, but no contraction-path data, no independent implementation, and no uncertainty analysis are provided. Since the six-orders-of-magnitude benchmark is a direct comparison of this estimated classical cost, the estimate is load-bearing. Please provide a sensitivity analysis over the FLOP-efficiency assumption, memory constraints, and contraction ordering, and release sufficient details (e.g., contraction paths or a reproducible benchmark) for independent scrutiny. The inconsistent use of '80 qubits' versus '83 qubits' in this same section should also be corrected.
  2. [Large-Scale Random Circuit Sampling, Fig. 3(c)] The fidelity of the 83-qubit, 32-cycle full circuit is not measured directly; it is extrapolated from 4-patch circuits and an error model, yielding an estimated fidelity of 0.025%. The 31-qubit fidelity scaling is a valuable consistency check, but it does not certify the larger full-circuit fidelity, and systematic errors in idle gates, coupler distortion, or state preparation could shift the extrapolation. Because the classical sampling cost in Table I scales with fidelity (the '1 Million Noisy Samples' column depends on the target fidelity), the uncertainty in this extrapolated fidelity propagates into the headline runtime. Please quantify the uncertainty in the full-circuit fidelity estimate and discuss how a 5x or 10x deviation in the actual full-circuit fidelity would affect the claimed advantage.
minor comments (6)
  1. [Computational Cost Estimation] The word 'harderst' is a typo; it should be 'hardest'.
  2. [Computational Cost Estimation] The text alternates between '80 qubits' and '83 qubits' for the same circuit; please use '83 qubits' consistently throughout.
  3. [Fig. 4] The caption and axes of Figure 4 are unclear in the provided text: the 'dotted line illustrates the pattern of doubly-exponential growth' is not defined, and the x- and y-axes are not labeled in the figure as rendered.
  4. [Large-Scale Random Circuit Sampling] The sentence 'the average fidelity ratios of the 4-patch circuit to the full circuit fidelity is 1.05' is grammatically awkward and should be rewritten.
  5. [Abstract] The abstract emphasizes the 105-qubit processor, but the RCS experiment uses an 83-qubit subset; consider clarifying this distinction in the abstract itself to avoid confusion.
  6. [Table S2] The supplemental table includes a 46.2 PB memory scenario that is not discussed in the main text; please add a sentence explaining its relevance or remove it.

Circularity Check

0 steps flagged · score 0.0 of 10

No circularity: full-circuit fidelity is a validated prediction, and the classical runtime estimate is an externally falsifiable benchmark rather than a fitted input.

full rationale

The paper's derivation chain has three load-bearing components. (1) Processor calibration: single-qubit, two-qubit, and readout errors are measured by standard XEB and SPB methods; these are inputs, not conclusions. (2) Full-circuit fidelity: the 83-qubit, 32-cycle fidelity (0.025%) is predicted by a discrete error model from the measured gate and readout errors, not fitted to the full-circuit output. The model is validated on smaller systems: the 31-qubit 2-patch and 4-patch circuits and the 83-qubit 4-patch circuit, where the experimental fidelity of 0.030% agrees with the estimated 0.033%. This validation is on the same hardware but is not a circular reduction; the full-circuit fidelity is a genuine extrapolation from per-gate errors. (3) Classical cost: the 6.4e9-year Frontier estimate follows from tensor-network contraction FLOP counts in refs. [26,27] combined with stated assumptions (20% FLOP efficiency, 8 machine FLOPs per complex FLOP, 9.2 PB memory). The runtime is not defined as equal to the quantum sampling time, and no parameter is fitted to make the claim; the cost model is externally testable and falsifiable by any independent tensor-network implementation. The self-cited nature of refs. [26,27] is a validation and provenance concern, since no independent implementation or uncertainty estimate appears in this paper, but it is not circularity: those works provide an algorithmic cost model whose assumptions do not include the target 6.4e9-year runtime. The '80 qubits' versus '83 qubits' inconsistency in Section V is a typographical error, not a circular step. Overall, no prediction in this paper reduces to its own input by construction.

Assumptions & free parameters 1 free parameters · 3 assumptions · 0 invented entities

The central claim relies on a computational complexity conjecture, the accuracy of the tensor-network cost model, and the extrapolation of patch-circuit fidelities to the full circuit. The only hand-chosen numerical parameter we identified is the 20% FLOP efficiency. No invented entities are introduced.

free parameters (1)
  • Classical FLOP efficiency = 20%
    The runtime estimate divides the FLOP count by 20% of Frontier's peak FLOPS. This factor is assumed, not measured, and directly sets the 6.4e9 year headline number.
assumptions (3)
  • domain assumption Random circuit sampling is classically hard on average.
    The entire benchmark's significance depends on this computational complexity conjecture, invoked implicitly throughout the introduction and cost section.
  • domain assumption The tensor-network contraction algorithms of refs [26,27] give a reliable near-optimal cost estimate for the 83-qubit 32-cycle circuit.
    The classical cost numbers (5.1e31 and 8.4e33 FLOP) are taken from these references, which are co-authored by members of this collaboration; no independent benchmark is given.
  • domain assumption The discrete error model, built from per-gate Pauli errors and readout errors, extrapolates accurately from 4-patch circuits to the full 83-qubit 32-cycle circuit.
    Used in Fig. 3 to convert measured 4-patch fidelities (0.030%) and the 1.05 fidelity ratio into the 0.025% full-circuit fidelity estimate.

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Cite this review

Pith. "Pith review of Establishing a New Benchmark in Quantum Computational Advantage with 105-qubit Zuchongzhi 3.0 Processor." pith.science (2026). https://pith.science/paper/YQPFYWPC

@misc{pith2026241211924,
  author       = {Pith},
  title        = {Pith review of: Establishing a New Benchmark in Quantum Computational Advantage with 105-qubit Zuchongzhi 3.0 Processor},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/YQPFYWPC}},
  note         = {Machine review of arXiv:2412.11924}
}
abstract

In the relentless pursuit of quantum computational advantage, we present a significant advancement with the development of Zuchongzhi 3.0. This superconducting quantum computer prototype, comprising 105 qubits, achieves high operational fidelities, with single-qubit gates, two-qubit gates, and readout fidelity at 99.90%, 99.62% and 99.18%, respectively. Our experiments with an 83-qubit, 32-cycle random circuit sampling on Zuchongzhi 3.0 highlight its superior performance, achieving one million samples in just a few hundred seconds. This task is estimated to be infeasible on the most powerful classical supercomputers, Frontier, which would require approximately $6.4\times 10^9$ years to replicate the task. This leap in processing power places the classical simulation cost six orders of magnitude beyond Google's SYC-67 and SYC-70 experiments [Nature 634, 328(2024)], firmly establishing a new benchmark in quantum computational advantage. Our work not only advances the frontiers of quantum computing but also lays the groundwork for a new era where quantum processors play an essential role in tackling sophisticated real-world challenges.

Figures

Figures reproduced from arXiv: 2412.11924 by the authors.

Figure 1
Figure 1. FIG. 1 [PITH_FULL_IMAGE:figures/full_fig_p003_1.png] view at source ↗
Figure 2
Figure 2. FIG. 2 [PITH_FULL_IMAGE:figures/full_fig_p003_2.png] view at source ↗
Figure 3
Figure 3. FIG. 3 [PITH_FULL_IMAGE:figures/full_fig_p004_3.png] view at source ↗
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Figure 4
Figure 4. Figure 4: FIG. 4 [PITH_FULL_IMAGE:figures/full_fig_p005_4.png]

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Reviewed August 11, 2026 · model on record in the stance chip above.