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Paper Citation Record · LEDGER

RTLLM: An Open-Source Benchmark for Design RTL Generation with Large Language Model

As of 20 August 2026, this Paper Citation Record lists 0 of 0 outbound references and 17 inbound Pith citation observations for arXiv:2308.05345.

A citation records a reference. It does not transfer a finding from one paper to another.

pith.paper-citation-record.v1
2308.05345 v3

Coverage vector

measured 0 of 0 reference resolution

Typed states for the displayed outbound observations.

Source: paper_references, paper_reference_links

measured 17 of 17 standing notices

One-hop event checks from named stored sources.

Source: scholarly_work_events, retraction_status_cache, observed 2026-08-20T06:33:59.587034+00:00

measured 17 of 17 inbound itemization

Pith citing papers itemized under the disclosed page cap.

Source: paper_references, paper_reference_links, observed 2026-08-16T00:08:22.494120Z

measured 0 of 1 external citation measurements

A source-named dated measurement, never combined with another source.

Source: arxiv_reference, observed 2026-07-03T19:08:49.829179Z

Reference resolution

0 of 0 outbound references displayed

  • verified exact0
  • verified fuzzy0
  • unresolved0
  • parse uncertain0
  • malformed identifier0
  • metadata mismatch0

External citation measurements

No source-named external measurement is stored.

Outbound references

No outbound reference observations are available for this paper version.

Pith citing papers

Observation dae15a0d-97fa-4c82-9daf-218d30c363e4 · inbound

UVLLM: An Automated Universal RTL Verification Framework using LLMs cites this paper.

UVLLM: An Automated Universal RTL Verification Framework using LLMs RTLLM: An Open-Source Benchmark for Design RTL Generation with Large Language Model

Reference 38

Resolution
unresolved
no resolver link, observed 2026-08-12T13:27:04.894147Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

source=pdf_text observed=2026-08-12T13:27:04.894147Z digest=sha256:b72410b657410af2d5ec8a4df01bb07292d1c97e45e238a2a0cd68db756a5de8

Observation 36617016-8920-4334-91c5-ec98211a98ac · inbound

C2HLSC: Leveraging Large Language Models to Bridge the Software-to-Hardware Design Gap cites this paper.

C2HLSC: Leveraging Large Language Models to Bridge the Software-to-Hardware Design Gap RTLLM: An Open-Source Benchmark for Design RTL Generation with Large Language Model

Reference 13

Resolution
unresolved
no resolver link, observed 2026-08-12T05:41:30.974962Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

source=pdf_text observed=2026-08-12T05:41:30.974962Z digest=sha256:21492f50228f420d27f924b8e89591fb0a8d9854839ae68cb3089ffddd2c0a14

Observation 5665f351-9293-413b-94ce-4ca0d4d765cd · inbound

AGON: Automated Design Framework for Customizing Processors from ISA Documents cites this paper.

AGON: Automated Design Framework for Customizing Processors from ISA Documents RTLLM: An Open-Source Benchmark for Design RTL Generation with Large Language Model

Reference 11

Resolution
unresolved
no resolver link, observed 2026-08-10T23:11:12.545554Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

source=pdf_text observed=2026-08-10T23:11:12.545554Z digest=sha256:b90cfd3456bb58d4a1238ab64281917707a06de50d59c4e9dabe0b326ff854b7

Observation ba44d707-69e4-4856-a443-415cd7a75c30 · inbound

A Survey of Research in Large Language Models for Electronic Design Automation cites this paper.

A Survey of Research in Large Language Models for Electronic Design Automation RTLLM: An Open-Source Benchmark for Design RTL Generation with Large Language Model

Reference 36

Resolution
unresolved
no resolver link, observed 2026-08-10T19:49:55.594550Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

source=pdf_text observed=2026-08-10T19:49:55.594550Z digest=sha256:f291315975c28a35a65eff4457b9d22a195720facebb3c3911942e498c078098

Observation c76af563-6072-4a2a-80f2-724bee73e467 · inbound

From Concept to Practice: an Automated LLM-aided UVM Machine for RTL Verification cites this paper.

From Concept to Practice: an Automated LLM-aided UVM Machine for RTL Verification RTLLM: An Open-Source Benchmark for Design RTL Generation with Large Language Model

Reference 44

Resolution
verified exact
arxiv_id, observed 2026-05-22T18:01:54.470242Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-20T06:33:59.587034+00:00.

source=pdf_text observed=2026-05-22T17:58:45.319714Z digest=sha256:576f1da2d299bda2935b635b491a0ba6f7c7629ec1fa6f900b6274277c4de2c8

Observation b9485870-131b-4930-9d3b-df4425eefedb · inbound

RTL++: Graph-enhanced LLM for RTL Code Generation cites this paper.

RTL++: Graph-enhanced LLM for RTL Code Generation RTLLM: An Open-Source Benchmark for Design RTL Generation with Large Language Model

Reference 41

Resolution
unresolved
no resolver link, observed 2026-08-15T22:36:25.247836Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

source=pdf_text observed=2026-08-15T22:36:25.247836Z digest=sha256:7e2b26e78d28c3c3531975bd2b89ef09e167516d112eefcb18b39a951ab07201

Observation 30f26d61-7c48-478b-9130-c8cb31a7354c · inbound

Generalizing Large Language Model Usability Across Resource-Constrained cites this paper.

Generalizing Large Language Model Usability Across Resource-Constrained RTLLM: An Open-Source Benchmark for Design RTL Generation with Large Language Model

Reference 79

Resolution
unresolved
no resolver link, observed 2026-08-15T22:08:54.352351Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

source=pdf_text observed=2026-08-15T22:08:54.352351Z digest=sha256:77e84d66c7015347b042ac44c6e76edf3370c119ad429e92179b3ee79156a466

Observation 0c54734d-6ff0-4f51-9f47-90269c4296f3 · inbound

Veritas: Deterministic Verilog Code Synthesis from LLM-Generated Conjunctive Normal Form cites this paper.

Veritas: Deterministic Verilog Code Synthesis from LLM-Generated Conjunctive Normal Form RTLLM: An Open-Source Benchmark for Design RTL Generation with Large Language Model

Reference 16

Resolution
unresolved
no resolver link, observed 2026-08-15T23:27:33.035330Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

source=pdf_text observed=2026-08-15T23:27:33.035330Z digest=sha256:d53e419b686b158ad07e42b8c81bd4bb690ae5a5c8c1fef70f5c6d523e59bb7e

Observation e00af0db-2ebd-456b-967f-954bb8a5dc2b · inbound

ProtocolLLM: RTL Benchmark for SystemVerilog Generation of Communication Protocols cites this paper.

ProtocolLLM: RTL Benchmark for SystemVerilog Generation of Communication Protocols RTLLM: An Open-Source Benchmark for Design RTL Generation with Large Language Model

Reference 25

Resolution
unresolved
no resolver link, observed 2026-08-07T05:27:36.116201Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

source=pdf_text observed=2026-08-07T05:27:36.116201Z digest=sha256:23cdbdb1c6e1615a2b1b1fdcb480fbd38cfcd3fff48214b30cefa94515216411

Observation ae9f620a-8bc0-44ee-8e46-5e8db082ebdb · inbound

Spec2RTL-Agent: Automated Hardware Code Generation from Complex Specifications Using LLM Agent Systems cites this paper.

Spec2RTL-Agent: Automated Hardware Code Generation from Complex Specifications Using LLM Agent Systems RTLLM: An Open-Source Benchmark for Design RTL Generation with Large Language Model

Reference 6

Resolution
unresolved
no resolver link, observed 2026-08-07T00:31:00.464408Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

source=pdf_text observed=2026-08-07T00:31:00.464408Z digest=sha256:3c416028a58c77433d094d0a554a83765f0aaaa4e3cb0cbd742ba81c6098a74f

Observation 0ec66da2-188b-4aa0-ad9e-db7e4d35ed1e · inbound

HYPERHEURIST: A Simulated Annealing-Based Control Framework for LLM-Driven Code Generation in Optimized Hardware Design cites this paper.

HYPERHEURIST: A Simulated Annealing-Based Control Framework for LLM-Driven Code Generation in Optimized Hardware Design RTLLM: An Open-Source Benchmark for Design RTL Generation with Large Language Model

Reference 13

Resolution
verified exact
arxiv_id, observed 2026-05-10T09:18:31.652957Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-20T06:33:59.587034+00:00.

source=pdf_text observed=2026-05-10T08:04:48.949697Z digest=sha256:cc263dd113f8cdb04058e687729ab67a4253635dc126a2c584e580a477e21676

Observation 3d5d9d3e-8043-428a-ba6d-849ead6e5f83 · inbound

UVMarvel: an Automated LLM-aided UVM Machine for Subsystem-level RTL Verification cites this paper.

UVMarvel: an Automated LLM-aided UVM Machine for Subsystem-level RTL Verification RTLLM: An Open-Source Benchmark for Design RTL Generation with Large Language Model

Reference 28

Resolution
verified exact
arxiv_id, observed 2026-05-11T18:31:13.607006Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-20T06:33:59.587034+00:00.

source=pdf_text observed=2026-05-08T15:36:38.153161Z digest=sha256:836842968c4692afdc001b32d2c9898daa85f886fba139d0d75a944a0784818d

Observation e0a1726e-097f-4a4a-9c96-d81362237d81 · inbound

Verilog-Evolve: Feedback-Driven and Skill-Evolving Verilog Generation cites this paper.

Verilog-Evolve: Feedback-Driven and Skill-Evolving Verilog Generation RTLLM: An Open-Source Benchmark for Design RTL Generation with Large Language Model

Reference 11

Resolution
verified exact
arxiv_id, observed 2026-06-29T18:53:51.248419Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-20T06:33:59.587034+00:00.

source=pdf_text observed=2026-06-29T18:49:52.243940Z digest=sha256:5cf02ecbef0f05de79aff5016671494050dc8486512d46ea860033d29b76bee5

Observation b59d7472-3626-4883-9d00-00644f5b25b8 · inbound

Alpha-RTL: Test-Time Training for RTL Hardware Optimization cites this paper.

Alpha-RTL: Test-Time Training for RTL Hardware Optimization RTLLM: An Open-Source Benchmark for Design RTL Generation with Large Language Model

Reference 28

Resolution
verified exact
arxiv_id, observed 2026-07-02T07:06:44.149727Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-20T06:33:59.587034+00:00.

source=arxiv_source observed=2026-06-28T07:11:52.187869Z digest=sha256:31e4b0a41b17fee0f9a41404644a1cfa8c5e4236110ccbffc72f5db383a58928

Observation 463f3ad8-a58f-4bf7-8ddd-6ad287335458 · inbound

PDAGENT-BENCH: Characterizing, Grounding, and Architecting LLM Agents for VLSI Physical Design cites this paper.

PDAGENT-BENCH: Characterizing, Grounding, and Architecting LLM Agents for VLSI Physical Design RTLLM: An Open-Source Benchmark for Design RTL Generation with Large Language Model

Reference 20

Resolution
verified exact
arxiv_id, observed 2026-07-03T19:08:49.830893Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-20T06:33:59.587034+00:00.

source=pdf_text observed=2026-06-27T02:11:34.174504Z digest=sha256:61eee92664ded0c47eb9a13d62a96c0ae371edfc56df918f821474dfcc23622e

Observation 89c1c522-7ddf-44bb-acb3-3c138501172b · inbound

Agentic Hardware Design as Repository-Level Code Evolution cites this paper.

Agentic Hardware Design as Repository-Level Code Evolution RTLLM: An Open-Source Benchmark for Design RTL Generation with Large Language Model

Reference 8

Resolution
metadata mismatch
arxiv_id, observed 2026-07-01T18:45:58.333957Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-20T06:33:59.587034+00:00.

source=pdf_text observed=2026-06-29T01:49:07.838897Z digest=sha256:30437455593b93d6b9e84522b63d8798314f757c543e006c215efbbc5270ae63

Observation 1106c16c-9584-4fcf-abbe-4ceb298612f5 · inbound

GateTruth: Auditing the Rigor of RTL Design Benchmarks via Mutation Testing cites this paper.

GateTruth: Auditing the Rigor of RTL Design Benchmarks via Mutation Testing RTLLM: An Open-Source Benchmark for Design RTL Generation with Large Language Model

Reference 9

Resolution
unresolved
no resolver link, observed 2026-08-16T00:08:22.494120Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

source=pdf_text observed=2026-08-16T00:08:22.494120Z digest=sha256:c778204492e3d82f4534f8fd48efb9aacf950675d3e1ea8da11414233c2cce28