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MLIR: A Compiler Infrastructure for the End of Moore's Law

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arxiv 2002.11054 v2 pith:ZILLUJUS submitted 2020-02-25 cs.PL cs.LG

Chris Lattner , Mehdi Amini , Uday Bondhugula , Albert Cohen , Andy Davis , Jacques Pienaar , River Riddle , Tatiana Shpeisman
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Nicolas Vasilache Oleksandr Zinenko
This is my paper · ORCID
classification cs.PLcs.LG
keywords mlirdesignbuildingcompilersinfrastructurecompilercostenvironments
verification ladder T0 review T1 audit T2 compute T3 formal
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This work presents MLIR, a novel approach to building reusable and extensible compiler infrastructure. MLIR aims to address software fragmentation, improve compilation for heterogeneous hardware, significantly reduce the cost of building domain specific compilers, and aid in connecting existing compilers together. MLIR facilitates the design and implementation of code generators, translators and optimizers at different levels of abstraction and also across application domains, hardware targets and execution environments. The contribution of this work includes (1) discussion of MLIR as a research artifact, built for extension and evolution, and identifying the challenges and opportunities posed by this novel design point in design, semantics, optimization specification, system, and engineering. (2) evaluation of MLIR as a generalized infrastructure that reduces the cost of building compilers-describing diverse use-cases to show research and educational opportunities for future programming languages, compilers, execution environments, and computer architecture. The paper also presents the rationale for MLIR, its original design principles, structures and semantics.

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Forward citations

Cited by 11 Pith papers

Reviewed papers in the Pith corpus that reference this work. Sorted by Pith novelty score. OpenAlex reports about 120 citations worldwide. Full citation record

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    On the new SeGaBench benchmark, the strongest of five LLMs recovered compiler-missed optimization semantics and produced validated, speedup-delivering code changes in a large majority of cases.

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    An agentic kernel-coding system combining tree search with hardware-knowledge retrieval generated optimized Triton kernels for NVIDIA, AMD, and Meta's MTIA accelerators: 100% correctness on 480 operator-platform confi...

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    Adding a cache hierarchy, CGRA-specific runahead prefetching, and per-PE cache reconfiguration allows CGRAs to process irregular memory-access kernels at near-ideal speed with 1.27% of the storage.

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    Adding a description-length term to the quantum-compiler objective changes the chosen circuit on ~0.3% of tested single-qubit targets, showing gate-count-only compilation discards genuinely structured alternatives.

  6. From Intent to Infrastructure: LLM-Driven Agent Compilers for ISAC Networks

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    An LLM-driven compilation layer for ISAC networks parses engineer intent into a policy graph and adapts configurations at three time scales.

  7. ATLAS: Multi-View Code Representation Tool for C and C++ Source Programs

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    ATLAS claims no-build aligned AST/CFG/DFG extraction for C/C++ at 96.8%/91.7% CFG correctness, and a 34.7-point LLM line-coverage lift when fed its CFG paths.

  8. Improving compiler support for SIMD offload using Arm Streaming SVE

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    Current LLVM and MLIR auto-vectorizers produce slow Streaming SVE code because their cost models ignore streaming-mode overheads and memory hazards.

  9. A Unified Framework for Mapping and Synthesis of Approximate R-Blocks CGRAs

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  11. Pattern-Guided Design Space Exploration for FPGA Accelerator Design

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    Pattern-guided design-space exploration reduces HLS evaluations from 140 to 29 on six kernels while matching the best achieved latency, but relies on hand-assigned patterns and a weak baseline.

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