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REVIEW 3 major objections 7 minor 16 references

Deep sub micron normally off AlGaN/GaN MOSFET on silicon with VTH > 5V and On Current > 0.5 A/mm

T0 review · 3 major / 7 minor · reviewed 2026-08-14 · deepseek-v4-flash

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Pith's one-line read A recessed-gate AlGaN/GaN MOSFET on silicon achieves a threshold voltage above 5 V with an on-current of 500 mA/mm, a combination the paper says is the best reported so far for normally-off GaN devices.

desk verdict A genuine, incremental device demonstration with the best VTH/on-current combination in its own comparison table, held back by an undefined VTH extraction and single-device support. read the letter →

arxiv 1908.05853 v1 pith:ZL5D3CJN submitted 2019-08-16 physics.app-ph

Sandeep Kumar , Sandeep Vura , Surani B. Dolmanan , Sudhiranjan Tripathy , R. Muralidharan , Digbijoy N. Nath This is my paper · ORCID
classification physics.app-ph
keywords AlGaN/GaNnormally-offHEMTrecessed-gateMOSFETthresholdvoltageon-currentpost-metalannealenhancement-modepowerelectronics
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

This paper reports a normally-off AlGaN/GaN transistor on a silicon substrate in which a 200 nm-long, 124 nm-deep recess etched under the gate removes the two-dimensional electron gas at zero bias, making the device enhancement-mode. By varying recess depth and post-deposition annealing conditions, the authors tuned the threshold voltage and obtained an optimized device with threshold voltage above 5 V and on-current of about 500 mA/mm. These two numbers together, the paper argues, are the best normally-off combination reported among the devices it tabulates. The result matters because normally-off GaN transistors with high threshold and high current are desired for fail-safe power switching, and most prior devices traded one against the other. The paper also identifies a limitation of the deeply recessed gate: destructive breakdown near 40 V, which 2D-TCAD simulations attribute to residual electric field penetrating the short recess region.

What carries the argument

The key object is the gate recess: a 200 nm trench etched through the AlGaN barrier and into the GaN channel (124 nm total depth), so that under the gate the two-dimensional electron gas is removed and the device turns off at zero gate bias; an ALD-grown Al2O3 layer of 30 nm then separates the gate metal from the etched GaN. The second control is the post-deposition and post-metal anneal at 500 C in forming gas, which shifts VTH positive by reducing interface fixed charge, moving Device III from about 2 V before anneal to above 5 V after. A field plate extends over the access region. The combination of a deep recess (high VTH) and a short gate length (high current) carries the claimed performance, while the 2D-TCAD electric-field simulation explains why the short recess leaves residual electric field across most of the recess and leads to early breakdown.

What would settle it

Fabricate multiple devices with the same recess and anneal recipe, extract VTH with a fixed linear-extrapolation rule, and plot the distribution of threshold against on-current; if the typical device does not reach above 5 V while sustaining 500 mA/mm, the record-combination claim is falsified. A more targeted check is a wafer-scale VTH map: large spatial variation would show that the single Device III result is not process-representative.

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Extended reading notes

Core claim

The central claim, made for the device labelled Device III, is that a recessed-gate AlGaN/GaN MOSFET with a 124 nm recess depth, a 30 nm ALD-grown Al2O3 gate dielectric, and a 500 C post-metal anneal achieves simultaneous normally-off operation (threshold voltage above 5 V by linear extrapolation, listed as +5.1 V in Table I) and a drain current of 500 mA/mm at gate and drain biases of 10 V and 5 V. The paper states that this is the best on-current and VTH combination among normally-off devices reported to date, comparing against prior recessed-gate, fluorine-implanted, and p-GaN/p-AlGaN devices whose thresholds and currents range from about +1 V at 200 mA/mm to +7.6 V at 355 mA/mm. The positive threshold shift after post-metal annealing is attributed to a reduction of fixed charge at the Al2O3/GaN interface.

Load-bearing premise

The headline numbers come from single-device measurements of one fabricated device, shown in one transfer curve and one output curve, with no device-to-device statistics and no explicit statement of the threshold-voltage extraction rule; if that device is not representative of the process, or if its threshold is measured differently from the comparison table, the 'best reported combination' claim does not hold.

Editorial extensions

If this is right

  • A 200 nm recess with 124 nm depth is sufficient to deplete the 2DEG and maintain enhancement-mode operation with threshold voltage above 5 V.
  • Post-metal annealing in forming gas at 500 C can raise VTH by several volts, providing a process lever for threshold control in recessed-gate GaN devices.
  • The same process on a silicon substrate can deliver on-current near 0.5 A/mm, comparable to many normally-on HEMTs and removing one practical objection to enhancement-mode GaN power switches.
  • The deep short recess limits three-terminal breakdown to roughly 40 V, so the demonstrated device is not suitable for power blocks above that voltage without a longer recess or improved etched-GaN interface.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • If the 500 mA/mm and above-5 V combination reproduces across devices, a natural next step is a longer recess or graded recess to push breakdown voltage upward while retaining high threshold, a direction the authors themselves suggest.
  • The threshold-voltage comparison across Table I assumes a consistent linear-extrapolation convention; a constant-current definition such as 1 mA/mm could shift VTH by a volt or more, so the 'best combination' claim is sensitive to the extraction rule.
  • The TCAD-based residual-field explanation implies a testable relationship: breakdown voltage should increase monotonically with recess length in otherwise identical devices, which a simple recess-length series could verify.
  • Because the claimed performance depends on the Al2O3/etched-GaN interface, interface-trap characterization of the recess sidewall would indicate whether the positive threshold is stable under bias and temperature stress.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

3 major / 7 minor

Summary. The paper reports the fabrication and characterization of a normally-off (enhancement-mode) AlGaN/GaN MOSFET on a silicon substrate, using a 200 nm gate recess with 124 nm recess depth and a 30 nm Al2O3 gate dielectric. Three device variants with different recess depths and post-dielectric-anneal temperatures are compared; the optimized Device III shows a threshold voltage above 5 V and an on-current near 500 mA/mm. The authors also present three-terminal breakdown measurements and use Silvaco TCAD simulations to argue that residual electric-field penetration into the recess region limits the breakdown voltage of deeply scaled recess-gate devices.

Significance. If the reported data are reproducible, the paper provides a useful data point for normally-off GaN power devices: a simple 200 nm recess process on a silicon substrate achieving simultaneously a linear-extrapolation threshold voltage above 5 V and an on-current near 0.5 A/mm. The comparison table in Table I directly situates the result against prior work. The paper's central experimental claim is grounded in measured transfer and output characteristics rather than in simulation, and the TCAD analysis, while not fully matching the device geometry, represents a reasonable qualitative attempt to explain the observed limited breakdown. The main weaknesses are the absence of device statistics and the ambiguity in the definition and reporting of VTH, both of which affect the strength of the headline claim.

major comments (3)
  1. [Title, Abstract, Section III, Table I] The threshold-voltage value defining the headline claim is not consistently reported: the title says VTH > 5 V, the abstract says VTH = 5 V, Table I lists +5.1 V, and Section III (after Fig. 3(C)) says VTH was found to be '>5 V' after PMA. Because '>5 V' appears to be a display limit rather than an extracted value, and because no linear-extrapolation window or current-criterion is specified, the exact VTH of the reported device is ambiguous. Please define the extraction method precisely, report the extracted value for the measured device, and state whether 5.1 V is the extracted number used in Table I.
  2. [Section III, Figs. 3(C) and 4(C)] The central claim of on-current 500 mA/mm and VTH > 5 V rests on a single transfer curve and a single output family for Device III. No device-to-device statistics, error bars, or number of measured devices are reported, so it is not possible to determine whether the quoted values are representative of the process or a favorable single-device result. Please provide data from multiple devices and report the spread in VTH and on-current.
  3. [Section III, TCAD discussion and Fig. 6] The TCAD simulations use a recess depth of 35 nm (25 nm AlGaN + 10 nm GaN), whereas the fabricated Device III has a recess depth of 124 nm. The simulated electric-field profiles therefore do not represent the geometry of the device whose breakdown was measured, and the conclusion that residual field penetration into the recess causes premature breakdown is not directly supported. Please either simulate a 124 nm deep recess or justify explicitly why the 35 nm case captures the relevant physics for Device III.
minor comments (7)
  1. [Section II] The text 'samples were placed at an angle of 10 °C from the horizontal' should read '10°', since the unit is a degree of angle, not Celsius.
  2. [References] Reference [11] lists the journal as 'ACS Appl. Electrosn. Mater.'; the correct abbreviation is 'ACS Appl. Electron. Mater.'.
  3. [Fig. 3 caption] The symbol 'Lfp' is used in the Fig. 3 caption without being defined in the text; please define it.
  4. [Section III] The sentence 'The device III exhibited excellent on-current (500 mA/mm) and VTH (>5V) combinations reported till date' is grammatically incomplete; it should read '... the best combination of on-current and VTH reported to date'.
  5. [Conclusion] In the Conclusion, 'residuals electric fields' should be 'residual electric fields'.
  6. [Section III, TCAD paragraph] The material parameter sets 'kp.set2' and 'pol.set2' used in Silvaco ATLAS are not described; please provide references or parameter values so the simulation can be reproduced.
  7. [Fig. 2] The SEM image in Fig. 2 has no scale bar; please add one to allow the gate length and recess geometry to be verified.

Circularity Check

0 steps flagged · score 0.0 of 10

No circularity: the central performance claim is a directly measured experimental result, and no load-bearing derivation reduces to its inputs.

full rationale

The paper's central claim (Device III with VTH > 5 V and on-current near 500 mA/mm) is a directly measured electrical result from the transfer and output characteristics shown in Figs. 3(C) and 4(C). It is not obtained by fitting parameters to data and then predicting a closely related quantity, nor is VTH defined in terms of the measured on-current. The recess depth, post-dielectric anneal, and post-metal anneal conditions were varied and the resulting devices were measured, but the reported values are single-device measurements rather than outputs of a model whose inputs already contain the claimed result. The Silvaco TCAD simulations are used only to propose a qualitative breakdown mechanism, namely residual electric-field penetration into the recess region, and those simulations do not feed back into the headline VTH/on-current numbers. The self-citations [12]-[14] are invoked to interpret the observed VTH shift after post-metal annealing as an interface fixed-charge effect; this is background mechanistic attribution, not the load-bearing argument for the measured performance. The inconsistency among the abstract's '5 V', the title and body's '>5 V', and Table I's '+5.1 V' is a potential correctness or extraction-convention concern, but ambiguity in a measured threshold voltage is not circularity. Therefore no circular step is present.

Assumptions & free parameters 0 free parameters · 4 assumptions · 0 invented entities

The central contribution is an experimental result, so the ledger contains no fitted parameters in the derivation sense. The assumptions are the validity of the referenced epitaxial growth, the linear-extrapolation definition of VTH, the interpretation of PMA-induced fixed-charge changes, and the Silvaco material parameters used for the breakdown mechanism study. No new physical entities are introduced.

assumptions (4)
  • domain assumption The epitaxial stack grown on Si (ref [11]) has the assumed AlGaN barrier, GaN channel, and 2DEG properties used for device operation and simulation.
    The paper does not reproduce growth details; it references ref [11] for the epi-stack in Section II, and the 2DEG is central to the HEMT operation.
  • domain assumption The linear-extrapolation threshold voltage reported as VTH>5 V (or +5.1 V in Table I) is a standard and meaningful definition; the extraction method is not described.
    VTH is the headline metric, and Section III reports values without specifying the extrapolation procedure or error bar.
  • domain assumption Silvaco ATLAS material parameters kp.set2 and pol.set2 correctly represent the AlGaN/GaN/Al2O3 stack and support the breakdown mechanism conclusion.
    Section III states the parameters were used but no calibration against measured breakdown is shown; the simulated recess depth (35 nm) differs from Device III (124 nm).
  • domain assumption PMA-induced fixed-charge reduction at the Al2O3/GaN interface (refs 12-14) explains the observed VTH shifts.
    The VTH shift after PMA is attributed to interface fixed charge based on prior work; the paper does not measure interface charge directly.

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Cite this review

Pith. "Pith review of Deep sub micron normally off AlGaN/GaN MOSFET on silicon with VTH > 5V and On Current > 0.5 A/mm." pith.science (2026). https://pith.science/paper/ZL5D3CJN

@misc{pith2026190805853,
  author       = {Pith},
  title        = {Pith review of: Deep sub micron normally off AlGaN/GaN MOSFET on silicon with VTH > 5V and On Current > 0.5 A/mm},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/ZL5D3CJN}},
  note         = {Machine review of arXiv:1908.05853}
}
read the original abstract

We report on the demonstration of a deep sub-micron normally-off AlGaN/GaN HEMT with high on-current and high threshold voltage (VTH). The high-performance device was realized by utilizing a gate recess with length and depth of 200 nm and 124 nm respectively. The recess etched region had a roughness of 0.7 nm. Various recess etch depths and dielectric annealing conditions were used to tune the VTH. The optimized device exhibited on-current and VTH of 500 mA/mm and 5 V respectively. The measured breakdown characteristics of the devices and their limitations were investigated using 2D-TCAD device simulation. The penetration of the residual electric field in most of the recess region could be the reason for the premature breakdown of deeply scaled recess-gate e-mode HEMTs.

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Reference graph

Works this paper leans on

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