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A sparse spin qubit array with integrated control electronics

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arxiv 1912.06461 v1 pith:KDKPPRPM submitted 2019-12-13 quant-ph cond-mat.mes-hallphysics.app-ph

A sparse spin qubit array with integrated control electronics

classification quant-ph cond-mat.mes-hallphysics.app-ph
keywords controlelectronicsintegratedquantumqubitsparsearchitecturearray
verification ladder T0 review T1 audit T2 compute T3 formal T4 reserved
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Current implementations of quantum computers suffer from large numbers of control lines per qubit, becoming unmanageable with system scale up. Here, we discuss a sparse spin-qubit architecture featuring integrated control electronics significantly reducing the off-chip wire count. This quantum-classical hardware integration closes the feasibility gap towards a CMOS quantum computer.

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