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Superconducting-semiconducting voltage-tunable qubits in the third dimension

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arxiv 2203.06209 v1 pith:BJ7AVIBQ submitted 2022-03-11 quant-ph cond-mat.mes-hall

Superconducting-semiconducting voltage-tunable qubits in the third dimension

classification quant-ph cond-mat.mes-hall
keywords waferprobequbitstsvselectricfieldqubitsample
verification ladder T0 review T1 audit T2 compute T3 formal T4 reserved
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abstract

We propose superconducting-semiconducting (super-semi) qubit and coupler designs based on high-quality, compact through-silicon vias (TSVs). An interposer "probe" wafer containing TSVs is used to contact a sample wafer with, for example, a superconductor-proximitized, epitaxially-grown, germanium quantum well. By utilizing the capacitance of the probe wafer TSVs, the majority of the electric field in the qubits is pulled away from lossy regions in the semiconducting wafer. Through simulations, we find that the probe wafer can reduce the qubit's electric field participation in the sample wafer by an order of magnitude for thin substrates and remains small even when the epitaxial layer thickness approaches 100 $\mu$m. We also show how this scheme is extensible to multi-qubit systems which have tunable qubit-qubit couplings without magnetic fields. This approach shrinks the on-chip footprint of voltage-tunable superconducting qubits and promises to accelerate the understanding of super-semi heterostructures in a variety of systems.

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