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arxiv: 1804.01906 · v3 · pith:J5CAWYXZnew · submitted 2018-04-05 · 🧬 q-bio.NC · cs.ET· physics.bio-ph· physics.comp-ph

An Accelerated LIF Neuronal Network Array for a Large Scale Mixed-Signal Neuromorphic Architecture

classification 🧬 q-bio.NC cs.ETphysics.bio-phphysics.comp-ph
keywords arraycircuitnetworkacceleratedchipcircuitsdesigndesigned
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We present an array of leaky integrate-and-fire (LIF) neuron circuits designed for the second-generation BrainScaleS mixed-signal 65-nm CMOS neuromorphic hardware. The neuronal array is embedded in the analog network core of a scaled-down prototype HICANN-DLS chip. Designed as continuous-time circuits, the neurons are highly tunable and reconfigurable elements with accelerated dynamics. Each neuron integrates input current from a multitude of incoming synapses and evokes a digital spike event output. The circuit offers a wide tuning range for synaptic and membrane time constants, as well as for refractory periods to cover a number of computational models. We elucidate our design methodology, underlying circuit design, calibration and measurement results from individual sub-circuits across multiple dies. The circuit dynamics match with the behavior of the LIF mathematical model. We further demonstrate a winner-take-all network on the prototype chip as a typical element of cortical processing.

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Cited by 1 Pith paper

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    Authors apply a consistent methodology to benchmark physical performance metrics across neural network architectures and device technologies, identifying promising combinations.