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Co-Designed Superconducting Architecture for Lattice Surgery of Surface Codes with Quantum Interface Routing Card
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Co-Designed Superconducting Architecture for Lattice Surgery of Surface Codes with Quantum Interface Routing Card
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Facilitating the ability to achieve logical qubit error rates below physical qubit error rates, error correction is anticipated to play an important role in scaling quantum computers. While many algorithms require millions of physical qubits to be executed with error correction, current superconducting qubit systems contain only hundreds of physical qubits. One of the most promising codes on the superconducting qubit platform is the surface code, requiring a realistically attainable error threshold and the ability to perform universal fault-tolerant quantum computing with local operations via lattice surgery and magic state injection. Surface code architectures easily generalize to single-chip planar layouts, however space and control hardware constraints point to limits on the number of qubits that can fit on one chip. Additionally, the planar routing on single-chip architectures leads to serialization of commuting gates and strain on classical decoding caused by large ancilla patches. A distributed multi-chip architecture utilizing the surface code can potentially solve these problems if one can optimize inter-chip gates, manage collisions in networking between chips, and minimize routing hardware costs. We propose QuIRC, a superconducting Quantum Interface Routing Card for Lattice Surgery between surface code modules inside of a single dilution refrigerator. QuIRC improves scaling by allowing connection of many modules, increases ancilla connectivity of surface code lattices, and offers improved transpilation of Pauli-based surface code circuits. QuIRC employs in-situ Entangled Pair (EP) generation protocols for communication. We explore potential topological layouts of QuIRC based on superconducting hardware fabrication constraints, and demonstrate reductions in ancilla patch size by up to 77.8%, and in layer transpilation size by 51.9% when compared to the single-chip case.
Forward citations
Cited by 7 Pith papers
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Networked Realization of Quantum LDPC Codes
Networked bivariate bicycle QLDPC codes achieve competitive circuit-level performance to monolithic versions when Bell pair fidelity is high enough, based on Stim simulations with BP-OSD decoding.
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Impact of Network Constraints on Fault-Tolerant Distributed Quantum Computing
A modular end-to-end simulation framework jointly models surface-code operations, QPU connectivity, and network constraints to produce execution latency and logical error rate estimates, revealing network-dependent op...
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Heterogeneous architectures enable a 138x reduction in physical qubit requirements for fault-tolerant quantum computing under detailed accounting
Heterogeneous quantum architectures with task-specific hardware and QEC encodings deliver up to 138x lower physical-qubit overhead than monolithic baselines for fault-tolerant algorithms, including RSA-2048 factoring ...
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Architectural Approaches to Fault-Tolerant Distributed Quantum Computing and Their Entanglement Overheads
Three architectural types for fault-tolerant distributed quantum computing exhibit distinct scaling of Bell-pair consumption and generation attempts with code distance in planar surface and toric codes.
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Transversal Fault Tolerant Distributed Quantum Computing Operations
Simulations show non-local CNOT achieves up to 10x lower logical error than teleportation and distributed qLDPC needs d≈11 at p=10^{-4} or d≈29 at p=10^{-3} (with p_ebit=10p) for <10^{-12} error.
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Towards the Characterization of Logical Errors in Distributed Lattice Surgery
A simulated distributed XX merge of two surface-code patches keeps its fault-tolerance threshold near 0.83–0.87% even when shared Bell pairs are up to 11 times noisier than local gates.
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Fabless Quantum Chip Design and Commercial Production
Proposes a fabless-foundry ecosystem for superconducting quantum chips built on certified PDKs, SPICE-Q multiphysics modeling, parameterized cells, Q-EDA automation, and a quantum-IP market.
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