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A Survey on Hardware Accelerators for Large Language Models

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arxiv 2401.09890 v1 pith:4B7JXVAO submitted 2024-01-18 cs.AR cs.CLcs.LG

classification cs.ARcs.CLcs.LG
keywords languagellmsacceleratorshardwarelargemodelssurveycomputational
verification ladder T0 review T1 audit T2 compute T3 formal
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Large Language Models (LLMs) have emerged as powerful tools for natural language processing tasks, revolutionizing the field with their ability to understand and generate human-like text. As the demand for more sophisticated LLMs continues to grow, there is a pressing need to address the computational challenges associated with their scale and complexity. This paper presents a comprehensive survey on hardware accelerators designed to enhance the performance and energy efficiency of Large Language Models. By examining a diverse range of accelerators, including GPUs, FPGAs, and custom-designed architectures, we explore the landscape of hardware solutions tailored to meet the unique computational demands of LLMs. The survey encompasses an in-depth analysis of architecture, performance metrics, and energy efficiency considerations, providing valuable insights for researchers, engineers, and decision-makers aiming to optimize the deployment of LLMs in real-world applications.

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Cited by 2 Pith papers

Reviewed papers in the Pith corpus that reference this work. Sorted by Pith novelty score. Full citation record

  1. DECA: A Near-Core LLM Decompression Accelerator Grounded on a 3D Roofline Model

    cs.AR 2025-05 conditional novelty 7.0 of 10

    A near-core decompression accelerator plus a 3D roofline model speeds up compressed LLM matrix multiplication by up to 4x in simulation.

  2. Preserving Fairness and Safety in Quantized LLMs Through Critical Weight Protection

    cs.CL 2026-01 conditional novelty 5.0 of 10

    Quantization tends to degrade LLM fairness and safety—more in non-English tasks—and preserving top sensitivity-ranked weights in FP16 mostly mitigates the loss.

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