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Make Every Move Count: LLM-based High-Quality RTL Code Generation Using MCTS

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arxiv 2402.03289 v1 pith:6QPMTHOX submitted 2024-02-05 cs.LG cs.AIcs.AR

classification cs.LGcs.AIcs.AR
keywords codelanguagetransformercorrectdecodingfunctionallygenerationlarge
verification ladder T0 review T1 audit T2 compute T3 formal
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Existing large language models (LLMs) for register transfer level code generation face challenges like compilation failures and suboptimal power, performance, and area (PPA) efficiency. This is due to the lack of PPA awareness in conventional transformer decoding algorithms. In response, we present an automated transformer decoding algorithm that integrates Monte Carlo tree-search for lookahead, guiding the transformer to produce compilable, functionally correct, and PPA-optimized code. Empirical evaluation with a fine-tuned language model on RTL codesets shows that our proposed technique consistently generates functionally correct code compared to prompting-only methods and effectively addresses the PPA-unawareness drawback of naive large language models. For the largest design generated by the state-of-the-art LLM (16-bit adder), our technique can achieve a 31.8% improvement in the area-delay product.

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Cited by 9 Pith papers

Reviewed papers in the Pith corpus that reference this work. Sorted by Pith novelty score.

  1. RTLScout: Joint Agentic Code and Synthesis Optimization for Efficient Digital Circuits

    cs.AR 2026-06 unverdicted novelty 7.0 of 10

    RTLScout combines LLM-driven agentic RTL code optimization with synthesis and architecture sweeps to achieve 35% area and 45% delay reductions on a 16-bit IEEE-754 floating-point multiplier compared to baseline design...

  2. ARIADNE: Agentic Reward-Informed Adaptive Decision Exploration via Blackboard-Driven MCTS for Competitive Program Generation

    cs.SE 2026-05 unverdicted novelty 7.0 of 10

    ARIADNE combines blackboard architecture with MCTS to coordinate strategy, code, test, evaluation, and repair stages, yielding higher Pass@1 scores than prior LLM baselines on APPS, CodeContests, and related benchmarks.

  3. Dr. RTL: Autonomous Agentic RTL Optimization through Tool-Grounded Self-Improvement

    cs.AI 2026-04 unverdicted novelty 6.0 of 10

    Dr. RTL's multi-agent framework with group-relative skill learning achieves 21% WNS and 17% TNS timing improvements plus 6% area reduction on 20 real-world RTL designs over commercial synthesis tools.

  4. ChipSeek: Optimizing Verilog Generation via EDA-Integrated Reinforcement Learning

    cs.AI 2025-07 unverdicted novelty 6.0 of 10

    ChipSeek is a hierarchical-reward reinforcement learning framework with Curriculum-Guided Dynamic Policy Optimization that integrates EDA simulator feedback to improve LLM-generated RTL code on both functional correct...

  5. From Concept to Practice: an Automated LLM-aided UVM Machine for RTL Verification

    cs.AR 2025-04 conditional novelty 6.0 of 10

    UVM^2 is an LLM-driven system that generates and refines UVM testbenches for RTL verification, reporting up to substantial time savings and average code/function coverage of 87.44%/89.58% on designs up to 1.6K lines, ...

  6. LLMs for Secure Hardware Design and Related Problems: Opportunities and Challenges

    cs.CR 2026-05 unverdicted novelty 3.0 of 10

    A review synthesizing opportunities and challenges of using LLMs for secure hardware design, EDA synthesis, and related security issues.

  7. LLMs for Secure Hardware Design and Related Problems: Opportunities and Challenges

    cs.CR 2026-05 unverdicted novelty 3.0 of 10

    A survey of LLM applications in secure hardware design covering EDA synthesis, vulnerability analysis, countermeasures, and educational uses.

  8. LLMs for Secure Hardware Design and Related Problems: Opportunities and Challenges

    cs.CR 2026-05 accept novelty 2.0 of 10

    LLMs enable RTL code generation and vulnerability analysis in hardware design but introduce data contamination and adversarial risks that require red-teaming and dynamic benchmarking.

  9. LLMs for Secure Hardware Design and Related Problems: Opportunities and Challenges

    cs.CR 2026-05 unverdicted novelty 1.0 of 10

    A survey of LLM applications in electronic design automation and hardware security, covering opportunities, vulnerabilities, and countermeasures.

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