Paper Citation Record · LEDGER

AnalogCoder: Analog Circuit Design via Training-Free Code Generation

As of 8 August 2026, this Paper Citation Record lists 0 of 0 outbound references and 10 inbound Pith citation observations for arXiv:2405.14918.

A citation records a reference. It does not transfer a finding from one paper to another.

pith.paper-citation-record.v1
2405.14918 v2

Coverage vector

measured 0 of 0 reference resolution

Typed states for the displayed outbound observations.

Source: paper_references, paper_reference_links

measured 10 of 10 standing notices

One-hop event checks from named stored sources.

Source: scholarly_work_events, retraction_status_cache, observed 2026-08-08T06:32:00.761636+00:00

measured 10 of 10 inbound itemization

Pith citing papers itemized under the disclosed page cap.

Source: paper_references, paper_reference_links, observed 2026-08-07T23:14:10.342424Z

measured 0 of 1 external citation measurements

A source-named dated measurement, never combined with another source.

Source: arxiv_reference, observed 2026-07-03T17:38:43.486750Z

Reference resolution

0 of 0 outbound references displayed

verified exact0
verified fuzzy0
unresolved0
parse uncertain0
malformed identifier0
metadata mismatch0

External citation measurements

No source-named external measurement is stored.

Outbound references

No outbound reference observations are available for this paper version.

Pith citing papers

Observation 62cf1f4f-bad5-4455-ae46-78bfb4aac613 · inbound

DICE: Device-level Integrated Circuits Encoder with Graph Contrastive Pretraining cites this paper.

DICE: Device-level Integrated Circuits Encoder with Graph Contrastive Pretraining AnalogCoder: Analog Circuit Design via Training-Free Code Generation

Reference 43

Resolution: unresolved; no resolver link, observed 2026-08-07T23:14:10.342424Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation d4c73ca4-336c-463d-bf4e-2775f86f2f60 · inbound

MenTeR: A fully-automated Multi-agenT workflow for end-to-end RF/Analog Circuits Netlist Design cites this paper.

MenTeR: A fully-automated Multi-agenT workflow for end-to-end RF/Analog Circuits Netlist Design AnalogCoder: Analog Circuit Design via Training-Free Code Generation

Reference 3

Resolution: unresolved; no resolver link, observed 2026-08-07T13:00:30.892457Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation ad858346-1080-4813-951b-e28b8b7bf7d7 · inbound

LaMAGIC2: Advanced Circuit Formulations for Language Model-Based Analog Topology Generation cites this paper.

LaMAGIC2: Advanced Circuit Formulations for Language Model-Based Analog Topology Generation AnalogCoder: Analog Circuit Design via Training-Free Code Generation

Reference 6

Resolution: unresolved; no resolver link, observed 2026-08-07T04:37:15.085206Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 1fff8344-93ce-4f0d-84f5-6f5b4517b759 · inbound

A Large Language Model-based Multi-Agent Framework for Analog Circuits' Sizing Relationships Extraction cites this paper.

A Large Language Model-based Multi-Agent Framework for Analog Circuits' Sizing Relationships Extraction AnalogCoder: Analog Circuit Design via Training-Free Code Generation

Reference 7

Resolution: unresolved; no resolver link, observed 2026-08-06T23:21:46.384747Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation a712ff91-b90e-4866-a9a0-70f02e0ce98e · inbound

DiffCkt: A Diffusion Model-Based Hybrid Neural Network Framework for Automatic Transistor-Level Generation of Analog Circuits cites this paper.

DiffCkt: A Diffusion Model-Based Hybrid Neural Network Framework for Automatic Transistor-Level Generation of Analog Circuits AnalogCoder: Analog Circuit Design via Training-Free Code Generation

Reference 10

Resolution: unresolved; no resolver link, observed 2026-08-06T21:21:13.380119Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 5e1600e6-534a-423e-aab4-7fc3754cf72f · inbound

White-Box Reasoning: Synergizing LLM Strategy and gm/Id Data for Automated Analog Circuit Design cites this paper.

White-Box Reasoning: Synergizing LLM Strategy and gm/Id Data for Automated Analog Circuit Design AnalogCoder: Analog Circuit Design via Training-Free Code Generation

Reference 5

Resolution: unresolved; no resolver link, observed 2026-08-05T22:36:52.984737Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 493ad0a8-a982-4662-9ad5-eccc39c3d159 · inbound

Frontier-Eng: Benchmarking Self-Evolving Agents on Real-World Engineering Tasks with Generative Optimization cites this paper.

Frontier-Eng: Benchmarking Self-Evolving Agents on Real-World Engineering Tasks with Generative Optimization AnalogCoder: Analog Circuit Design via Training-Free Code Generation

Reference 9

Resolution: verified exact; arxiv_id, observed 2026-05-11T09:05:57.743104Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-08T06:32:00.761636+00:00.

Observation f2841815-6ee4-42bb-825c-8b73da0355e1 · inbound

AnalogRetriever: Learning Cross-Modal Representations for Analog Circuit Retrieval cites this paper.

AnalogRetriever: Learning Cross-Modal Representations for Analog Circuit Retrieval AnalogCoder: Analog Circuit Design via Training-Free Code Generation

Reference 1

Resolution: verified exact; arxiv_id, observed 2026-05-11T20:31:14.180954Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-08T06:32:00.761636+00:00.

Observation e128115b-2e92-44c0-a336-be8b6449effd · inbound

SINA: A Fully Automated Circuit Schematic Image to Netlist Generator Using Artificial Intelligence cites this paper.

SINA: A Fully Automated Circuit Schematic Image to Netlist Generator Using Artificial Intelligence AnalogCoder: Analog Circuit Design via Training-Free Code Generation

Reference 7

Resolution: verified exact; arxiv_id, observed 2026-07-03T17:38:43.488584Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-08T06:32:00.761636+00:00.

Observation 99572825-eafe-44a9-aaac-ff6df7e26cd7 · inbound

SABLE: An NDA-Safe Closed-Loop LLM Framework for Analog Circuit Optimization in Industrial EDA Flows cites this paper.

SABLE: An NDA-Safe Closed-Loop LLM Framework for Analog Circuit Optimization in Industrial EDA Flows AnalogCoder: Analog Circuit Design via Training-Free Code Generation

Reference 7

Resolution: malformed identifier; no resolver link, observed 2026-07-12T00:33:59.659330Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.