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Optimal Layout-Aware CNOT Circuit Synthesis with Qubit Permutation
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Optimal Layout-Aware CNOT Circuit Synthesis with Qubit Permutation
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CNOT optimization plays a significant role in noise reduction for Quantum Circuits. Several heuristic and exact approaches exist for CNOT optimization. In this paper, we investigate more complicated variations of optimal synthesis by allowing qubit permutations and handling layout restrictions. We encode such problems into Planning, SAT, and QBF. We provide optimization for both CNOT gate count and circuit depth. For experimental evaluation, we consider standard T-gate optimized benchmarks and optimize CNOT sub-circuits. We show that allowing qubit permutations can further reduce up to 56% in CNOT count and 46% in circuit depth. In the case of optimally mapped circuits under layout restrictions, we observe a reduction up to 17% CNOT count and 19% CNOT depth.
Forward citations
Cited by 2 Pith papers
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Noise-Aware Synthesis of Quantum LDPC Encoder Circuits via Two-Sided Hamming Descent
Two-sided Hamming descent plus noise-aware routing and live-range scheduling cuts CSS LDPC encoder CNOT counts by 53.8% aggregate and improves preparation fidelity under circuit-level noise.
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Automated Circuit Depth Reduction of Quantum Subroutines via Compilation
A compiler automates constant-depth GHZ and CZ chains plus logarithmic-depth CNOT chains, trading higher gate counts for reduced depth in quantum subroutines.
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