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Implementation of scalable suspended superinductors

T0 review · 2 major / 5 minor · reviewed 2026-08-12 · deepseek-v4-flash

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Pith's one-line read A selective-etch framework suspends Josephson-junction-array superinductors above the substrate, cutting capacitance to ground by roughly 74% and raising a fluxonium's inductance by 87% while preserving coherence.

desk verdict A useful selective-etch fabrication result whose headline numbers rest on thin fits; the fixed-CJ worry in the stress test points the wrong way. read the letter →

arxiv 2411.10396 v1 pith:BWNI57BW submitted 2024-11-15 quant-ph

Christian Jünger , Trevor Chistolini , Long B. Nguyen , Hyunseong Kim , Larry Chen , Thomas Ersevim , William Livingston , Gerwin Koolstra
show 2 more authors
David I. Santiago Irfan Siddiqi
This is my paper · ORCID
classification quant-ph
keywords superinductorJosephsonjunctionarrayselectivesubstrateetchingXeF2fluxoniumqubitcapacitancetogroundsuspendedsuperconductingcircuitsQuantumPhaseModel
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

This paper introduces a fabrication method that selectively suspends superinductors—Josephson-junction arrays that provide very large inductance—above the silicon substrate in planar superconducting circuits, rather than etching the whole chip. A lithographically defined etch mask opens a window over the array, XeF2 vapor removes silicon only beneath it, and the released array curls upward, cutting its capacitance to ground by a mean of about 74% according to Quantum Phase Model fits. The same process yields a suspended fluxonium whose extracted characteristic inductance is 87% larger than that of its on-substrate neighbor on the same chip, with $T_1$ and $T_{2,\mathrm{Echo}}$ times in the tens of microseconds, comparable to leading on-substrate devices. If the claim holds, it offers a scalable route to the high-impedance circuit elements required by qubit designs such as fluxonium, blochnium, and 0-π qubits, and a way to study substrate-related loss by comparing suspended and on-substrate devices.

What carries the argument

The key mechanism is selective undercut etching of a strained aluminum film. A lithographically defined etch mask leaves a window over the Josephson-junction array; XeF2 vapor removes the silicon beneath it, and strain at the Al–Si interface makes the released array lift and curl away from the substrate, removing the dominant dielectric from the array's capacitive environment. The quantitative workhorse is the Quantum Phase Model (QPM), a capacitance-matrix Hamiltonian for a chain of Josephson junctions with capacitor paddles at its ends; the paper fits each array's fundamental frequency using the per-island ground capacitance $C_0$ as the only free parameter, with junction capacitance, paddle capacitances, and coupling capacitances taken from simulation or reference values. The reduction in $C_0$ between on-substrate and suspended devices is the paper's evidence that the method achieves its goal.

What would settle it

Measure at least two plasma-mode frequencies on the same suspended and on-substrate arrays and check whether one shared value of $C_0$ reproduces the full mode spectrum; if it does not, the claimed 74% capacitance reduction is not established.

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Extended reading notes

Core claim

The paper's central claim is that suspending only the inductive element—not the entire circuit—is a practical and scalable way to build higher-impedance superconducting devices. Using an etch mask and an oxygen-ashing removal step, the authors undercut selected Josephson-junction arrays with XeF2, leaving the rest of the chip pristine and protecting materials such as niobium that XeF2 would otherwise attack. Suspended resonators show internal quality factors around $3.6 \times 10^4$ and self-Kerr coefficients that follow the expected dependence on junction number. Fitting the Quantum Phase Model to the measured fundamental frequencies, the authors report a mean reduction of about 74% in the per-island capacitance to ground $C_0$; in a fluxonium qubit with a suspended array, the extracted characteristic inductance $L$ is 87% greater than that of the on-substrate device on the same chip. The measured coherence times remain comparable to state-of-the-art on-substrate fluxonium devices, which the authors attribute to the gentler cleaning required by fragile suspended structures rather than to the suspension itself.

Load-bearing premise

The load-bearing premise is that the measured ~74% reduction in capacitance to ground is genuine and not an artifact of the fitting routine: each array's single measured fundamental frequency is fitted with the ground capacitance $C_0$ as the only free parameter, while all other capacitances are taken from simulation or reference values, and any error in those values could change or erase the claimed reduction.

Editorial extensions

If this is right

  • Suspended arrays can be incorporated into wafer-scale planar fabrication without exposing the whole chip to the etchant, so XeF2-sensitive metals such as niobium can remain in the ground plane and other components.
  • A roughly 74% reduction in $C_0$ means a target impedance can be reached with a shorter array, which lowers the frequency of parasitic modes and reduces the device footprint.
  • The 87% inductance increase observed in the suspended fluxonium shows that etching alone can move devices into higher-impedance operating regimes.
  • If the coherence gap versus fully on-substrate devices is caused by the gentler cleaning, then critical-point drying or other liquid-free cleaning could close that gap in future runs.
  • The suspended/on-substrate pair on the same chip provides a controlled comparison for investigating substrate-mediated loss mechanisms such as dielectric loss, quasiparticle poisoning, and $1/f$ flux noise.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • The paper's single-mode $C_0$ extraction could be independently checked by measuring higher array modes; this is an editorial suggestion, not something the paper reports.
  • If the inductance increase is caused by etchant-induced barrier thickening or fluorination, the same etch chemistry might be usable as a post-fabrication junction-tuning step, though the paper does not test that.
  • The method's compatibility with protected niobium suggests it could extend to XeF2-sensitive high-kinetic-inductance films such as NbN or TiN as long as they are masked, but the paper does not demonstrate that combination.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

2 major / 5 minor

Summary. This paper reports a selective XeF2 etching process that suspends Josephson-junction arrays (and potentially other superinductors) above a silicon substrate while leaving surrounding on-substrate elements, such as Nb ground planes, intact. The authors fabricate and characterize two chips of JJ-array resonators and three fluxonium devices (one fully on-substrate, one on-substrate on an etched chip, and one suspended). The central quantitative claims are a mean reduction of approximately 74% in the fitted capacitance to ground C0 of the suspended arrays (Table S2) and an 87% increase in the extracted characteristic inductance L of a suspended fluxonium relative to an on-substrate neighbor (Section 'Suspended Fluxoniums'), while maintaining coherence times comparable to state-of-the-art on-substrate devices.

Significance. If the quantitative claims hold, the selective-etch framework is a useful advance: it allows suspended superinductors to be integrated into wafer-scale, Nb-based superconducting circuits, potentially enabling higher-impedance qubit architectures such as blochnium or 0-π qubits. The paper is careful in several respects: it provides extensive supplementary data, room-temperature wafer statistics, explicit acknowledgments of fit limitations, and a plausible path to improved cleaning via critical-point drying. The main unresolved issue is that the headline capacitance reduction is a fitted parameter rather than an independently measured quantity, and the inductance increase rests on a single device pair.

major comments (2)
  1. [Supplementary: Determining Ground Capacitance; Eq. (2), Tables S1-S2] The claimed mean 74% reduction in C0 is extracted by fitting each array's single measured fundamental frequency with C0 as the only free parameter, while fixing the junction capacitance CJ = 20 fF identically for on-substrate and etched arrays (Table S1). This is internally inconsistent with the paper's own explanation that XeF2 'effectively thickens the tunnel barrier' and may form AlFx (Section 'Suspended Fluxoniums'), since either mechanism would alter the junction capacitance CJ = εA/d entering Eq. (2). Because Eq. (2) depends on the ratio C0/(2CJ), the extracted C0 values for the two device types are not on the same footing if CJ differs between them; the 74% figure could be substantially different under a plausible change in CJ. The SI explicitly acknowledges that only the fundamental mode was fitted, so C0 cannot be separated from the many simulated and reference capacitances. I ask the authors to (i) measure or bound CJ for both device types (for example via multiple plasma modes or transmission-electron microscopy), (ii) provide a sensitivity analysis of the extracted C0 versus CJ, or (iii) reframe the result as a model-dependent estimate rather than a directly measured capacitance reduction.
  2. [Suspended Fluxoniums; Fig. 3] The claim that the suspended fluxonium has an 87% greater characteristic inductance L is based on a single suspended device (C) and a single on-substrate neighbor (B) on the same chip, with L derived from the fitted inductive energy EL of the fluxonium Hamiltonian. With one device per condition, the result carries no statistical uncertainty, and the extracted L could be sensitive to fit degeneracies among EJ, EC, and EL. Furthermore, the room-temperature array probing in the SI (Fig. S1) shows only a 21% increase in per-junction inductance after etching (0.91 nH to 1.10 nH), which is far smaller than the 87% qubit-level increase. The paper does not reconcile these two numbers. Please provide replicate devices or a quantitative discussion of uncertainties, and explain the relationship between the room-temperature junction inductance and the qubit-level extracted L.
minor comments (5)
  1. [Suspended Resonators / Conclusion] The conclusion states that the extracted self-Kerr coefficients exhibit 'excellent agreement with theory,' but the main text provides no theoretical curve or quantitative comparison, and Table I lists values without error bars. Please add a comparison to the expected scaling (e.g., from Ref. [46]) or soften the claim.
  2. [Table S2] Table S2 lists four etched C0 values but only three on-substrate values (with N=400 on-substrate marked N/A), while the text says 'of the three arrays measured on both devices.' Please clarify the exact pairing used to compute the mean 74% reduction, and report per-pair reductions.
  3. [Fig. S4] The caption of Fig. S4 contains a typo: 'Josesphson' should be 'Josephson'.
  4. [Suspended Resonators] The phrase 'excellent agreement with theory' is also used for the trend of self-Kerr coefficients with junction number, but the attenuation calibration is acknowledged to carry uncertainty; please state explicitly that the trend, not the absolute values, is the validated quantity.
  5. [Main text, Eq. (1)] The notation 'ω10 mode' is used without definition; please define it as the fundamental plasma mode of the array.

Circularity Check

0 steps flagged · score 0.0 of 10

No significant circularity: C0 and L are extracted parameters from standard, externally anchored circuit models, and the paper's own single-mode fit limitation is an accuracy caveat, not a circular step.

full rationale

The central quantitative claims, a ~74% reduction in C0 and an 87% increase in L, are obtained by extracting parameters from standard circuit models, not by predicting quantities that were themselves used as fit inputs. For C0, the paper uses the Quantum Phase Model (Eqs. 2-3) and states in the SI: "We use the ground capacitance, C0, as the free parameter, and we set the remaining variables from experimental measurements, referenced results, or simulated values as indicated in Tab. S1." The extracted C0 values in Table S2 are then compared between on-substrate and etched arrays. This is ordinary parameter extraction: the model and the fixed capacitances come from external literature, prior TEM data, and Ansys simulation, not from the claimed result. The SI explicitly acknowledges that "the fitting routine to extract C0 is only based on the experimentally measured fundamental frequency instead of fitting to multiple modes, as other work has done [41], so it relies upon many simulated and referenced values." That is a real underdetermination/accuracy limitation, but it is not circularity: a single-mode fit does not force the claimed 74% reduction to be whatever the paper wants; it merely leaves C0 potentially degenerate with the simulated/reference capacitances. The same logic applies to the fluxonium inductance increase: EL is fitted to the measured transition-frequency spectrum under the standard fluxonium Hamiltonian (Eq. 4), and the 87% figure is a comparison of fitted EL values for devices B and C on the same chip. The later proposed mechanism (XeF2 effectively thickening the tunnel barrier and possibly forming AlFx) is a post-hoc explanation, not a premise used in extracting EL. The self-citations in the paper (Refs. 12, 33, 50, 53, 58, 66) provide fabrication recipes, a TEM junction-thickness value, cleaning methods, and standard dispersive-shift formulas; none of them is a uniqueness theorem, an ansatz smuggled in as external fact, or an input equivalent to the claimed capacitance/inductance changes. The on-substrate versus suspended comparison is self-contained on-chip for the fluxonium case. Therefore, no load-bearing step reduces by construction to its own inputs, and no circular step is reported; the relevant concerns are model accuracy and parameter identifiability, which the paper itself flags, not circularity.

Assumptions & free parameters 3 free parameters · 5 assumptions · 0 invented entities

The central quantitative claims rest on fitted parameters C0 and EL, plus simulated capacitances. The models are standard but not independently verified in this paper; no new entities are introduced.

free parameters (3)
  • Ground capacitance C0 per array = 15-118 aF (depending on junction number and etch state, Table S2)
    Used as the single free parameter in the QPM fit to match the measured fundamental frequency of each array; the claimed 74% reduction is the difference between fitted C0 values.
  • Inductive energy EL (and derived inductance L) for each fluxonium = A: 0.73 GHz, B: 0.78 GHz, C: 0.42 GHz (spectroscopy fits)
    Extracted from fitting the fluxonium transition spectrum to Eq. 4; the 87% inductance increase for Device C is based on this fitted EL.
  • Line attenuation correction for photon number calibration = 0.85 dB
    Used to convert VNA power to average photon number for Kerr coefficient fits; acknowledged to carry uncertainty.
assumptions (5)
  • standard math Quantum Phase Model for JJ arrays (Eqs. 2-3) accurately describes the array modes and capacitances
    Adopted from Refs [40,41,47,48]; used to fit C0 from frequencies.
  • standard math Ambegaokar-Baratoff relation converts room-temperature normal-state resistance to critical current
    Used to translate probe resistances into junction inductance LJ (SI Eq. S5).
  • domain assumption The fluxonium Hamiltonian (Eq. 4) with linear EL is a valid model for the suspended array
    Used to extract EJ, EC, EL from qubit spectra; assumes the array behaves inductively and no extra modes affect the spectrum.
  • domain assumption Ansys-simulated capacitances (CS, CC, Cg) are accurate for both on-substrate and suspended geometries
    These simulated values are fixed inputs in the C0 extraction; any error shifts the fitted C0.
  • domain assumption Etching modifies only the JJ tunnel barrier (thickening/fluorination) and does not introduce additional loss channels
    Used to interpret the Qi reduction in suspended resonators as due to cleaning rather than etching (Section 'Suspended Resonators').

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Cite this review

Pith. "Pith review of Implementation of scalable suspended superinductors." pith.science (2026). https://pith.science/paper/BWNI57BW

@misc{pith2026241110396,
  author       = {Pith},
  title        = {Pith review of: Implementation of scalable suspended superinductors},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/BWNI57BW}},
  note         = {Machine review of arXiv:2411.10396}
}
read the original abstract

Superinductors have become a crucial component in the superconducting circuit toolbox, playing a key role in the development of more robust qubits. Enhancing the performance of these devices can be achieved by suspending the superinductors from the substrate, thereby reducing stray capacitance. Here, we present a fabrication framework for constructing superconducting circuits with suspended superinductors in planar architectures. To validate the effectiveness of this process, we systematically characterize both resonators and qubits with suspended arrays of Josephson junctions, ultimately confirming the high quality of the superinductive elements. In addition, this process is broadly compatible with other types of superinductors and circuit designs. Our results not only pave the way for scalable novel superconducting architectures but also provide the primitive for future investigation of loss mechanisms associated with the device substrate.

Figures

Figures reproduced from arXiv: 2411.10396 by the authors.

Figure 1
Figure 1. FIG. 1. Device fabrication. (a) Etching method schematic for selectively suspended fluxonium. The etch mask is shown in [PITH_FULL_IMAGE:figures/full_fig_p002_1.png] view at source ↗
Figure 2
Figure 2. FIG. 2. Characterization of Josephson junction arrays. [PITH_FULL_IMAGE:figures/full_fig_p003_2.png] view at source ↗
Figure 3
Figure 3. FIG. 3. Characterization of suspended fluxonium. (a) Tran [PITH_FULL_IMAGE:figures/full_fig_p004_3.png] view at source ↗

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Pith tools

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