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BOSS: Blocking algorithm for optimizing shuttling scheduling in Ion Trap

T0 review · 5 major / 5 minor · reviewed 2026-08-11 · deepseek-v4-flash

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Pith's one-line read BOSS, a blocking algorithm for trapped-ion TILT compilation, cuts shuttle operations by up to 96.1% on benchmark circuits by grouping gates into execution-zone-sized blocks and scheduling qubit movement in half-zone chunks.

desk verdict A genuinely new blocking heuristic for TILT compilation with plausible shuttle reductions, but the headline numbers cannot be trusted until the baseline reimplementation and the distance model in Eq. (9) are made reproducible. read the letter →

arxiv 2412.03443 v1 pith:C2X4SHXF submitted 2024-12-04 quant-ph cs.AR

Xian Wu , Chenghong Zhu , Jingbo Wang , Xin Wang This is my paper · ORCID
classification quant-phcs.AR MSC 68Q1281P68 PACS 03.67.Lx
keywords quantumcompilationtrapped-ioncomputingTILTarchitectureshuttlingschedulingcircuitblockingunion-findpartitioningexecutiontimeestimationsuccessrate
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

The paper argues that shuttling ions in a linear trapped-ion tape is the dominant source of fidelity loss and slowdown, and that compilation should therefore minimize shuttle count rather than gate count. It introduces BOSS, which cuts a circuit into blocks that fit inside the execution zone (AOM), then moves qubits in half-zone chunks so each shuttle carries as many needed qubits as possible. On seven benchmark applications with 64–78 qubits and AOM sizes 16 and 32, BOSS reduces shuttles by up to 96.1% compared with the prior TILT compiler, and cuts estimated execution time by up to 179.6x. It also evaluates success rates under sympathetic cooling, reporting higher fidelity than prior estimates. The broader claim is that blocking gives a scalable $O(ng)$ compilation path for TILT and future modular ion-trap systems.

What carries the argument

The load-bearing mechanism is block decomposition plus half-zone shuttling. First, the dependency graph's frontier is processed FIFO, and two-qubit gates are merged into a group when their qubit-index union stays within the AOM size; groups are emitted as blocks, which the paper argues lowers the vacancy rate of qubits in the execution zone. Second, for each block, Algorithm 3 selects the middle index of the block's qubits on the tape and shuttles the left half to the right of it and the right half to the left, requiring at most $\lceil d/(m-k)\rceil$ shuttles for moving $k$ qubits distance $d$, and bounding total shuttles between blocks by $2nL/m$ with at most $\lfloor m/2\rfloor$ swap gates per shuttle. This combination gives $O(ng)$ overall compilation time and turns shuttle reduction into a structural property of the scheduling, not a per-gate heuristic.

What would settle it

Compile the SQRT benchmark with AOM size 32 using the original TILT compiler of [77] and count shuttle operations; if that count is materially below the 76 shuttles reported as the previous result, the claimed 96.1% reduction is inflated.

Watch

Extended reading notes

Core claim

The paper's central claim is that on a linear trapped-ion tape (TILT) architecture, the number of shuttle operations—not the number of gates—is the quantity a compiler should minimize, because each shuttle heats the ion chain and adds error. BOSS does this by partitioning the circuit's dependency graph into blocks of at most $m$ qubits, where $m$ is the AOM execution-zone size, using a union-find/FIFO grouping; it then schedules each block by moving the left and right halves of the required qubits toward the block's middle index, so no shuttle carries more than $\lfloor m/2\rfloor$ ions. On seven applications with 64–78 qubits and AOM sizes 16 and 32, the method reduces shuttle count by up to 96.1% (SQRT, AOM 32) and cuts estimated execution time by up to 179.6x (SQRT, AOM 16) versus the prior TILT compiler. The paper further estimates success rates under sympathetic cooling and reports substantially higher success rates than prior estimates, because fewer shuttles mean less accumulated error.

Load-bearing premise

The reported reductions are measured against the authors' own reimplementation of the prior TILT compiler, which is not shipped; if that reimplementation is suboptimal or uses a different distance model, the headline improvements would be overstated.

Editorial extensions

If this is right

  • Most benchmark circuits compile to fewer shuttles, with a maximum reduction of 96.1% and an average of 16.6% fewer shuttles than the prior TILT compiler.
  • Compilation time scales as $O(ng)$; the paper shows a 180-qubit QFT compiling in under 1.2 seconds, while the prior method took over 60 seconds for a 64-qubit QFT.
  • Estimated execution times fall by up to 179.6x and on average 61.5x, mainly because more gates execute during each visit of the execution zone, reducing idle qubit time.
  • Estimated success rates improve sharply; for example, QFT at AOM 16 exceeds $4\times 10^{-3}$, while the prior model put it below $1\times 10^{-14}$, because shuttle-induced error is lowered.
  • The improvement is not uniform: on RCS at AOM 32 BOSS uses 21 shuttles versus 11 for the prior method, and BOSS sometimes inserts more swap gates (336 vs 120 for QFT at AOM 16), a cost the paper argues is outweighed by the shuttle reduction.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • An extension left implicit is that the same dependency-graph blocking pass could serve as an inner scheduler for multi-zone or QCCD ion-trap layouts, where each linear tape segment is compiled by BOSS and inter-segment transport is handled separately.
  • Because the paper's FIFO grouping is one of many possible partitioning strategies, replacing step 7 of Algorithm 2 with a heuristic that anticipates the next block's qubit positions could cut shuttles further while keeping the same $O(ng)$ complexity.
  • A direct hardware measurement of whether fidelity loss scales with shuttle count rather than shuttle distance would determine how much of the reported success-rate gain transfers to real devices.
  • If gate fidelity degrades more slowly with execution-zone size than the $N^2$ model assumed, the shuttle reduction becomes the dominant error term and BOSS's relative advantage over the previous compiler would widen as technology improves.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

5 major / 5 minor

Summary. The manuscript proposes BOSS, a blocking-based compiler for the linear-tape trapped-ion (TILT) architecture. The compiler first partitions a circuit's two-qubit gates into blocks of at most Z qubits using a union-find-style greedy procedure (Algorithm 2), then schedules each block by moving ions so that the block's qubits lie within the AOM execution zone (Algorithm 3). The authors report reductions in shuttle count, compilation time, and estimated execution time relative to the prior TILT compiler [77] on seven benchmark circuits, with claimed maximum reductions of 96.1% in shuttles and 179.6x in execution time, together with a success-rate analysis based on new gate and shuttle fidelity models.

Significance. If the quantitative claims are reliable, the blocking idea is a useful and plausible contribution: it is simple, has claimed O(ng) complexity versus O(ng^2) for [77], is evaluated on standard benchmarks, and extends prior compilation work with explicit execution-time and cooling models. The comparison is not circular, since BOSS outputs are compared with independent benchmarks and a baseline, but the baseline itself is not reproducible from the text, and several internal numerical inconsistencies affect the headline numbers. The core algorithmic concept of grouping gates into AOM-sized blocks to reduce shuttling is worth serious consideration, provided the comparison is made reproducible and the reported aggregates are corrected.

major comments (5)
  1. [Section V, Table II] The 'Previous' columns (Tpre, Spre, tpre) are load-bearing for every headline claim, but the manuscript never states whether these numbers come from the original TILT implementation [77], from a reimplementation by the authors, or from a third-party implementation. No code or artifact is provided, and the previous compiler's swap-insertion heuristic is only summarized in Section III.B rather than specified. Without a faithful and stated baseline, the claimed 96.1% shuttle reduction and 179.6x execution-time improvement cannot be evaluated. Please state the provenance of these numbers, describe or reference the exact baseline algorithm used, and ship an artifact or detailed pseudocode.
  2. [Section V.B, Eq. (9)] The term 'dist' in Eq. (9) is undefined. The text says only that 'dist is the total shuttle distance'; the units, how the distance is accumulated over a schedule, and whether it is computed identically for BOSS and the baseline are not given. Figure 1's caption states that in TILT 'each shuttle enables the tape to move any distance,' which makes a distance-proportional time model ambiguous. Since the tpre/tboss ratios in Table II depend on this term, the execution-time improvements are not checkable. Define dist operationally (for example, the sum over shuttles of the tape displacement in ion spacings, converted to micrometers) and provide the per-benchmark values used.
  3. [Section I and Table II] The abstract and introduction claim an average shuttle reduction of 16.6%, but no reasonable aggregation of Table II yields this number. The arithmetic mean of the 14 per-benchmark DeltaS/Spre percentages is about 18.1%; excluding the two RCS rows gives about 33.9%; and the total shuttle count falls from 626 to 322, a 48.6% reduction. In addition, the SQRT/AOM32 row reports tpre=40.817s and tboss=0.207s with tpre/tboss=107.1, but 40.817/0.207 is approximately 197.2, which would exceed the claimed maximum of 179.6. These inconsistencies suggest the numbers in Table II and the summary statistics were not cross-checked; please correct them and state explicitly how the average improvement is computed.
  4. [Section V.C, Eqs. (10)-(12)] The success-rate model is internally inconsistent. Eq. (11) defines Fshuttle = 1 - epsilon_shuttle * m, and Eq. (12) then multiplies product_{m=1}^{S}(1 - epsilon_shuttle * m), so each successive shuttle has a larger error; this is not the usual per-shuttle error model and should be justified. The text in Section V.C.a also says 'the fidelity of a single shuttle operation decreases linearly with the number of times it is performed,' which appears to contradict a constant per-shuttle error and is not what Eq. (11) states. The claim in Section V.C.b that for QFT/AOM16 the previous success rate is below 1e-14 while BOSS exceeds 4e-3 is not supported by any figure or table that includes the previous method. Please clarify the model, report per-benchmark success rates for both methods, and state explicitly that epsilon_laser and epsilon_shuttle are hand-set parameters.
  5. [Section III.C, Algorithm 3] The scheduling algorithm is underspecified. The pseudocode moves 'the left half qubit of bi to the right of mi' without defining the TILT primitives used to reorder ions or the number and type of swap gates inserted; Figure 4 shows swap gates, but Algorithm 3 contains no swap-gate insertion. The statement that 'the swap gates that need to be introduced will not exceed floor(m/2) * s' is asserted without derivation. Since the shuttle-count reduction is the central mechanism, please give a complete formal description of the schedule, including how qubit order changes and how swap gates are counted, and prove the stated bounds.
minor comments (5)
  1. [Algorithm 2] The variable G is used both for the dependency graph and for the group list; these should be disambiguated to avoid confusion.
  2. [Algorithm 2] The pseudocode does not show how the dependency-graph frontier is updated after a gate is placed into a group; please complete the pseudocode so the control flow is unambiguous.
  3. [Section III.C] There is a typo 'ha euristic' (should be 'heuristic'), and the statement that the worst case requires at least Omega(4^(n-m)) shuttles is stated without a derivation and with unclear notation.
  4. [Section V.C.a] The sentence 'the fidelity of a single shuttle operation decreases linearly with the number of times it is performed' needs rewording; the mathematical statement should follow directly from the equation.
  5. [Section V.C.b] The phrase 'because we make good use of the cooling process' is misleading, since the success-rate model in Eqs. (10)-(12) contains no cooling term; the improvement should be attributed to fewer shuttles.

Circularity Check

0 steps flagged · score 0.0 of 10

No circularity: BOSS's shuttle reductions are empirical comparisons against an external TILT baseline; no fitted parameter is renamed as a prediction.

full rationale

The paper's central claim, that BOSS reduces the number of shuttles and improves execution time relative to the prior TILT compiler [77], is an empirical comparison against an external baseline. The shuttle counts are produced by Algorithms 1-3 applied to listed benchmark circuits, and Table II reports baseline, previous, and BOSS counts separately. No parameter is fitted to the shuttle-count or execution-time metrics that are subsequently reported as improvements: epsilon_laser and epsilon_shuttle are fixed simulation constants (1/256000 and 0.001), and Eq. (12) merely multiplies gate and shuttle fidelities according to an explicit noise model. The only self-citation ([56]) appears in a list of similar blocking and circuit-knitting strategies and is not load-bearing for the BOSS result. Concerns about the unshipped reimplementation of [77] and the operationally undefined 'dist' in Eq. (9) bear on reproducibility and fair comparison, not on circularity: the baseline comparison could be inaccurate, but it is not true by construction. No equation defines its output in terms of the claimed metric, and no fitted input is relabeled as a prediction. Therefore the derivation chain is self-contained with respect to circularity, and the score is 0.

Assumptions & free parameters 2 free parameters · 4 assumptions · 0 invented entities

The paper's quantitative claims depend on three hand-set modeling choices (epsilon_laser, epsilon_shuttle) and on the TILT movement model. No new physical entities are introduced. The free parameters directly control the success-rate and execution-time claims.

free parameters (2)
  • epsilon_laser = 1/256000
    Set by hand in Section V.C.a so that a two-qubit gate achieves 99.9% fidelity with AOM size 16 (Fgate = 1 - epsilon_laser*N^2). This parameter directly controls the success-rate comparison in Eq. (12).
  • epsilon_shuttle = 0.001
    Set by hand in Section V.C.a to model residual ion-phonon entanglement per shuttle (Fshuttle = 1 - epsilon_shuttle*m). It linearizes fidelity loss with shuttle count and feeds Eq. (12).
assumptions (4)
  • domain assumption In the TILT architecture, gates can only be applied to qubits inside a contiguous execution zone of size m, and a shuttle can move the tape any distance.
    Stated in Sections II.D and III.C.b (Figure 1). The entire compilation problem is defined by this model; if real TILT hardware has limited tape travel per shuttle or non-contiguous zones, the algorithm and its bounds change.
  • domain assumption All gates grouped into one block are mutually independent and can be executed simultaneously within the execution zone.
    Algorithm 2 groups gates from the dependency-graph frontier, so gates sharing a qubit are not placed in the same block; however, the paper does not prove this invariant explicitly. The schedule 'execute bi' treats the block as a single multi-qubit operation.
  • ad hoc to paper Fidelity of a two-qubit gate scales as Fgate = 1 - epsilon_laser*N^2 and shuttle fidelity as Fshuttle = 1 - epsilon_shuttle*m, with linear accumulation.
    Eqs. (10)-(12) in Section V.C.a. This is a simplified model introduced for this paper, with constants set by hand; it is not derived from first principles or from a specific experimental dataset.
  • domain assumption A tape moving k<m qubits a distance d costs ceil(d/(m-k)) shuttles.
    Section III.C.b, used to derive the 2nL/m upper bound on shuttle count. This assumes the tape can translate any subset of ions in a single move and that only the separation between leftmost and rightmost qubits matters.

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Cite this review

Pith. "Pith review of BOSS: Blocking algorithm for optimizing shuttling scheduling in Ion Trap." pith.science (2026). https://pith.science/paper/C2X4SHXF

@misc{pith2026241203443,
  author       = {Pith},
  title        = {Pith review of: BOSS: Blocking algorithm for optimizing shuttling scheduling in Ion Trap},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/C2X4SHXF}},
  note         = {Machine review of arXiv:2412.03443}
}
read the original abstract

Ion traps stand at the forefront of quantum hardware technology, presenting unparalleled benefits for quantum computing, such as high-fidelity gates, extensive connectivity, and prolonged coherence times. In this context, we explore the critical role of shuttling operations within these systems, especially their influence on the fidelity loss and elongated execution times. To address these challenges, we have developed BOSS, an efficient blocking algorithm tailored to enhance shuttling efficiency. This optimization not only bolsters the shuttling process but also elevates the overall efficacy of ion trap devices. We experimented on multiple applications using two qubit gates up to 4000+ and qubits ranging from 64 to 78. Our method significantly reduces the number of shuttles on most applications, with a maximum reduction of 96.1%. Additionally, our investigation includes simulations of realistic experimental parameters that incorporate sympathetic cooling, offering a higher fidelity and a refined estimate of execution times that align more closely with practical scenarios.

Figures

Figures reproduced from arXiv: 2412.03443 by the authors.

Figure 1
Figure 1. Linear Trapped-Ion quantum computer. Qubits within the Acousto [PITH_FULL_IMAGE:figures/full_fig_p003_1.png] view at source ↗
Figure 2
Figure 2. Overview of this work. In section III-C, we will propose algorithms to minimize the number of shuttling numbers in order to prevent the heating error and achieve a higher success rate for the quantum program. In section V, the evaluation of the method is conducted through the enumeration of shuttles, evaluation of the success rate and estimation of the execution time. The noise model that we have taken into account … view at source ↗
Figure 4
Figure 4. An example of block scheduling. We will execute the block once it has all of the qubits needed inside the execution zone. Otherwise, we will use [PITH_FULL_IMAGE:figures/full_fig_p006_4.png] view at source ↗
Figures from the paper (5 more)
Figure 5
Figure 5. Figure 5: An example of how to move selected qubits. Consider we need to [PITH_FULL_IMAGE:figures/full_fig_p006_5.png]
Figure 6
Figure 6. Figure 6: Number of shuttling operations (Lower the better). [PITH_FULL_IMAGE:figures/full_fig_p008_6.png]
Figure 7
Figure 7. Figure 7: A comparative analysis of the execution time with previous work [77] utilizing AM gate implementation [73]. [PITH_FULL_IMAGE:figures/full_fig_p009_7.png]
Figure 8
Figure 8. Figure 8: Time evaluation on different applications with Duan, Trout AM gate and PM gate implementation. Circuits with a high percentage of short-distance [PITH_FULL_IMAGE:figures/full_fig_p010_8.png]
Figure 10
Figure 10. Figure 10: The compilation time varies with the size of the circuit. The circuit [PITH_FULL_IMAGE:figures/full_fig_p011_10.png]

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Reference graph

Works this paper leans on

85 extracted references · 59 canonical work pages · cited by 3 Pith papers

  1. [78]

    Ilp-based scheduling for linear-tape model trapped-ion quantum computers,

    X.-C. Wu, Y . Ding, Y . Shi, Y . Alexeev, H. Finkel, K. Kim, and F. T. Chong, “Ilp-based scheduling for linear-tape model trapped-ion quantum computers,” in the Proceedings of The International Conference for High Performance Computing, Networking, Storage, and Analysis, Denver Co, 2019

    2019

  2. [77]

    Tilt: Achieving higher fidelity on a trapped-ion linear- tape quantum computing architecture,

    X.-C. Wu, D. M. Debroy, Y . Ding, J. M. Baker, Y . Alexeev, K. R. Brown, and F. T. Chong, “Tilt: Achieving higher fidelity on a trapped-ion linear- tape quantum computing architecture,” in 2021 IEEE International Sym- posium on High-Performance Computer Architecture (HPCA) . IEEE, 2021, pp. 153–166

    2021

  3. [1]

    A high-fidelity quantum matter-link between ion-trap microchip modules,

    M. Akhtar, F. Bonus, F. Lebrun-Gallagher, N. Johnson, M. Siegele- Brown, S. Hong, S. Hile, S. Kulmiya, S. Weidt, and W. Hensinger, “A high-fidelity quantum matter-link between ion-trap microchip modules,” Nature Communications, vol. 14, no. 1, p. 531, 2023

    2023

  4. [2]

    Qiskit: An open-source framework for quantum computing,

    G. Aleksandrowicz, T. Alexander, P. Barkoutsos, L. Bello, Y . Ben-Haim, D. Bucher, F. J. Cabrera-Hern ´andez, J. Carballo-Franquis, A. Chen, C.-F. Chen et al. , “Qiskit: An open-source framework for quantum computing,” Accessed on: Mar , vol. 16, 2019

    2019

  5. [3]

    Quantum supremacy using a programmable superconducting processor,

    F. Arute, K. Arya, R. Babbush, D. Bacon, J. C. Bardin, R. Barends, R. Biswas, S. Boixo, F. G. Brandao, D. A. Buell et al. , “Quantum supremacy using a programmable superconducting processor,” Nature, vol. 574, no. 7779, pp. 505–510, 2019

    2019

  6. [4]

    High-fidelity quantum logic gates using trapped-ion hyperfine qubits,

    C. Ballance, T. Harty, N. Linke, M. Sepiol, and D. Lucas, “High-fidelity quantum logic gates using trapped-ion hyperfine qubits,” Physical review letters, vol. 117, no. 6, p. 060504, 2016

    2016

  7. [5]

    Towards fault- tolerant quantum computing with trapped ions,

    J. Benhelm, G. Kirchmair, C. F. Roos, and R. Blatt, “Towards fault- tolerant quantum computing with trapped ions,” Nature Physics, vol. 4, no. 6, pp. 463–466, 2008

    2008

  8. [6]

    Quantum complexity theory,

    E. Bernstein and U. Vazirani, “Quantum complexity theory,” in Proceed- ings of the twenty-fifth annual ACM symposium on Theory of computing , 1993, pp. 11–20

    work page 1993

Show all 85 references
  1. [7]

    A quantum processor based on coherent transport of entangled atom arrays,

    D. Bluvstein, H. Levine, G. Semeghini, T. T. Wang, S. Ebadi, M. Kali- nowski, A. Keesling, N. Maskara, H. Pichler, M. Greiner et al. , “A quantum processor based on coherent transport of entangled atom arrays,” Nature, vol. 604, no. 7906, pp. 451–456, 2022

    2022

  2. [8]

    Materials chal- lenges for trapped-ion quantum computers,

    K. R. Brown, J. Chiaverini, J. M. Sage, and H. H ¨affner, “Materials chal- lenges for trapped-ion quantum computers,” Nature Reviews Materials , vol. 6, no. 10, pp. 892–905, 2021

    2021

  3. [9]

    Trapped- ion quantum computing: Progress and challenges,

    C. D. Bruzewicz, J. Chiaverini, R. McConnell, and J. M. Sage, “Trapped- ion quantum computing: Progress and challenges,” Applied Physics Reviews, vol. 6, no. 2, 2019

    2019

  4. [10]

    Trapped-ion quantum computing: Progress and challenges,

    C. D. Bruzewicz, J. Chiaverini, R. McConnell, and J. M. Sage, “Trapped-ion quantum computing: Progress and challenges,” Applied Physics Reviews , vol. 6, no. 2, May 2019. [Online]. Available: http://dx.doi.org/10.1063/1.5088164

    2019 doi

  5. [11]

    Approximate quantum circuit synthesis using block encodings,

    D. Camps and R. Van Beeumen, “Approximate quantum circuit synthesis using block encodings,” Physical Review A , vol. 102, no. 5, p. 052411, 2020

    2020

  6. [12]

    Efficient-sideband-cooling protocol for long trapped-ion chains,

    J.-S. Chen, K. Wright, N. Pisenti, D. Murphy, K. Beck, K. Landsman, J. Amini, and Y . Nam, “Efficient-sideband-cooling protocol for long trapped-ion chains,” Physical Review A , vol. 102, no. 4, p. 043110, 2020

    2020

  7. [13]

    Benchmarking a trapped-ion quantum computer with 29 algorithmic qubits,

    J.-S. Chen, E. Nielsen, M. Ebert, V . Inlek, K. Wright, V . Chaplin, A. Maksymov, E. P ´aez, A. Poudel, P. Maunz et al. , “Benchmarking a trapped-ion quantum computer with 29 algorithmic qubits,” arXiv preprint arXiv:2308.05071, 2023

    2023 arXiv

  8. [14]

    Ultrasonic imaging transceiver design for cmut: A three-level 30-vpp pulse-shaping pulser with improved efficiency and a noise-optimized receiver,

    K. Chen, H.-S. Lee, A. P. Chandrakasan, and C. G. Sodini, “Ultrasonic imaging transceiver design for cmut: A three-level 30-vpp pulse-shaping pulser with improved efficiency and a noise-optimized receiver,” IEEE Journal of Solid-State Circuits , vol. 48, no. 11, pp. 2734–2745, 2013

    2013

  9. [15]

    Epoc: A novel pulse generation framework incorporating advanced synthesis techniques for quantum circuits,

    J. Cheng, Y . Zhu, Y . Zhou, H. Ren, Z. Song, and Z. Liang, “Epoc: A novel pulse generation framework incorporating advanced synthesis techniques for quantum circuits,” arXiv preprint arXiv:2405.03804 , 2024

    2024 arXiv

  10. [16]

    Optimal quantum control of multimode couplings between trapped ion qubits for scalable entanglement,

    T. Choi, S. Debnath, T. A. Manning, C. Figgatt, Z.-X. Gong, L.-M. Duan, and C. Monroe, “Optimal quantum control of multimode couplings between trapped ion qubits for scalable entanglement,” Phys. Rev. Lett. , vol. 112, p. 190502, May 2014. [Online]. Available: https://link.aps...

    2014 doi

  11. [17]

    Quantum computations with cold trapped ions,

    J. I. Cirac and P. Zoller, “Quantum computations with cold trapped ions,” Physical review letters, vol. 74, no. 20, p. 4091, 1995

    1995

  12. [18]

    A new quantum ripple-carry addition circuit,

    S. A. Cuccaro, T. G. Draper, S. A. Kutin, and D. P. Moulton, “A new quantum ripple-carry addition circuit,” arXiv preprint quant-ph/0410184, 2004

    2004 arXiv

  13. [19]

    A quantum approximate optimization algorithm,

    E. Farhi, J. Goldstone, and S. Gutmann, “A quantum approximate optimization algorithm,” arXiv preprint arXiv:1411.4028 , 2014

    2014 arXiv

  14. [20]

    The quantum ap- proximate optimization algorithm and the sherrington-kirkpatrick model at infinite size,

    E. Farhi, J. Goldstone, S. Gutmann, and L. Zhou, “The quantum ap- proximate optimization algorithm and the sherrington-kirkpatrick model at infinite size,” Quantum, vol. 6, p. 759, 2022

    2022

  15. [21]

    A modular quantum compila- tion framework for distributed quantum computing,

    D. Ferrari, S. Carretta, and M. Amoretti, “A modular quantum compila- tion framework for distributed quantum computing,” IEEE Transactions on Quantum Engineering , 2023

    2023

  16. [22]

    Optimized fast gates for quantum computing with trapped ions,

    E. P. Gale, Z. Mehdi, L. M. Oberg, A. K. Ratcliffe, S. A. Haine, and J. J. Hope, “Optimized fast gates for quantum computing with trapped ions,” Physical Review A , vol. 101, no. 5, p. 052328, 2020

    2020

  17. [23]

    Overhead-constrained circuit knitting for variational quantum dynamics,

    G. Gentinetta, F. Metz, and G. Carleo, “Overhead-constrained circuit knitting for variational quantum dynamics,” Quantum, vol. 8, p. 1296, 2024

    2024

  18. [24]

    Optimized quantum compilation for near-term algorithms with open- pulse,

    P. Gokhale, A. Javadi-Abhari, N. Earnest, Y . Shi, and F. T. Chong, “Optimized quantum compilation for near-term algorithms with open- pulse,” in 2020 53rd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO). IEEE, 2020, pp. 186–200

    2020

  19. [25]

    Google, “Cirq,” https://github.com/quantumlib/Cirq, 2023

    2023

  20. [26]

    Phase-modulated decoupling and error suppression in qubit-oscillator systems,

    T. J. Green and M. J. Biercuk, “Phase-modulated decoupling and error suppression in qubit-oscillator systems,” Physical review letters , vol. 114, no. 12, p. 120502, 2015

    2015

  21. [27]

    Efficient arbitrary simultaneously entangling gates on a trapped-ion quantum computer,

    N. Grzesiak, R. Bl ¨umel, K. Wright, K. M. Beck, N. C. Pisenti, M. Li, V . Chaplin, J. M. Amini, S. Debnath, J.-S. Chen et al. , “Efficient arbitrary simultaneously entangling gates on a trapped-ion quantum computer,” Nature communications, vol. 11, no. 1, p. 2963, 2020

    2020

  22. [28]

    Quantum computing with trapped ions,

    H. H ¨affner, C. F. Roos, and R. Blatt, “Quantum computing with trapped ions,” Physics reports, vol. 469, no. 4, pp. 155–203, 2008

    2008

  23. [29]

    Reinforcement learning and dear framework for solving the qubit mapping problem,

    C.-Y . Huang, C.-H. Lien, and W.-K. Mak, “Reinforcement learning and dear framework for solving the qubit mapping problem,” in Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022, pp. 1–9

    2022

  24. [30]

    Quantum advantage in learning from experiments,

    H.-Y . Huang, M. Broughton, J. Cotler, S. Chen, J. Li, M. Mohseni, H. Neven, R. Babbush, R. Kueng, J. Preskill et al., “Quantum advantage in learning from experiments,” Science, vol. 376, no. 6598, pp. 1182– 1186, 2022

    2022

  25. [31]

    Ionq harnesses single-atom qubits to build the world’s most powerful quantum computer,

    IONQ, “Ionq harnesses single-atom qubits to build the world’s most powerful quantum computer,” https://ionq.com/news/december-11-2018, Dec 2018

    2018

  26. [32]

    Scalable arrays of micro- penning traps for quantum computing and simulation,

    S. Jain, J. Alonso, M. Grau, and J. P. Home, “Scalable arrays of micro- penning traps for quantum computing and simulation,” Physical Review X, vol. 10, no. 3, p. 031027, 2020

    2020

  27. [33]

    Scaffcc: Scalable compilation and analysis of quantum programs,

    A. JavadiAbhari, S. Patil, D. Kudrow, J. Heckey, A. Lvov, F. T. Chong, and M. Martonosi, “Scaffcc: Scalable compilation and analysis of quantum programs,” Parallel Computing, vol. 45, pp. 2–17, 2015

    2015

  28. [34]

    Designing filter functions of frequency-modulated pulses for high-fidelity two-qubit gates in ion chains,

    M. Kang, Y . Wang, C. Fang, B. Zhang, O. Khosravani, J. Kim, and K. R. Brown, “Designing filter functions of frequency-modulated pulses for high-fidelity two-qubit gates in ion chains,” Physical Review Applied, vol. 19, no. 1, p. 014014, 2023

    2023

  29. [35]

    Shuttling-based trapped-ion quantum information processing,

    V . Kaushal, B. Lekitsch, A. Stahl, J. Hilder, D. Pijn, C. Schmiegelow, A. Bermudez, M. M ¨uller, F. Schmidt-Kaler, and U. Poschinger, “Shuttling-based trapped-ion quantum information processing,” AVS Quantum Science, vol. 2, no. 1, 2020

    2020

  30. [36]

    Quantum-assisted quantum compiling,

    S. Khatri, R. LaRose, A. Poremba, L. Cincio, A. T. Sornborger, and P. J. Coles, “Quantum-assisted quantum compiling,” Quantum, vol. 3, p. 140, 2019

    2019

  31. [37]

    Architecture for a large- scale ion-trap quantum computer,

    D. Kielpinski, C. Monroe, and D. J. Wineland, “Architecture for a large- scale ion-trap quantum computer,” Nature, vol. 417, no. 6890, pp. 709– 711, 2002

    2002

  32. [38]

    A. Y . Kitaev, A. Shen, and M. N. Vyalyi, Classical and quantum computation. American Mathematical Soc., 2002, no. 47

    2002

  33. [39]

    Suppression of heating rates in cryogenic surface-electrode ion traps,

    J. Labaziewicz, Y . Ge, P. Antohi, D. Leibrandt, K. R. Brown, and I. L. Chuang, “Suppression of heating rates in cryogenic surface-electrode ion traps,” Physical review letters, vol. 100, no. 1, p. 013001, 2008

    2008

  34. [40]

    Tackling the qubit mapping problem for nisq-era quantum devices,

    G. Li, Y . Ding, and Y . Xie, “Tackling the qubit mapping problem for nisq-era quantum devices,” in Proceedings of the Twenty-Fourth International Conference on Architectural Support for Programming Languages and Operating Systems , 2019, pp. 1001–1014

    2019

  35. [41]

    Experimental comparison of two quantum computing architectures,

    N. M. Linke, D. Maslov, M. Roetteler, S. Debnath, C. Figgatt, K. A. Landsman, K. Wright, and C. Monroe, “Experimental comparison of two quantum computing architectures,” Proceedings of the National Academy of Sciences , vol. 114, no. 13, p. 3305–3310, Mar. 2017. [Online]. Avai...

    2017 doi

  36. [42]

    Analytical and experimental study of center-line miscalibrations in molmer-sorensen gates,

    F. Martinez-Garcia, L. Gerster, D. V odola, P. Hrmo, T. Monz, P. Schindler, and M. Muller, “Analytical and experimental study of center-line miscalibrations in molmer-sorensen gates,” Physical Review A, vol. 105, no. 3, p. 032437, 2022

    2022

  37. [43]

    An outlook for quantum computing [point of view],

    D. Maslov, Y . Nam, and J. Kim, “An outlook for quantum computing [point of view],” Proceedings of the IEEE , vol. 107, no. 1, pp. 5–10, 2018

    2018

  38. [44]

    Integrated optical addressing of an ion qubit,

    K. K. Mehta, C. D. Bruzewicz, R. McConnell, R. J. Ram, J. M. Sage, and J. Chiaverini, “Integrated optical addressing of an ion qubit,” Nature nanotechnology, vol. 11, no. 12, pp. 1066–1070, 2016

    2016

  39. [45]

    Phase-modulated entangling gates robust to static and time- varying errors,

    A. R. Milne, C. L. Edmunds, C. Hempel, F. Roy, S. Mavadia, and M. J. Biercuk, “Phase-modulated entangling gates robust to static and time- varying errors,” Physical Review Applied , vol. 13, no. 2, p. 024022, 2020

    2020

  40. [46]

    Large-scale modular quantum-computer architecture with atomic memory and photonic interconnects,

    C. Monroe, R. Raussendorf, A. Ruthven, K. R. Brown, P. Maunz, L.-M. Duan, and J. Kim, “Large-scale modular quantum-computer architecture with atomic memory and photonic interconnects,” Phys. Rev. A , vol. 89, p. 022317, Feb 2014. [Online]. Available: https://link.aps.org/doi/1...

    2014 doi

  41. [47]

    Scaling the ion trap quantum processor,

    C. Monroe and J. Kim, “Scaling the ion trap quantum processor,” Science, vol. 339, no. 6124, pp. 1164–1169, 2013

    2013

  42. [48]

    Scalable digital hardware for a trapped ion quantum computer,

    E. Mount, D. Gaultney, G. Vrijsen, M. Adams, S.-Y . Baek, K. Hudek, L. Isabella, S. Crain, A. van Rynbach, P. Maunz et al., “Scalable digital hardware for a trapped ion quantum computer,” Quantum Information Processing, vol. 15, pp. 5281–5298, 2016

    2016

  43. [49]

    Archi- tecting noisy intermediate-scale trapped ion quantum computers,

    P. Murali, D. M. Debroy, K. R. Brown, and M. Martonosi, “Archi- tecting noisy intermediate-scale trapped ion quantum computers,” in 2020 ACM/IEEE 47th Annual International Symposium on Computer Architecture (ISCA). IEEE, 2020, pp. 529–542

    2020

  44. [50]

    High-fidelity readout of trapped-ion qubits,

    A. Myerson, D. Szwer, S. Webster, D. Allcock, M. Curtis, G. Imreh, J. Sherman, D. Stacey, A. Steane, and D. Lucas, “High-fidelity readout of trapped-ion qubits,” Physical Review Letters , vol. 100, no. 20, p. 200502, 2008

    2008

  45. [51]

    Enabling pulse-level programming, compilation, and execution in xacc,

    T. Nguyen and A. McCaskey, “Enabling pulse-level programming, compilation, and execution in xacc,” IEEE Transactions on Computers , vol. 71, no. 3, pp. 547–558, 2021

    2021

  46. [52]

    M. A. Nielsen and I. L. Chuang, Quantum computation and quantum information. Cambridge university press, 2010

    2010

  47. [53]

    Greedy randomized search for scalable com- pilation of quantum circuits,

    A. Oddi and R. Rasconi, “Greedy randomized search for scalable com- pilation of quantum circuits,” in Integration of Constraint Programming, Artificial Intelligence, and Operations Research: 15th International Conference, CPAIOR 2018, Delft, The Netherlands, June 26–29, 2018, ...

    2018

  48. [54]

    Robust and resource-efficient quantum circuit approximation,

    T. Patel, E. Younis, C. Iancu, W. de Jong, and D. Tiwari, “Robust and resource-efficient quantum circuit approximation,” arXiv preprint arXiv:2108.12714, 2021

    2021 arXiv

  49. [55]

    Quest: sys- tematically approximating quantum circuits for higher output fidelity,

    T. Patel, E. Younis, C. Iancu, W. de Jong, and D. Tiwari, “Quest: sys- tematically approximating quantum circuits for higher output fidelity,” in Proceedings of the 27th ACM International Conference on Architectural Support for Programming Languages and Operating Systems , 202...

    2022

  50. [56]

    Simulating large quantum circuits on a small quantum computer,

    T. Peng, A. W. Harrow, M. Ozols, and X. Wu, “Simulating large quantum circuits on a small quantum computer,” Physical review letters, vol. 125, no. 15, p. 150504, 2020

    2020

  51. [57]

    Demonstration of fault-tolerant steane quantum error correction,

    L. Postler, F. Butt, I. Pogorelov, C. D. Marciniak, S. Heußen, R. Blatt, P. Schindler, M. Rispler, M. M ¨uller, and T. Monz, “Demonstration of fault-tolerant steane quantum error correction,” PRX Quantum , vol. 5, p. 030326, Aug 2024. [Online]. Available: https://link.aps.org/...

    2024 doi

  52. [58]

    Transport dynamics of single ions in segmented microstructured paul trap arrays,

    R. Reichle, D. Leibfried, R. Blakestad, J. Britton, J. D. Jost, E. Knill, C. Langer, R. Ozeri, S. Seidelin, and D. J. Wineland, “Transport dynamics of single ions in segmented microstructured paul trap arrays,” Fortschritte der Physik: Progress of Physics, vol. 54, no. 8-10, p...

    2006

  53. [59]

    Ion trap quantum gates with amplitude-modulated laser beams,

    C. F. Roos, “Ion trap quantum gates with amplitude-modulated laser beams,” New Journal of Physics , vol. 10, no. 1, p. 013002, 2008

    2008

  54. [60]

    Realization of real-time fault-tolerant quantum error correction,

    C. Ryan-Anderson, J. G. Bohnet, K. Lee, D. Gresh, A. Hankin, J. P. Gaebler, D. Francois, A. Chernoguzov, D. Lucchetti, N. C. Brown, T. M. Gatterman, S. K. Halit, K. Gilmore, J. A. Gerber, B. Neyenhuis, D. Hayes, and R. P. Stutz, “Realization of real-time fault-tolerant quantum...

  55. [61]

    Muzzle the shuttle: efficient compilation for multi-trap trapped-ion quantum computers,

    A. A. Saki, R. O. Topaloglu, and S. Ghosh, “Muzzle the shuttle: efficient compilation for multi-trap trapped-ion quantum computers,” in 2022 Design, Automation & Test in Europe Conference & Exhibition (DATE). IEEE, 2022, pp. 322–327

    2022

  56. [62]

    Saqip: A scalable architecture for quantum information processors,

    S. Sargaran and N. Mohammadzadeh, “Saqip: A scalable architecture for quantum information processors,” ACM Trans. Archit. Code Optim., vol. 16, no. 2, apr 2019. [Online]. Available: https: //doi.org/10.1145/3311879

    2019 doi

  57. [63]

    Fast quantum logic gates with trapped-ion qubits,

    V . Sch ¨afer, C. Ballance, K. Thirumalai, L. Stephenson, T. Ballance, A. Steane, and D. Lucas, “Fast quantum logic gates with trapped-ion qubits,” Nature, vol. 555, no. 7694, pp. 75–78, 2018

    2018

  58. [64]

    Algorithms for quantum computation: discrete logarithms and factoring,

    P. W. Shor, “Algorithms for quantum computation: discrete logarithms and factoring,” in Proceedings 35th annual symposium on foundations of computer science . Ieee, 1994, pp. 124–134

    1994

  59. [65]

    Colloquium: Trapped ions as quantum bits: Essential numerical tools,

    K. Singer, U. Poschinger, M. Murphy, P. Ivanov, F. Ziesel, T. Calarco, and F. Schmidt-Kaler, “Colloquium: Trapped ions as quantum bits: Essential numerical tools,” Reviews of Modern Physics , vol. 82, no. 3, p. 2609, 2010

    2010

  60. [66]

    Qubit allocation,

    M. Y . Siraichi, V . F. d. Santos, C. Collange, and F. M. Q. Pereira, “Qubit allocation,” in Proceedings of the 2018 International Symposium on Code Generation and Optimization , 2018, pp. 113–125

    2018

  61. [67]

    t— ket¿: a retargetable compiler for nisq devices,

    S. Sivarajah, S. Dilkes, A. Cowtan, W. Simmons, A. Edgington, and R. Duncan, “t— ket¿: a retargetable compiler for nisq devices,”Quantum Science and Technology, vol. 6, no. 1, p. 014003, 2020

    2020

  62. [68]

    Programming physical quantum systems with pulse-level con- trol,

    K. N. Smith, G. S. Ravi, T. Alexander, N. T. Bronn, A. R. Carvalho, A. Cervera-Lierta, F. T. Chong, J. M. Chow, M. Cubeddu, A. Hashim et al. , “Programming physical quantum systems with pulse-level con- trol,” Frontiers in physics, vol. 10, p. 900099, 2022

    2022

  63. [69]

    Quantum computation with ions in thermal motion,

    A. Sørensen and K. Mølmer, “Quantum computation with ions in thermal motion,” Physical review letters, vol. 82, no. 9, p. 1971, 1999

    1971

  64. [70]

    Cutqc: using small quantum computers for large quantum circuit evaluations,

    W. Tang, T. Tomesh, M. Suchara, J. Larson, and M. Martonosi, “Cutqc: using small quantum computers for large quantum circuit evaluations,” in Proceedings of the 26th ACM International conference on architectural support for programming languages and operating systems , 2021, p...

    2021

  65. [71]

    Quantum circuit generator,

    T. Tomesh, “Quantum circuit generator,” https://github.com/ teaguetomesh/quantum circuit generator, 2023

    2023

  66. [72]

    Quantum gate using qubit states separated by terahertz,

    K. Toyoda, S. Haze, R. Yamazaki, and S. Urabe, “Quantum gate using qubit states separated by terahertz,” Physical Review A , vol. 81, no. 3, p. 032322, 2010

    2010

  67. [73]

    Simulating the performance of a distance-3 surface code in a linear ion trap,

    C. J. Trout, M. Li, M. Guti ´errez, Y . Wu, S.-T. Wang, L. Duan, and K. R. Brown, “Simulating the performance of a distance-3 surface code in a linear ion trap,” New Journal of Physics , vol. 20, no. 4, p. 043038, apr

  68. [74]

    A shuttle- efficient qubit mapper for trapped-ion quantum computers,

    S. Upadhyay, A. A. Saki, R. O. Topaloglu, and S. Ghosh, “A shuttle- efficient qubit mapper for trapped-ion quantum computers,” in Proceed- ings of the Great Lakes Symposium on VLSI 2022 , 2022, pp. 305–308

    2022

  69. [75]

    Single ion qubit with estimated coherence time exceeding one hour,

    P. Wang, C.-Y . Luan, M. Qiao, M. Um, J. Zhang, Y . Wang, X. Yuan, M. Gu, J. Zhang, and K. Kim, “Single ion qubit with estimated coherence time exceeding one hour,” Nature communications, vol. 12, no. 1, p. 233, 2021

    2021

  70. [76]

    Laser cooling of atoms,

    D. J. Wineland and W. M. Itano, “Laser cooling of atoms,” Physical Review A, vol. 20, no. 4, p. 1521, 1979

    1979

  71. [79]

    Noise analysis for high-fidelity quantum entangling gates in an anharmonic linear paul trap,

    Y . Wu, S.-T. Wang, and L.-M. Duan, “Noise analysis for high-fidelity quantum entangling gates in an anharmonic linear paul trap,” Physical Review A, vol. 97, no. 6, p. 062325, 2018

    2018

  72. [80]

    Symmetry-based quantum circuit mapping,

    D. Yu and K. Fang, “Symmetry-based quantum circuit mapping,” 2023

    2023

  73. [81]

    Time- optimal qubit mapping,

    C. Zhang, A. B. Hayes, L. Qiu, Y . Jin, Y . Chen, and E. Z. Zhang, “Time- optimal qubit mapping,” in Proceedings of the 26th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2021, pp. 360–374

    2021

  74. [82]

    A variation-aware quantum circuit mapping approach based on multi-agent cooperation,

    P. Zhu, W. Ding, L. Wei, X. Cheng, Z. Guan, and S. Feng, “A variation-aware quantum circuit mapping approach based on multi-agent cooperation,” IEEE Transactions on Computers , 2023

    2023

  75. [83]

    Trapped ion quantum compu- tation with transverse phonon modes,

    S.-L. Zhu, C. Monroe, and L.-M. Duan, “Trapped ion quantum compu- tation with transverse phonon modes,” Physical review letters , vol. 97, no. 5, p. 050505, 2006

    2006

  76. [2018]

    Available: https://dx.doi.org/10.1088/1367-2630/aab341

    [Online]. Available: https://dx.doi.org/10.1088/1367-2630/aab341

    doi

  77. [2021]

    Available: https://link.aps.org/doi/10.1103/PhysRevX

    [Online]. Available: https://link.aps.org/doi/10.1103/PhysRevX. 11.041058

    doi

Pith tools

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