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Evaluating Single Event Upsets in Deep Neural Networks for Semantic Segmentation: an embedded system perspective

T0 review · 3 major / 5 minor · reviewed 2026-08-11 · deepseek-v4-flash

Pith's one-line read For ReLU-based segmentation networks, most single-event-upset errors come from bit flips that increase parameter values, with the exponent MSB being the dominant risk; the paper derives a formula predicting these error rates from bias…

desk verdict Solid, citable SEU study of segmentation U-Nets with a useful protection technique; the printed Equation 2 is mis-specified but the sign-aware calculation behind it is sound. read the letter →

arxiv 2412.03630 v1 pith:YFCBIRW2 submitted 2024-12-04 cs.CV cs.AIcs.ARcs.LGeess.IV

classification cs.CVcs.AIcs.ARcs.LGeess.IV
keywords singleeventupsetssemanticsegmentationfaultinjectionmodelcompressionpruningquantizationembeddedAIrobustnessevaluation
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

This paper tries to establish where single-event upsets actually hurt a deep segmentation network, and whether that vulnerability can be known before any hardware is built. Using a U-Net trained on hyperspectral driving images, it injects single bit-flips layer by layer and bit by bit, in both floating-point and 8-bit quantized versions, and finds that critical errors are dominated by bit-flips that increase a parameter's magnitude. The most dangerous flip is bit 30, the MSB of the exponent in IEEE 754 single precision, because it turns values below 2 into NaNs or infinities; the paper even derives a formula that predicts the resulting error rate from bias signs and class frequencies (37.29% predicted vs 34% measured). It also shows that pruning raises per-parameter sensitivity while quantization makes the model more robust and concentrates all residual risk in the biases. A sympathetic reader would care because this turns a black-box reliability problem into a checkable property of a trained model's weights, and it leads to a no-cost mitigation: nudging parameters away from filled-exponent states.

What carries the argument

The load-bearing object is the binary representation of a trained parameter. In IEEE 754 single precision, a flip in bit 30—the MSB of the exponent—turns any value in $[1,2)$ into NaN or infinity, and a flip in a partially filled exponent (six of the seven lower exponent bits already set to one) pushes a sub-unity value above unity. The paper's central identity is the error-rate formula for the final-layer biases, $$\%\text{error}_{30} = \sum_{j=0}^{5} $P_j^{{\mathrm{fi}}$} $P_j^{{\mathrm{m}}$},$$ where $P_j^{\mathrm{fi}}$ is the probability that a bit-flip lands in bias $j$ (taken as $1/6$ in the experiment) and $P_j^{\mathrm{m}}$ is the faultless model's probability of predicting class $j$. This identity carries the argument because it converts a costly fault-injection campaign into an offline computation from two cheap quantities: bias signs and per-class prediction probabilities. The same representational reasoning motivates the proposed protection, which increments or decrements the exponent and compensates the mantissa so that no parameter sits one zero away from a filled exponent.

What would settle it

Take any trained ReLU segmentation FCN, compute the six output-bias signs and the faultless model's per-class prediction probabilities, then inject 1550 bit-30 flips into those biases; if the measured error rate disagrees with Equation 2 by more than the 2.5% margin allowed by the sample-size formula, the paper's predictive claim fails.

Watch

Extended reading notes

Core claim

On the paper's own terms, the central discovery is that for ReLU-based encoder-decoder segmentation networks, SEU-induced failures are not spread uniformly across the parameter tensor: they concentrate in magnitude-increasing flips, with the exponent MSB (bit 30) as the dominant threat. In single-precision floating point, flipping bit 30 of any parameter in $[1,2)$ yields NaN or infinity; flipping a partially filled exponent (six lower exponent bits already set to one) pushes a sub-unity value above unity. Because ReLU outputs are nonnegative and the network's computation is largely monotonic, positive biases and positive gamma parameters in batch-normalization layers become the vulnerable points, and the final-layer bias error rate can be predicted with an equation that combines the probability of a flip in each bias and the probability the model predicts that class. The paper verifies this prediction experimentally (37.29% vs 34% for the unpruned model, 37.24% vs 32% for the pruned one), then shows that BN folding and quantization relocate rather than remove the risk, and concludes with a set of zero-overhead parameter-adjustment protections.

Load-bearing premise

The analysis assumes a streaming-like implementation with independent resources per layer, so a single event upset flips one stored parameter and never corrupts configuration memory, control logic, or shared buses (Section 3.2); if real-device errors are dominated by configuration upsets or multi-bit upsets, the per-layer error rates and SEU-per-hour estimates will not transfer.

Editorial extensions

If this is right

  • Once a network is trained, its SEU error rate for the dominant bit-30 mechanism can be estimated from parameter sign, magnitude, and class frequencies, without running fault injections.
  • Pruning removes the redundant slack that absorbs errors, so every remaining parameter is more critical; however, the pruned model's 100x smaller size drops the expected SEU encounter rate from about 5 to 0.05 SEUs per hour at 20 FIT/Mb.
  • Integer quantization eliminates NaN and infinity states, making weights nearly immune; error protection can therefore be limited to the small bias subset, enabling low-cost redundancy.
  • Batch-normalization folding eliminates the most sensitive parameters but increases conv-bias magnitudes, shifting vulnerability to lower exponent bits (24-29), so hardening must account for where the risk moves.
  • The proposed exponent-adjustment protection reduces error rates at PT1-PT2 settings with no memory or computational overhead and only minor IoU changes.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • The same sign-and-representation analysis should transfer to other ReLU-based encoder-decoder networks; a direct test is to compute Equation 2 on a published segmentation model with different class frequencies and compare against a short bit-30 injection campaign.
  • Because the upper word of an int8 bias only extends the sign, those redundant high bits could be repurposed as parity or error-detection storage with zero memory overhead—an idea the paper leaves implicit.
  • The exponent-adjustment protection could be folded into training as a regularizer that keeps parameters away from filled-exponent states, potentially improving SEU robustness before deployment.
  • The crossover point where pruning's smaller SEU encounter rate outweighs its higher per-bit sensitivity is a design variable the paper quantifies but does not optimize; finding that optimum for a given FIT rate and mission time would be a natural next step.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

3 major / 5 minor

Summary. This manuscript presents a software fault-injection study of single-bit upsets (SBUs) in a U-Net-based semantic segmentation model, covering unpruned/pruned and FP32/INT8 variants. It reports layer-by-layer and bit-by-bit error rates, identifies sign- and exponent-related sensitivity patterns, and proposes zero-overhead parameter reconfiguration techniques to reduce risky exponent states. The central quantitative claim is that the error rate for bit-30 flips in the output biases can be predicted analytically from class frequencies (Equation 2), and that robustness can therefore be estimated without new fault injections.

Significance. The paper has clear strengths: the FI campaign is large (155,000 injections); the code for the FI tool and for the protection tool is publicly available; and the qualitative observations about positive biases, BN gamma sensitivity, partial-exponent filling, and BN folding are supported by calibration data and per-layer/per-bit statistics. If the analytic error-rate model were valid, the paper would offer a practical pre-deployment robustness estimator for encoder-decoder segmentation networks. However, the central analytic model is not valid as printed, and the SEU/hour extrapolation contains a unit error, so the paper currently overstates what is established. The qualitative vulnerability analysis remains a useful contribution.

major comments (3)
  1. [Sec. 4.1.1, Eq. (2)] Equation (2) is not a valid probability model as printed. The quantities P_j^m are described as probabilities that the faultless model predicts class j, but the substituted values (0, 55.09, 4.41, 73.05, 7.47, 83.73) are percentages summing to 223.75, not to 100. More importantly, the equation applies the same factor P_j^m to every bias regardless of sign, while the surrounding prose correctly states that a bit-30 flip in a negative bias makes that class never predicted (contribution P_j^m) and in a positive bias makes it always predicted (contribution 1 - P_j^m). With the listed values and the sign-aware rule, the prediction is (0 + 4.41 + 7.47 + 44.91 + 26.95 + 16.27)/6 = 16.67%, not the reported 37.29%; the claimed agreement with the experimental 34% is therefore not supported. The same invalid formula is reused in Sec. 4.1.2 (37.24%) and in Secs. 4.2.1 and 4.2.2 for the QNN (37.06% and 37.89%), so the quantitative half of the claim that robustness can be predicted without fault injection fails. Please correct the model and re-evaluate the agreement, or explicitly limit the claim to the qualitative sign/exponent mechanism.
  2. [Sec. 4.2.3 and Sec. 6] The SEU/hour estimates derived from a failure rate of 20 FIT/Mb are inconsistent with the standard definition of FIT (failures per 10^9 device-hours). With the model sizes in Table 2, 20 FIT/Mb corresponds to about 1.9e-5 SEU/h for the 118.77 MB FP32 unpruned model and about 4.8e-6 SEU/h for the 29.70 MB INT8 unpruned model, not the reported 5 SEU/h. The claimed 1000 upsets in 8.3 days and the corresponding pruned-model figure of about 2.3 years are therefore off by several orders of magnitude. Please correct the unit conversion or state the assumed FIT definition explicitly; the current numbers do not follow from the cited failure rate.
  3. [Sec. 5.1, paragraph after Table 17] The protection method is evaluated by injecting single bit-flips only in the risky bit positions of the parameters selected by the PT setting. Because the method is specifically designed to eliminate those risky exponents, this evaluation is partly circular and cannot quantify the method's effect on overall robustness under a realistic SEU distribution. The paper should also report the error rate of the protected models under the same random or exhaustive FI campaign used in Section 4, or at least under random bit positions across all parameters, together with the observed IoU changes. Without that, the claim that the proposed technique improves robustness with no memory or computational cost is demonstrated only for a targeted failure mode, not for general SBU exposure.
minor comments (5)
  1. [Abstract and Introduction] There are typos such as 'artifical intelligence' in the abstract and 'mayor concern' in the introduction; please correct them.
  2. [Sec. 4.2.1] The 'linear weighting approximation based on bit significance' used to obtain the experimental values 37.64% and 37.89% is not specified; the weights should be stated so that the aggregation is reproducible.
  3. [Sec. 5.1] The PT1-PT4 thresholds (1.999/1.001, 1.99/1.01, 1.95/1.05, 1.9/1.1) are introduced only in prose before Table 13; a compact definition in the table caption or in a short equation would improve readability.
  4. [Sec. 3.2, Sec. 4.2.3, Sec. 6] The streaming-like architecture assumption (independent per-layer resources, no configuration-memory or control-logic upsets) is stated early, but it should be recalled when the SEU/hour numbers are given, because those numbers are parameter-memory estimates, not device-level soft-error rates.
  5. [Sec. 6] The word 'prunning' appears in the conclusions; it should be 'pruning'.

Circularity Check

0 steps flagged · score 0.0 of 10

No significant circularity: the analytic error-rate estimate is checked against independent FI data, not fitted to it.

full rationale

This paper is an empirical fault-injection study whose central analytic estimate (Eq. 2) is computed from the faultless model's class frequencies and then compared against independently measured bit-flip error rates. The P_j^m inputs are not fitted to the experimental error rates; the comparison is a check rather than a tautology. The protection method is evaluated by flipping the specific bits it was designed to make safe, which tests the mechanism directly and does not rename the design target as a prediction. Self-citations ([20], [21], [66]) provide the public dataset and tooling used as experimental setup; they are not invoked as authority for the robustness conclusions. No step in the derivation chain reduces to its own inputs by construction. A separate correctness concern is that Eq. 2 as printed contains a normalization/sign inconsistency (the listed P_j^m values sum to 223.75, and the sign-dependent error rule in the text would require using 1-P_j^m for positive biases), but this is a modeling error, not circularity. The score reflects that the main derivation is self-contained against external fault-injection benchmarks.

Assumptions & free parameters 1 free parameters · 5 assumptions · 0 invented entities

The central results rest on the software fault-injection model rather than on radiation testing; the streaming-architecture assumption (Section 3.2, [68]) is the main structural premise. The analytic error-rate expressions use faultless-model class frequencies as inputs and match experimental averages, so they add no fitted degrees of freedom, while the PT thresholds are hand-set trade-off knobs.

free parameters (1)
  • Protection target mantissa thresholds (PT1-PT4) = PT1 (1.999, 1.001), PT2 (1.99, 1.01), PT3 (1.95, 1.05), PT4 (1.9, 1.1)
    Hand-chosen thresholds that define which mantissas count as 'full' or 'empty' for the exponent-protection method; higher PT protects more parameters but perturbs the model more (Tables 14-17).
assumptions (5)
  • domain assumption Streaming-like implementation with independent resources per layer, so an SEU only affects one stored parameter and does not propagate to configuration memory or shared logic (Section 3.2, [68]).
    This is what makes per-layer error rates well-defined and justifies the parameter-only fault injection model; real FPGAs can also suffer configuration upsets that corrupt the circuit itself.
  • domain assumption Software-injected single bit-flips in stored weights/biases/BN parameters emulate hardware SEUs with uniform probability over bits and parameters (Section 4).
    The FI campaign is the evidence base for all error rates; if real SEU cross-sections are non-uniform (e.g., more likely in certain memory columns or during specific states), the quantitative results shift.
  • standard math Statistical sample-size formula from Leveugle et al. [73] with p=0.5, e=0.025, t=1.96 yields n=1550 (Equation 1).
    The formula is standard for binomial proportion confidence; p=0.5 is a conservative worst case used to maximize sample size.
  • domain assumption For Equation 2, the error rate from a bit-flip in bias j is P_j^m for negative biases and 1-P_j^m for positive biases, with each bias equally likely to be flipped (Section 4.1.1).
    This sign-dependent rule is what makes the predicted 37.29 match the experimental 34%; the printed equation hides the sign dependence, which is a presentation flaw.
  • domain assumption Numeric ranges observed in calibration passes (e.g., activations within [-6.77, 11.79], gamma in (0.1, 2)) are representative of the test distribution (Section 4.1.1).
    All mechanistic explanations about exponent-fill and NaN rely on these calibration ranges; a different input distribution could change which parameters are risky.

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Cite this review

Pith. "Pith review of Evaluating Single Event Upsets in Deep Neural Networks for Semantic Segmentation: an embedded system perspective." pith.science (2026). https://pith.science/paper/YFCBIRW2

@misc{pith2026241203630,
  author       = {Pith},
  title        = {Pith review of: Evaluating Single Event Upsets in Deep Neural Networks for Semantic Segmentation: an embedded system perspective},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/YFCBIRW2}},
  note         = {Machine review of arXiv:2412.03630}
}
read the original abstract

As the deployment of artifical intelligence (AI) algorithms at edge devices becomes increasingly prevalent, enhancing the robustness and reliability of autonomous AI-based perception and decision systems is becoming as relevant as precision and performance, especially in applications areas considered safety-critical such as autonomous driving and aerospace. This paper delves into the robustness assessment in embedded Deep Neural Networks (DNNs), particularly focusing on the impact of parameter perturbations produced by single event upsets (SEUs) on convolutional neural networks (CNN) for image semantic segmentation. By scrutinizing the layer-by-layer and bit-by-bit sensitivity of various encoder-decoder models to soft errors, this study thoroughly investigates the vulnerability of segmentation DNNs to SEUs and evaluates the consequences of techniques like model pruning and parameter quantization on the robustness of compressed models aimed at embedded implementations. The findings offer valuable insights into the mechanisms underlying SEU-induced failures that allow for evaluating the robustness of DNNs once trained in advance. Moreover, based on the collected data, we propose a set of practical lightweight error mitigation techniques with no memory or computational cost suitable for resource-constrained deployments. The code used to perform the fault injection (FI) campaign is available at https://github.com/jonGuti13/TensorFI2 , while the code to implement proposed techniques is available at https://github.com/jonGuti13/parameterProtection .

Figures

Figures reproduced from arXiv: 2412.03630 by the authors.

Figure 1
Figure 1. A sample segmented image of HSI-Drive v2.0. The most recent version of the model [66] was trained using the HSI-Drive v2.0 dataset [66], intended for develop￾ing ADAS/ADS systems using HSI ( [PITH_FULL_IMAGE:figures/full_fig_p005_1.png] view at source ↗
Figure 2
Figure 2. Architecture of the unpruned unfolded unquantized U-Net model which has been used as reference [PITH_FULL_IMAGE:figures/full_fig_p006_2.png] view at source ↗
Figure 3
Figure 3. Single-precision floating-point format (IEEE 754 format) [PITH_FULL_IMAGE:figures/full_fig_p007_3.png] view at source ↗
Figures from the paper (27 more)
Figure 5
Figure 5. Figure 5: Bit-flip error rate on the original pruned model. 4.1.1. Analysis of robustness of the unpruned model Output 𝑐𝑜𝑛𝑣2𝐷 layer 𝑐𝑜𝑛𝑣2𝐷_22 (𝑝99-𝑝100 sets in Fig￾ure 2) consists of 𝑛𝑐𝑙𝑎𝑠𝑠 filters of 1 ∗ 1 ∗ 𝐶 dimensions and 𝑛𝑐𝑙𝑎𝑠𝑠 biases, where 𝑛𝑐𝑙𝑎𝑠𝑠 is the number of classes …
Figure 6
Figure 6. Figure 6: Graphic representation of the unpruned model’s calibration study (layers 𝑐𝑜𝑛𝑣2𝐷_21 to 𝑐𝑜𝑛𝑣2𝐷_22). A signal calibration analysis (see [PITH_FULL_IMAGE:figures/full_fig_p008_6.png]
Figure 7
Figure 7. Figure 7: Graphic representation of the unpruned model’s calibration study (layers 𝑐𝑜𝑛𝑣2𝐷 to 𝑐𝑜𝑛𝑣2𝐷_3). It so happens that in this model, 𝛾 values are positive, smaller than 2 but higher than 0.1. Thus, in this case, three different scenarios can be considered: values higher tha…
Figure 9
Figure 9. Figure 9: Bit-flip error in the 30th bit (dashed) and ratio of positive parameters (solid) by parameter index: 𝑐𝑜𝑛𝑣2𝐷𝑏 (green), 𝐵𝑁𝑏𝑒𝑡𝑎 (blue) and 𝑐𝑜𝑛𝑣2𝐷𝑡𝑟𝑏 (orange) in the unpruned model. We can analyse the influence of bias parameters in more detail by inspecting the presence o…
Figure 8
Figure 8. Figure 8: Graphic representation of the unpruned model’s calibration study (layers 𝑐𝑜𝑛𝑣2𝐷_4 to 𝑐𝑜𝑛𝑣2𝐷_7). In the worst case, if a bit-flip occurs in bit 30th of a positive weight, when multiplied by a positive input, it pro￾duces a value close to the maximum representable number…
Figure 10
Figure 10. Figure 10: Graphic representation of the unpruned model’s calibration study (layers 𝑐𝑜𝑛𝑣2𝐷_8 to 𝑐𝑜𝑛𝑣2𝐷_11) [PITH_FULL_IMAGE:figures/full_fig_p011_10.png]
Figure 11
Figure 11. Figure 11: Graphic representation of the unpruned model’s calibration study (layers 𝑐𝑜𝑛𝑣2𝐷_12 to 𝑐𝑜𝑛𝑣2𝐷_14). However, since the values of the bias parameters are essen￾tially identical to those of the unpruned model (−0.8495, 0.3150, −0.02991, 0.0373, −0.1736, 0.1066), the concl…
Figure 13
Figure 13. Figure 13: Exponent part of the 32-bit floating-point represen￾tation of the biases of the last 𝑐𝑜𝑛𝑣2𝐷 of the pruned model. drastically from 01111111 to 1000000. Then, a change in bit 30 of those 𝛾s will no longer cause a value to be a 𝑁𝑎𝑁; instead, it will be a very small numbe…
Figure 14
Figure 14. Figure 14: Bit-flip error in the 30th bit (dashed) and ratio of positive parameters (solid) by parameter index: 𝑐𝑜𝑛𝑣2𝐷𝑏 (green), 𝐵𝑁𝑏𝑒𝑡𝑎 (blue) and 𝑐𝑜𝑛𝑣2𝐷𝑡𝑟𝑏 (orange) in the pruned model. Bias parameters in 𝑐𝑜𝑛𝑣2𝐷 layers As observed in the unpruned model, flips in bit 30 of the b…
Figure 15
Figure 15. Figure 15: Graphic representation of the pruned model’s calibration study (layers 𝑐𝑜𝑛𝑣2𝐷 to 𝑐𝑜𝑛𝑣2𝐷_3) [PITH_FULL_IMAGE:figures/full_fig_p013_15.png]
Figure 18
Figure 18. Figure 18: Graphic representation of the pruned model’s calibration study (layers 𝑐𝑜𝑛𝑣2𝐷_12 to 𝑐𝑜𝑛𝑣2𝐷_14). most of implementations the probability of a SBU in smaller models is also lower [PITH_FULL_IMAGE:figures/full_fig_p014_18.png]
Figure 17
Figure 17. Figure 17: Exponent part of the 32-bit floating-point represen￾tation of the 𝑐𝑜𝑛𝑣2𝐷𝑡𝑟_4𝑏 , 𝑝90 set in [PITH_FULL_IMAGE:figures/full_fig_p014_17.png]
Figure 19
Figure 19. Figure 19: Graphic representation of the pruned model’s calibration study (layers 𝑐𝑜𝑛𝑣2𝐷_4 to 𝑐𝑜𝑛𝑣2𝐷_7). 4.1.4. Batch normalization folding Since the 𝛾 parameters of the BN layers have shown to be the most sensitive ones of the network upon SBUs, fusing the BN operation with the…
Figure 20
Figure 20. Figure 20: Bit-flip error rate on the unpruned folded model [PITH_FULL_IMAGE:figures/full_fig_p015_20.png]
Figure 22
Figure 22. Figure 22: Two’s complement arithmetic for 8-bit and 32-bit integer/fixed-point representation. convolution layers to reduce the number of parameters and speed up computations. According to [69], the quantized version ̂𝑟 of a real number 𝑟 is approximated by Equation 5, where 𝑆 …
Figure 23
Figure 23. Figure 23: Bit-flip error rate on the unpruned quantized model. Weights are quantized to 8 bits (bit 7 is the MSB). Biases are quantized to 32 bits and faults are injected across all bit positions due to disparities in their ranges. 0 20 31 40 60 Percentage of errors 49 80 23 De…
Figure 24
Figure 24. Figure 24: Bit-flip error rate on the pruned quantized model. Weights are quantized to 8 bits (bit 7 is the MSB). Biases are quantized to 32 bits and faults are injected across all bit positions due to disparities in their ranges. The biases Contrary to what was observed for the…
Figure 25
Figure 25. Figure 25: Bit-flip error in [17 − 30] bits (dashed) and ratio of positive bias (solid) in some 𝑐𝑜𝑛𝑣2𝐷𝑏 encoder layers of the quantized unpruned model. For QNNs the layer position is more determinant, mainly due to the presence of skip connections and longer error propagation pa…
Figure 26
Figure 26. Figure 26: Calibration study of the unpruned quantized model (𝑞𝑤, 𝑞𝑏 and 𝑞𝑎 ) from layers 𝑐𝑜𝑛𝑣2𝐷 to 𝑐𝑜𝑛𝑣2𝐷_6. However, analyzing the sign of the biases remains rel￾evant to explain the bit-flip errors in the initial layers of the encoder. For int-8 representation, perturbed para…
Figure 29
Figure 29. Figure 29: Calibration study of the unpruned quantized model (𝑞𝑤, 𝑞𝑏 and 𝑞𝑎 ) from layers 𝑐𝑜𝑛𝑣2𝐷_7 to 𝑐𝑜𝑛𝑣2𝐷_12 [PITH_FULL_IMAGE:figures/full_fig_p018_29.png]
Figure 30
Figure 30. Figure 30: Calibration study of the pruned quantized model (𝑞𝑤, 𝑞𝑏 and 𝑞𝑎 ) from layers 𝑐𝑜𝑛𝑣2𝐷 to 𝑐𝑜𝑛𝑣2𝐷_6. 4.2.2. Analysis of robustness of the pruned model Relevance of weights compared to biases Despite the decrease in robustness of the pruned model (as illustrated in [PITH_…
Figure 31
Figure 31. Figure 31: Bit-flip error in [17 − 30] bits (dashed) and percentage of positive bias (solid) in 𝑐𝑜𝑛𝑣2𝐷𝑏 layers of the pruned quantized model. 26 and 30). The only region where this cleanup may not be too pronounced is the central area (as seen in the comparison of [PITH_FULL_IM…
Figure 33
Figure 33. Figure 33: Calibration study of the pruned quantized model (𝑞𝑤, 𝑞𝑏 and 𝑞𝑎 ) from layers 𝑐𝑜𝑛𝑣2𝐷_13 to 𝑐𝑜𝑛𝑣2𝐷_17. Output 𝑐𝑜𝑛𝑣2𝐷 layer The explanation given for the un￾pruned model remains applicable. Despite having slightly smaller magnitude bias values ([−19945, 1730, −150, 209, …
Figure 34
Figure 34. Figure 34: Calibration study of the pruned quantized model (𝑞𝑤, 𝑞𝑏 and 𝑞𝑎 ) from layers 𝑐𝑜𝑛𝑣2𝐷_18 to 𝑐𝑜𝑛𝑣2𝐷_22. given that targeted BFAs in embedded systems would be very improbable, this study has been performed based on a randomized fault injection campaign. We randomly inject…
Figure 36
Figure 36. Figure 36: Mean error rate due to multiple bit-flips for the quantized pruned model. Each purple dot represents the error rate of individual repetitions of the injections. 5. Robustness enhancement techniques As discussed in Subsection 2.2, neural network hard￾ening methods agai…
Figure 35
Figure 35. Figure 35: Mean error rate due to multiple bit-flips for the quantized unpruned model. Each purple dot represents the error rate of individual repetitions of the injections. The results align with those reported by other authors in the context of image classification. For instan…
Figure 37
Figure 37. Figure 37: Values of the partially filled exponents (in green) after increasing (in blue) or decreasing (in orange) its value by 1. The three values which are crossed in red are not useful as either the number of ’0’-valued positions does not increase or the value of the paramet…

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