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REVIEW 3 major objections 5 minor 31 references

IMPACT:InMemory ComPuting Architecture Based on Y-FlAsh Technology for Coalesced Tsetlin Machine Inference

T0 review · 3 major / 5 minor · reviewed 2026-08-11 · deepseek-v4-flash

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Pith's one-line read This paper presents IMPACT, an in-memory computing architecture that maps coalesced Tsetlin machine inference onto two Y-Flash crossbars and reports 96.3% accuracy on MNIST with 24.56 TOPS/W.

desk verdict The Y-Flash/CoTM mapping is real and interesting, but the 24.56 TOPS/W headline is off by ~140x against the paper's own numbers. read the letter →

arxiv 2412.05327 v1 pith:WBDQCDEQ submitted 2024-12-04 cs.AR cs.AIcs.ETcs.LG

Omar Ghazal , Wei Wang , Shahar Kvatinsky , Farhad Merchant , Alex Yakovlev , Rishad Shafik This is my paper · ORCID
classification cs.ARcs.AIcs.ETcs.LG
keywords coalescedTsetlinmachinein-memorycomputingY-Flashmemristornon-volatilememoryinferenceacceleratorMNISTcrossbararrayedgeAI
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

This paper proposes an in-memory computing architecture, IMPACT, that maps the inference path of a coalesced Tsetlin machine (CoTM) onto two Y-Flash memristor crossbars: a 2048x500 clause tile operating in Boolean conductance mode and a 500x10 class tile operating in analog mode. The goal is to show that the logic-based CoTM can be evaluated entirely inside memory, eliminating von Neumann data movement while keeping the model's interpretable propositional rules. On MNIST the architecture reaches 96.3% accuracy, matching software training within 25 epochs, with 24.56 TOPS/W and 0.17 TOPS/mm2. The paper also claims energy-efficiency advantages of 2.23x, 2.46x, and 2.06x over ReRAM-CNN, NOR-Flash neuromorphic, and PCM-DNN accelerators. A sympathetic reader would care because this points toward low-power, non-volatile, transparent edge inference.

What carries the argument

The load-bearing object is the Y-Flash cell, a two-terminal floating-gate memristor fabricated in 180 nm CMOS, with a read transistor and an injection transistor sharing a floating gate; it can be programmed to two Boolean conductance states or to intermediate analog levels. The carrying idea is to encode logical values as physical quantities: TA actions become HCS/LCS, input literals become 2 V or floating, weights become conductance segments, and Kirchhoff's current law performs the summation. The clause tile's current sense amplifier with a 4.1$\,\mu$A threshold turns the analog column current into the Boolean clause, while the class tile's two-step tuning (wide pulses for pre-tuning within $\pm20$ segments, narrow pulses for fine-tuning within $\pm5$ segments) maps the 0-419 weight range onto conductance. This mapping is what lets a propositional-logic model run as analog current sums in a memory array.

What would settle it

Program a batch of Y-Flash cells to each of the 420 weight-corresponding conductance segments using the paper's pre-tune/fine-tune sequence, then cycle each cell and record the spread of achieved conductance; if a material fraction of cells falls outside the $\pm5$-segment acceptance band, the mapped weights would deviate from the software weights and the 96.3% MNIST accuracy would not hold in hardware.

Watch

Extended reading notes

Core claim

The central claim is that a CoTM model can be decomposed into two physical crossbar operations and still preserve software accuracy. In the clause tile, each Tsetlin automaton's final include/exclude action is stored as a high or low conductance state (HCS or LCS), and each Boolean input literal is applied as either a floating node or a 2 V read voltage; Ohm's law at each cell then performs the required AND/OR interaction, and a current sense amplifier converts the column current into a Boolean clause using a 4.1$\,\mu$A threshold. In the class tile, the trained clause weights are shifted to unipolar values, segmented into 420 conductance levels, and written with a pre-tune/fine-tune pulse sequence; currents summed along each column realize the weighted vote for each class. With this mapping, the paper reports 96.3% MNIST accuracy and the energy and throughput figures above, and argues that Y-Flash's self-selecting behaviour removes sneak-path currents and the need for selectors.

Load-bearing premise

The class crossbar assumes that each Y-Flash cell can be programmed to any of the roughly 420 intermediate conductance levels within a tolerance of about $\pm5$ segments, but the variability data in the paper characterize only the two endpoint states, LCS and HCS.

Editorial extensions

If this is right

  • If IMPACT is correct, a full MNIST inference pass needs no transfers between separate memory and compute units: one crossbar evaluates all 500 clauses and the second computes the 10 class votes.
  • The 2.32% include-action ratio means most clause cells sit in the low-conductance state, so inference energy stays near the LCS reading energy for typical inputs, making the sparse logic of CoTM directly pay off in hardware.
  • Because Y-Flash is non-volatile with retention over 10 years and endurance of $10^5$ cycles, the trained model can be stored and re-read without refresh, supporting always-on edge inference after a single programming step.
  • The modular crossbar partitioning shown for clauses and classes implies the same two-tile scheme can scale to larger datasets by splitting literals or weights across multiple arrays and combining partial results digitally.
  • Against the published baselines, IMPACT's 24.56 TOPS/W gives a 2.23x, 2.46x, and 2.06x energy-efficiency improvement over ReRAM-CNN, NOR-Flash neuromorphic, and PCM-DNN accelerators, respectively.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • Editorial extension: the paper validates inference only; if the same Y-Flash cells can absorb TA state updates as program/erase pulses, the architecture could plausibly support online CoTM learning, since the device endurance of $10^5$ cycles is demonstrated.
  • Editorial extension: because the variability study measures only the LCS and HCS endpoints, a direct measurement of intermediate conductance-state reproducibility under the $\pm5$-segment fine-tuning tolerance would be the quickest test of whether the 96.3% accuracy survives in a manufactured class tile.
  • Editorial extension: the same Boolean-to-current mapping could be reused for other logic-based learners whose inference is a conjunction of literals, not only CoTM, potentially broadening Y-Flash IMC beyond Tsetlin machines.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

3 major / 5 minor

Summary. The paper proposes IMPACT, an in-memory computing architecture that uses two Y-Flash crossbar arrays to accelerate inference of a coalesced Tsetlin machine (CoTM). The clause crossbar tile (2048x500) operates in Boolean mode to compute clauses via column currents, while the class crossbar tile (500x10) operates in analog mode to compute weighted class sums. The authors report 96.3% accuracy on MNIST, 24.56 TOPS/W, 0.17 TOPS/mm2, and energy-efficiency improvements of 2.23X, 2.46X, and 2.06X over ReRAM-CNN, NOR-Flash neuromorphic, and PCM-DNN accelerators, respectively. The paper also presents CSA design and corner analysis, C2C and D2D variability measurements of Y-Flash endpoints, and a two-stage weight-to-conductance tuning procedure.

Significance. If the reported efficiency numbers were reproducible, the paper would be a valuable first demonstration of CoTM inference on a Y-Flash crossbar, with the practical strengths of using measured device data, a detailed CSA worst-case analysis, and a transparent two-stage mapping of trained weights to conductance levels. The architectural idea of splitting CoTM into a Boolean clause crossbar and an analog class crossbar is interesting and worth pursuing. However, the central quantitative claims about energy efficiency and the comparative speedups are not supported by the paper's own definitions and numbers, and the accuracy claim relies on an unverified assumption about the reliability of intermediate analog conductance states. These issues need to be resolved before the paper can be accepted.

major comments (3)
  1. [Section 5, Table 4, Table 6] The reported TOPS/W figure is not reproducible from the paper's own definitions. Section 5 defines an operation as reading one column of the crossbar and reports 5.76 pJ/operation as the worst-case column energy. For one MNIST image, the architecture performs 500 clause-column reads and 10 class-column reads, i.e., 510 operations, and Table 4 reports 67.99 pJ + 16.22 pJ = 84.21 pJ per image. These values give 510/(84.21e-12) = 6.06 TOPS/W, or 1/(5.76e-12) = 0.17 TOPS/W if the stated per-operation energy is used, not the claimed 24.56 TOPS/W. The claimed value is only reproducible if each of the 2048 cells in a column is counted as two operations (multiply and accumulate), a convention that contradicts the stated definition and is not used for the pJ/MAC entries of the comparison systems in Table 6. The Table 6 speedups (2.23X, 2.46X, 2.06X) are ratios of this unreproducible number and therefore do not support the abstract's efficiency claims. Please state the exact operation-counting convention, recompute all efficiency metrics consistently, and redo the comparisons on an apples-to-apples basis.
  2. [Section 4(a), Section 3(b), Figures 7-8] The class crossbar mapping in Section 3(b) divides the Y-Flash conductance range into up to 420 uniform segments and requires each cell to be tuned within a ±5-segment margin. However, the variability evidence in Section 4(a) characterizes only the endpoint states LCS and HCS; no cycle-to-cycle or device-to-device statistics are provided for intermediate analog conductance levels. Because the 96.3% accuracy result depends on the class tile accurately reproducing trained weights, the authors should provide per-segment variability data (or simulations using measured intermediate-state distributions) and show that the ±5-segment fine-tuning acceptance criterion is met across devices and cycles. Without this, the accuracy claim under realistic device mismatch is not established.
  3. [Section 5, Table 4] The reported GOPS value of 413.6 and the TOPS/mm2 value of 0.17 are not tied to a stated timing model. The paper gives a 5 ns read cycle for a clause column but does not state whether the 500 clause columns and 10 class columns are read sequentially, in parallel, or in a pipelined fashion. The statement that one clause/class computation 'is equivalent to two MAC operations' is asserted without derivation. Please provide a concrete throughput model and justify the MAC equivalence, since these metrics are central to the performance claims.
minor comments (5)
  1. [Section 4(b)] The text says the pre-tuning process 'reduced the cost error by 0.62%' and then 'reduce the 0.62% cost error to 1%'; if the cost error increased from 0.62% to 1%, the word 'reduced' is misleading and should be corrected.
  2. [Section 5, Table 6 discussion] The sentence 'IMPACT outperforms other technologies in terms of TOPS/W by a factor of X' is followed by a list that includes '0.61X compared to [26]', which is underperformance, not outperformance; the phrasing should be revised.
  3. [Section 5] The equivalence between a clause computation and two MAC operations appears without derivation or citation; please either justify it formally or replace it with a metric whose definition is explicit.
  4. [Data Accessibility] The paper states that no additional data are available; given that the efficiency claims cannot be reproduced from the text alone, providing a detailed calculation sheet or simulation scripts as supplementary material would be necessary during revision.
  5. [Table 5] The hyperparameters (number of epochs, TA states, literal encoding) for the additional datasets in Table 5 are not specified; please add them or clearly label these as preliminary feasibility results.

Circularity Check

1 steps flagged · score 6.0 of 10

TOPS/W efficiency advantage is an artifact of the paper's own operation-counting convention; accuracy mapping is not circular.

  1. self definitional [Section 5 (Performance and Efficiency Evaluation), Table 4 and Table 6; Abstract]
    "the operation in the IMPACT architecture is defined as reading one column in the crossbar array, with each column consisting of 2048 cells. ... The measurements showed that the energy consumed for reading one column is 5.76 pJ. ... The performance in terms of GOPS (Giga Operations Per Second) was determined by evaluating the number of operations per second during clause and class computations to be 413.6."

    The claimed TOPS/W (24.56) and the resulting 2.23X/2.46X/2.06X improvements are computed from an operation count that the paper never derives from the measured 5.76 pJ per column read. With the paper's own definition (one operation = one 2048-cell column read), 1/(5.76e-12 J) = 0.174 TOPS/W, and 510 column reads per image at 84.21 pJ give 6.06 TOPS/W; neither equals 24.56. The reported value requires roughly 2068 counted operations per image, or about 141 operations per column read, a convention stated nowhere and not implied by 'equivalent to two MAC operations.' The efficiency advantage and the comparative ratios are therefore artifacts of the chosen operation-counting convention rather than independent measured results.

full rationale

The MNIST accuracy result is a mapping validation, not a fit: a trained CoTM model's TA actions and clause weights are programmed into Y-Flash conductance states, and the resulting inference accuracy (96.3%) tracks the software model. That derivation chain has independent content. The Y-Flash device characterization is cited from prior work but is based on external measurements, and the cited CoTM algorithm is not developed by the authors, so self-citation is not load-bearing for the logical mapping. The circular element is confined to the efficiency comparison: the TOPS/W and relative improvements are determined by the authors' own operation-counting convention, which is inconsistent with the paper's stated per-column energy of 5.76 pJ. On a consistent operation count the claimed advantage reverses. The score reflects this partial circularity of the headline efficiency claim while recognizing that the accuracy validation remains independent.

Assumptions & free parameters 4 free parameters · 4 assumptions · 0 invented entities

The central claims rest on the device compact model, the CoTM software model, and several hand-set design parameters (CSA threshold, segmentation count, tuning margins, MAC equivalence). No new physical entities are introduced. The most significant unverified premise is the programmability of intermediate analog conductance states, which is asserted but not characterized by the variability measurements.

free parameters (4)
  • CSA clause threshold = 4.1 µA
    Set by hand to separate the clause-'0' condition (at least one literal-0 interacting with an include TA, producing roughly 5 µA) from the worst-case exclude leakage (roughly 3.1 µA in the 2048-cell column). This threshold directly controls the Boolean clause output and is not derived from first principles.
  • Weight-to-conductance segmentation count = 420 uniform segments over 1 nS to 2.5 µS
    The conductance range is uniformly divided into as many segments as the highest unsigned software weight (419 + 1). This discretization is a mapping choice, and the paper does not analyze sensitivity to the number of segments.
  • Pre-tune and fine-tune error margins = ±20 segments (pre-tune), ±5 segments (fine-tune)
    Chosen empirically to balance programming pulse count and accuracy; no optimization or sensitivity study is provided.
  • Clause-to-MAC equivalence = 2 MACs per clause computation
    The GOPS and TOPS/W calculations count each clause computation and each class computation as equivalent to two MAC operations. This equivalence is stated without justification and forms the basis of the efficiency comparison against neural network accelerators.
assumptions (4)
  • domain assumption Kirchhoff's current law and Ohm's law accurately describe the crossbar summation with negligible wire resistance and no sneak-path currents.
    The clause and class computations rely on column current summation. The paper claims Y-Flash self-selects, eliminating sneak paths, but full-array electrical behavior is not directly measured for the 2048x500 array; the scalability discussion assumes this holds.
  • domain assumption The Y-Flash compact model used in simulation reproduces the measured device behavior.
    The variability study compares simulations to measurements for 96-100 devices and shows close alignment, providing partial support. However, the compact model itself is not public or independently verifiable.
  • domain assumption The CoTM software implementation (Glimsdal and Granmo) produces the TA and weight matrices used, and those matrices are correct.
    The paper uses a trained CoTM model on MNIST as a given. Training details are not in this paper; accuracy is cited from ref 19 and the authors' own scripts, with no independent benchmark of the software model.
  • domain assumption Input literals can be represented as floating nodes (Z) or VR = 2V without significant crosstalk or parasitic coupling.
    The clause crossbar uses Z to represent literal '1' to save power. This assumes the floating node does not disturb neighboring cells or cause unintended currents in the array.

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Cite this review

Pith. "Pith review of IMPACT:InMemory ComPuting Architecture Based on Y-FlAsh Technology for Coalesced Tsetlin Machine Inference." pith.science (2026). https://pith.science/paper/WBDQCDEQ

@misc{pith2026241205327,
  author       = {Pith},
  title        = {Pith review of: IMPACT:InMemory ComPuting Architecture Based on Y-FlAsh Technology for Coalesced Tsetlin Machine Inference},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/WBDQCDEQ}},
  note         = {Machine review of arXiv:2412.05327}
}
read the original abstract

The increasing demand for processing large volumes of data for machine learning models has pushed data bandwidth requirements beyond the capability of traditional von Neumann architecture. In-memory computing (IMC) has recently emerged as a promising solution to address this gap by enabling distributed data storage and processing at the micro-architectural level, significantly reducing both latency and energy. In this paper, we present the IMPACT: InMemory ComPuting Architecture Based on Y-FlAsh Technology for Coalesced Tsetlin Machine Inference, underpinned on a cutting-edge memory device, Y-Flash, fabricated on a 180 nm CMOS process. Y-Flash devices have recently been demonstrated for digital and analog memory applications, offering high yield, non-volatility, and low power consumption. The IMPACT leverages the Y-Flash array to implement the inference of a novel machine learning algorithm: coalesced Tsetlin machine (CoTM) based on propositional logic. CoTM utilizes Tsetlin automata (TA) to create Boolean feature selections stochastically across parallel clauses. The IMPACT is organized into two computational crossbars for storing the TA and weights. Through validation on the MNIST dataset, IMPACT achieved 96.3% accuracy. The IMPACT demonstrated improvements in energy efficiency, e.g., 2.23X over CNN-based ReRAM, 2.46X over Neuromorphic using NOR-Flash, and 2.06X over DNN-based PCM, suited for modern ML inference applications.

Figures

Figures reproduced from arXiv: 2412.05327 by the authors.

Figure 1
Figure 1. The coalesced Tsetlin machine algorithm data pipeline consisting of (a) the learning element of CoTM, Tsetlin Automata (TA), (b) the interaction of the TA with the related Boolean literals forms the clauses, and (c) the clauses’ weight matrix to produce the class output vector (Y). raw data points consist of numerical values representing various features. These features are encoded into a binary format. Thresholds a… view at source ↗
Figure 2
Figure 2. (a) The structure of a Y-Flash cell. (b) The symbol of two terminal Y-Flash devices. (c) The Y-Flash characteristics under negative bias (VDS < 0 V ) and positive bias (VDS > 0 V ) reading cycle where (e) and (f) are the two biasing configurations. (d) The simulated DC behavior for (ID − VD) and (ISR − VD) characteristics of the Y-Flash device during a reading pulse (VR = 2 V ) showing the two distinct Boolean condu… view at source ↗
Figure 3
Figure 3. The simulated analog turnability behavior of the Y-Flash device. (a) Programming from HCS to LCS. (b) Erasing from LCS to HCS. (c) Conductance values were measured at (VR = 2V ) for the programming cycles in (a). (d) Conductance values were measured at (VR = 2V ) for the erasing cycles in (b). the connection shown in Figure 2e where VD = 0 V and VS > 0 V, the transistors are switching off where the current flow is n… view at source ↗
Figures from the paper (11 more)
Figure 4
Figure 4. Figure 4: The IMPACT architecture shows the two designed arrays. (a) The clause crossbar tile functions in Boolean conductance mode for clause computation. (b) Class crossbar tile works in analog tunable conductance mode for class computation. (IDS − VDS) and conductance dynamic…
Figure 5
Figure 5. Figure 5: Generating the Boolean Clause. (a) Current sense amplifier design. (b) Detecting the include of literal “0” during the reading cycle. Where T A1 in the clause is storing an include action and interacted with input literal “0”. TAs (2 to 1024) interacted with literal “1…
Figure 6
Figure 6. Figure 6: Tuning the memristor conductance involves two stages for mapping the CoTM weights into the class crossbar tile. Initially, the integer software weights are adjusted by incrementing them by the absolute value of the smallest weight to ensure they are unsigned, making th…
Figure 7
Figure 7. Figure 7: An analysis of the cycle-to-cycle variation over 400 cycles. (a) The programming pulse cycle for the transition of the device’s state from HCS to LCS < 1 nS. (b and c) Display these LCS values and the associated statistical metrics. (d) The erasing pulse cycle for the …
Figure 8
Figure 8. Figure 8: The device-to-device variation in the conductance of Y-Flash. (a-c) the programming pulse, the measured and simulated LCS, and the distribution of LCS, respectively. (d-f) the erasing pulse, the measured and simulated HCS, and the distribution of HCS, respectively. dat…
Figure 9
Figure 9. Figure 9: Encoding the TA matrix of trained CoTM model for the MNIST dataset on clause crossbar Memory. (a) Represents a sample of the TAs after reaching their final state for the clauses between 75 and 90. (b) Transferring the numerical TA value to one of the two Boolean action…
Figure 10
Figure 10. Figure 10: The allocation of programming pulses for storing the actions of TA into the clause crossbar array. A pulse width of (1 ms) is used to store the exclude actions and program the cells from initial HCS ≈ 2.5 µS to LCS ≈ 1 nS. The inset figure shows the percentage of the …
Figure 11
Figure 11. Figure 11: Clause software weight matrix and class crossbar tile. (a) A sample of a unipolar software clause weight matrix for clauses ranging from 75 to 90. (b) After programming the allocated memory to store the clause weight matrix for clauses between 75 and 90 as tunable con…
Figure 12
Figure 12. Figure 12: Store the CoTM-trained model weights in the class crossbar tile. (a) Programming pulses applied during the pre-tuning stage: 5 V for 0.5 ms to transfer the related Wij ’s conductance to an LCS. (b) Erasing pulses applied during the pre-tuning stage: 8 V for 0.5 ms to …
Figure 13
Figure 13. Figure 13: Evaluation of the cost and accuracy of Y-Flash crossbars using a trained CoTM on the MNIST dataset. (a) Pre￾tuning stage. We observed a significant increase in accuracy with minimal pulses needed for transferring CoTM weights to their corresponding conductance in the …
Figure 14
Figure 14. Figure 14: Addressing the scalability to larger CoTM models using the modularity of the IMPACT architecture. (a) Parallel task distribution for Clause Computation Matrix. Each tile P in the matrix represents the maximum array size (n × K) of the IMPACT architecture. (b) Parallel…

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Reference graph

Works this paper leans on

31 extracted references · 27 canonical work pages

  1. [1]

    Memory devices and applications for in-memory computing,

    A. Sebastian, M. Le Gallo, R. Khaddam-Aljameh, and E. Eleftheriou, “Memory devices and applications for in-memory computing,” Nature nanotechnology, vol. 15, no. 7, pp. 529–544, 2020

    2020

  2. [2]

    Neural architecture search for in-memory computing-based deep learning accelerators,

    O. Krestinskaya, M. E. Fouda, H. Benmeziane, K. El Maghraoui, A. Sebastian, W. D. Lu, M. Lanza, H. Li, F. Kurdahi, S. A. Fahmy et al., “Neural architecture search for in-memory computing-based deep learning accelerators,” Nature Reviews Electrical Engineering, pp. 1–17, 2024

    work page 2024

  3. [3]

    2022 roadmap on neuromorphic computing and engineering,

    D. V . Christensen, R. Dittmann, B. Linares-Barranco, A. Sebastian, M. Le Gallo, A. Redaelli, S. Slesazeck, T. Mikolajick, S. Spiga, S. Menzel et al. , “2022 roadmap on neuromorphic computing and engineering,” Neuromorphic Computing and Engineering, vol. 2, no. 2, p. 022501, 2022

    work page 2022

  4. [4]

    MemSPICE: Automated simulation and energy estimation framework for MAGIC-based logic-in-memory,

    S. Singh, C. K. Jha, A. Bende, V . Rana, S. Patkar, R. Drechsler, and F. Merchant, “MemSPICE: Automated simulation and energy estimation framework for MAGIC-based logic-in-memory,” in2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC), 2024, pp. 282–287

    work page 2024

  5. [5]

    22.1 a 12.4TOPS/W @ 136GOPS AI-IoT system-on-chip with 16 RISC- V, 2-to-8b precision-scalable DNN acceleration and 30%-boost adaptive body biasing,

    F. Conti, D. Rossi, G. Paulin, A. Garofalo, A. Di Mauro, G. Rutishauer, G. m. Ottavi, M. Eggimann, H. Okuhara, V . Huard, O. Montfort, L. Jure, N. Exibard, P . Gouedo, M. Louvat, E. Botte, and L. Benini, “22.1 a 12.4TOPS/W @ 136GOPS AI-IoT system-on-chip with 16 RISC- V, 2-to-8b precision-scalable DNN acceleration and 30%-boost adaptive body biasing,” in2...

    work page 2023

  6. [6]

    Ferroelectric capacitors and field-effect transistors as in-memory computing elements for machine learning workloads,

    E. Yu, G. K. K, U. Saxena, and K. Roy, “Ferroelectric capacitors and field-effect transistors as in-memory computing elements for machine learning workloads,” Scientific Reports, vol. 14, no. 1, p. 9426, 2024

    work page 2024

  7. [7]

    A compute-in-memory chip based on resistive random-access memory,

    W. Wan, R. Kubendran, C. Schaefer, S. B. Eryilmaz, W. Zhang, D. Wu, S. Deiss, P . Raina, H. Qian, B. Gao et al. , “A compute-in-memory chip based on resistive random-access memory,” Nature, vol. 608, no. 7923, pp. 504–512, 2022

    work page 2022

  8. [8]

    Computational phase-change memory: Beyond von neumann computing,

    A. Sebastian, M. Le Gallo, and E. Eleftheriou, “Computational phase-change memory: Beyond von neumann computing,” Journal of Physics D: Applied Physics, vol. 52, no. 44, p. 443002, 2019

    work page 2019

Show all 31 references
  1. [9]

    A crossbar array of magnetoresistive memory devices for in-memory computing,

    S. Jung, H. Lee, S. Myung, H. Kim, S. K. Yoon, S.-W. Kwon, Y. Ju, M. Kim, W. Yi, S. Han et al., “A crossbar array of magnetoresistive memory devices for in-memory computing,” Nature, vol. 601, no. 7892, pp. 211–216, 2022

    2022

  2. [10]

    Current- mode carry-free multiplier design using a memristor-transistor crossbar architecture,

    S. Yu, A. Soltan, R. Shafik, T. Bunnam, F. Xia, D. Balsamo, and A. Yakovlev, “Current- mode carry-free multiplier design using a memristor-transistor crossbar architecture,” in2020 Design, Automation and Test in Europe Conference and Exhibition (DATE), 2020, pp. 638–641

    2020

  3. [11]

    Unsupervised learning in probabilistic neural networks with multi-state metal-oxide memristive synapses,

    A. Serb, J. Bill, A. Khiat, R. Berdan, R. Legenstein, and T. Prodromakis, “Unsupervised learning in probabilistic neural networks with multi-state metal-oxide memristive synapses,” Nature communications, vol. 7, no. 1, p. 12611, 2016

    2016

  4. [12]

    The Tsetlin Machine - A Game Theoretic Bandit Driven Approach to Optimal Pattern Recognition with Propositional Logic,

    O.-C. Granmo, “The Tsetlin Machine - A Game Theoretic Bandit Driven Approach to Optimal Pattern Recognition with Propositional Logic,” arXiv preprint arXiv:1804.01508, 2018. [Online]. Available: https://arxiv.org/abs/1804.01508

    2018 arXiv

  5. [13]

    Toward memristive in-memory computing: principles and applications,

    H. Bao, H. Zhou, J. Li, H. Pei, J. Tian, L. Yang, S. Ren, S. Tong, Y. Li, Y. He et al., “Toward memristive in-memory computing: principles and applications,” Frontiers of Optoelectronics , vol. 15, no. 1, p. 23, 2022. 26rsta.royalsocietypublishing.org Phil. Trans. R. Soc. A 0000000

    2022

  6. [14]

    In- memory computing with emerging memory devices: Status and outlook,

    P . Mannocci, M. Farronato, N. Lepri, L. Cattaneo, A. Glukhov, Z. Sun, and D. Ielmini, “In- memory computing with emerging memory devices: Status and outlook,” APL Machine Learning, vol. 1, no. 1, 2023

    2023

  7. [15]

    Standards for the characterization of endurance in resistive switching devices,

    M. Lanza, R. Waser, D. Ielmini, J. J. Yang, L. Goux, J. Suñe, A. J. Kenyon, A. Mehonic, S. Spiga, V . Ranaet al., “Standards for the characterization of endurance in resistive switching devices,” ACS nano, vol. 15, no. 11, pp. 17 214–17 231, 2021

    2021

  8. [16]

    A memristive deep belief neural network based on silicon synapses,

    W. Wang, L. Danial, Y. Li, E. Herbelin, E. Pikhay, Y. Roizin, B. Hoffer, Z. Wang, and S. Kvatinsky, “A memristive deep belief neural network based on silicon synapses,” Nature Electronics, vol. 5, no. 12, pp. 870–880, 2022

    2022

  9. [17]

    Two-terminal floating-gate transistors with a low-power memristive operation mode for analogue neuromorphic computing,

    L. Danial, E. Pikhay, E. Herbelin, N. Wainstein, V . Gupta, N. Wald, Y. Roizin, R. Daniel, and S. Kvatinsky, “Two-terminal floating-gate transistors with a low-power memristive operation mode for analogue neuromorphic computing,” Nature Electronics, vol. 2, no. 12, pp. 596–605, 2019

    2019

  10. [18]

    Physical based compact model of Y-Flash memristor for neuromorphic computation,

    W. Wang, L. Danial, E. Herbelin, B. Hoffer, B. Oved, T. Greenberg-Toledo, E. Pikhay, Y. Roizin, and S. Kvatinsky, “Physical based compact model of Y-Flash memristor for neuromorphic computation,” Applied Physics Letters, vol. 119, no. 26, 2021

    2021

  11. [19]

    Coalesced multi-output tsetlin machines with clause sharing,

    S. Glimsdal and O.-C. Granmo, “Coalesced multi-output tsetlin machines with clause sharing,” arXiv preprint arXiv:2108.07594, 2021

    2021 arXiv

  12. [20]

    IMBUE: In-memory boolean-to-current inference architecture for tsetlin machines,

    O. Ghazal, S. Singh, T. Rahman, S. Yu, Y. Zheng, D. Balsamo, S. Patkar, F. Merchant, F. Xia, A. Yakovlev, and R. Shafik, “IMBUE: In-memory boolean-to-current inference architecture for tsetlin machines,” in 2023 IEEE/ACM International Symposium on Low Power Electronics and Des...

    2023

  13. [21]

    REDRESS: Generating compressed models for edge inference using tsetlin machines,

    S. Maheshwari, T. Rahman, R. Shafik, A. Yakovlev, A. Rafiev, L. Jiao, and O.-C. Granmo, “REDRESS: Generating compressed models for edge inference using tsetlin machines,” IEEE Transactions on Pattern Analysis and Machine Intelligence, vol. 45, no. 9, pp. 11 152–11 168, 2023

    2023

  14. [22]

    Asynchronous control for tsetlin machine with binary memristor-transistor array,

    O. Ghazal, G. Maot, T. Lan, J. Ojukwu, F. Xia, A. Yakovlev, and R. Shafik, “Asynchronous control for tsetlin machine with binary memristor-transistor array,” in2023 IEEE International Symposium on Circuits and Systems (ISCAS), 2023, pp. 1–5

    2023

  15. [23]

    An optimized toolbox for advanced image processing with tsetlin machine composites,

    Y. Grønningsæter, H. S. Smørvik, and O.-C. Granmo, “An optimized toolbox for advanced image processing with tsetlin machine composites,” arXiv preprint arXiv:2406.00704, 2024

    2024 arXiv

  16. [24]

    Fully hardware- implemented memristor convolutional neural network,

    P . Yao, H. Wu, B. Gao, J. Tang, Q. Zhang, W. Zhang, J. J. Yang, and H. Qian, “Fully hardware- implemented memristor convolutional neural network,” Nature, vol. 577, no. 7792, pp. 641– 646, 2020

    2020

  17. [25]

    High-performance mixed-signal neurocomputing with nanoscale floating-gate memory cell arrays,

    F. Merrikh-Bayat, X. Guo, M. Klachko, M. Prezioso, K. K. Likharev, and D. B. Strukov, “High-performance mixed-signal neurocomputing with nanoscale floating-gate memory cell arrays,” IEEE Transactions on Neural Networks and Learning Systems , vol. 29, no. 10, pp. 4782–4790, 2018

    2018

  18. [26]

    CONV-SRAM: An energy-efficient SRAM with in- memory dot-product computation for low-power convolutional neural networks,

    A. Biswas and A. P . Chandrakasan, “CONV-SRAM: An energy-efficient SRAM with in- memory dot-product computation for low-power convolutional neural networks,” IEEE Journal of Solid-State Circuits, vol. 54, no. 1, pp. 217–230, 2019

    2019

  19. [27]

    Accurate deep neural network inference using computational phase-change memory,

    V . Joshi, M. Le Gallo, S. Haefeli, I. Boybat, S. R. Nandakumar, C. Piveteau, M. Dazzi, B. Rajendran, A. Sebastian, and E. Eleftheriou, “Accurate deep neural network inference using computational phase-change memory,” Nature communications, vol. 11, no. 1, p. 2473, 2020

    2020

  20. [28]

    A Nonvolatile Al-Edge Processor with 4MB SLC-MLC Hybrid-Mode ReRAM Compute-in-Memory Macro and 51.4-251TOPS/W,

    W.-H. Huang, T.-H. Wen, J.-M. Hung, W.-S. Khwa, Y.-C. Lo, C.-J. Jhang, H.-H. Hsu, Y.-H. Chin, Y.-C. Chen, C.-C. Lo, R.-S. Liu, K.-T. Tang, C.-C. Hsieh, Y.-D. Chih, T.-Y. Chang, and M.-F. Chang, “A Nonvolatile Al-Edge Processor with 4MB SLC-MLC Hybrid-Mode ReRAM Compute-in-Memo...

    2023

  21. [29]

    33.4 A 28nm 2Mb STT-MRAM Computing-in-Memory Macro with a Refined Bit- Cell and 22.4 - 41.5TOPS/W for AI Inference,

    H. Cai, Z. Bian, Y. Hou, Y. Zhou, J.-l. Cui, Y. Guo, X. Tian, B. Liu, X. Si, Z. Wang, J. Yang, and W. Shan, “33.4 A 28nm 2Mb STT-MRAM Computing-in-Memory Macro with a Refined Bit- Cell and 22.4 - 41.5TOPS/W for AI Inference,” in 2023 IEEE International Solid-State Circuits Con...

    2023

  22. [30]

    A 22nm Nonvolatile AI-Edge Processor with 21.4TFLOPS/W using 47.25Mb Lossless-Compressed-Computing STT-MRAM Near-Memory-Compute Macro,

    D.-Q. You, W.-S. Khwa, J.-J. Wu, C.-J. Jhang, G.-Y. Lin, P .-J. Chen, T.-C. Chiu, F.-Y. Chen, A. Lee, Y.-C. Hung, C.-C. Lo, R.-S. Liu, C.-C. Hsieh, K.-T. Tang, Y.-D. Chih, T.-Y. J. Chang, and M.-F. Chang, “A 22nm Nonvolatile AI-Edge Processor with 21.4TFLOPS/W using 47.25Mb Lo...

    2024

  23. [31]

    A 28nm Nonvolatile AI Edge Processor using 4Mb Analog-Based Near-Memory-Compute ReRAM with 27.2 TOPS/W for Tiny AI Edge Devices,

    T.-H. Wen, J.-M. Hung, H.-H. Hsu, Y. Wu, F.-C. Chang, C.-Y. Li, C.-H. Chien, C.-I. Su, W.- S. Khwa, J.-J. Wu, C.-C. Lo, R.-S. Liu, C.-C. Hsieh, K.-T. Tang, M.-S. Ho, Y.-D. Chih, T.-Y. J. 27rsta.royalsocietypublishing.org Phil. Trans. R. Soc. A 0000000. . . . . . . . . . . . . ...

    2023

Pith tools

Reviewed August 11, 2026 · model on record in the stance chip above.