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REVIEW 4 major objections 5 minor 70 references

Tailored 1D/2D Van der Waals Heterostructures for Unified Analog and Digital Electronics

T0 review · 4 major / 5 minor · reviewed 2026-08-11 · deepseek-v4-flash

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Pith's one-line read A two-step vapor recipe makes p-n diodes and CMOS logic on one chip.

desk verdict A promising two-step vapor-growth route to mixed-dimensional Te/MoS2 circuits on one wafer, but the KPFM and Raman interpretations are internally inconsistent and need thorough correction before the band-alignment and charge-transfer claims can be trusted. read the letter →

arxiv 2412.09291 v1 pith:LWVUJVAV submitted 2024-12-12 cond-mat.mes-hall cond-mat.mtrl-sciphysics.app-ph

Bipul Karmakar , Bikash Das , Shibnath Mandal , Rahul Paramanik , Sujan Maity , Tanima Kundu , Soumik Das , Mainak Palit
show 3 more authors
Koushik Dey Kapildeb Dolui Subhadeep Datta
This is my paper · ORCID
classification cond-mat.mes-hallcond-mat.mtrl-sciphysics.app-ph
keywords TeNWMoS2vapordepositionvdWp-njunctionionicliquidgatingCMOSinverterlogicgates1D/2Dheterostructure
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

This paper claims that a two-step vapor deposition sequence—CVD for MoS2 flakes, then PVD for Te nanowires—can grow mixed-dimensional van der Waals heterostructures directly on a single SiO2 wafer, with the junction and the isolated materials available as devices on the same substrate. If true, the method would remove the exfoliate-and-restack step that usually limits vdW heterostructure fabrication, and would put diodes, p-type and n-type transistors, and CMOS logic within one platform. The paper supports the claim by showing gate-tunable rectification at the Te NW/MoS2 junction, an estimated atomically thin depletion region of about 6.85 nm, and working ionic-liquid-gated FETs that form an inverter and AND, OR, and NOT gates.

What carries the argument

The central object is the 1D/2D van der Waals heterojunction formed where a tellurium nanowire crosses an MoS2 flake, created in place by a two-step vapor deposition process: atmospheric-pressure CVD grows MoS2 on SiO2/Si, and subsequent PVD grows Te nanowires over and around it. That junction carries a gate-tunable p-n diode with an atomically thin depletion region; Kelvin probe force microscopy-derived work functions set the band alignment, and an ionic liquid electric double layer supplies the high gate capacitance used to run the CMOS inverter and logic gates from the same substrate.

What would settle it

Measure the contact-potential difference of the same Te NW/MoS2 junction against a reference metal with a calibrated Kelvin probe or ultraviolet photoemission spectroscopy; if the extracted work functions do not satisfy $W_{\mathrm{Te}} < W_{\mathrm{MoS_2}}$, then the type-I alignment, the 0.19 V built-in potential, and the 6.85 nm depletion width do not follow.

Watch

Extended reading notes

Core claim

The central discovery is that Te nanowires and MoS2 flakes grown sequentially by vapor deposition on one SiO2/Si substrate form a working mixed-dimensional electronics platform. At the overlapping Te NW/MoS2 junction, the paper reports a type-I band alignment with a built-in potential of about 0.19 V, a total depletion width of 6.85 nm, and a gate-tunable diode whose rectification ratio reaches around 180; first-principles transport calculations are presented as supporting the band bending and charge redistribution. Away from the junctions, the same growth gives p-type Te nanowire FETs and n-type MoS2 FETs whose performance is enhanced by ionic liquid gating, and these are combined into a CMOS inverter with a gain of 1.2 and static power near 10 nW, plus pass-transistor AND, OR, and NOT gates.

Load-bearing premise

The load-bearing premise is that the Kelvin probe surface-potential measurement correctly orders the work functions, with Te at 4.96 eV and MoS2 at 5.15 eV; if that ordering is wrong, the built-in potential, band offsets, and 6.85 nm depletion width are not established.

Editorial extensions

If this is right

  • The same wafer can provide p-type Te FETs, n-type MoS2 FETs, and Te/MoS2 diodes, so mixed-signal circuits no longer require transfer, stacking, or separate substrates.
  • A depletion width near 6.85 nm with an internal field around $3\times10^7$ V/m means the junction is atomically abrupt by the paper's estimate.
  • Ionic liquid gating raises both FET types to comparable on-off ratios around $\sim5\times10^4$, which the paper identifies as the key to building a working CMOS inverter on this platform.
  • AND, OR, and NOT gates built from the same IL-gated FETs follow their truth tables, so basic digital logic can be made entirely from 1D/2D heterostructures.
  • The observed density of 15-20 heterojunctions and 50-60 MoS2 flakes per 130 µm by 130 µm area suggests the growth route can be scaled to centimeter-scale templates.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • If the growth route is as general as the proof of concept suggests, other p-type 1D materials and n-type 2D channels could be substituted into the same two-step recipe, extending it from Te/MoS2 to a family of mixed-dimensional circuits.
  • The paper leaves junction capacitance and high-frequency rectifier operation as future work; measuring those quantities would directly test whether the 6.85 nm depletion region behaves as atomically thin in dynamic operation.
  • Since Te nanowires have an antenna effect and MoS2 photoluminescence is quenched at the junction, the same platform is a plausible basis for integrated photodetection and optoelectronic logic beyond the electrical gates demonstrated.
  • A direct measurement of the interface dipole, for example via surface potential under illumination or a band-bending-sensitive photoemission shift, would settle the relation between the KPFM-based electron transfer from MoS2 to Te and the paper's Bader charge analysis.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

4 major / 5 minor

Summary. This manuscript reports a sequential two-step vapor deposition route (CVD for MoS2, then PVD for Te nanowires) that produces mixed-dimensional van der Waals heterostructures on a single SiO2/Si substrate. The authors characterize the Te NW/MoS2 junctions as gate-tunable p-n diodes, extract a total depletion width of about 6.85 nm, and propose a type-I band alignment with a built-in potential of 0.19 V supported by KPFM, Raman spectroscopy, electrical transport, CAFM, and DFT-NEGF calculations. In the same platform, the isolated Te NWs and MoS2 flakes are used as p- and n-FETs, and ionic-liquid gating is used to demonstrate a CMOS inverter and AND/OR/NOT logic gates. The central claim is that this approach unifies analog diode devices and digital CMOS logic on one chip.

Significance. If the results hold, the paper would demonstrate a scalable, lithography-compatible route to mixed-dimensional 1D/2D vdW electronics, avoiding manual exfoliation and stacking. The breadth is a clear strength: growth, structural and optical characterization, transport measurements, first-principles transport calculations, and circuit-level demonstrations are all present. However, the quantitative diode picture—built-in potential, depletion width, band offsets, and charge-transfer direction—rests on a KPFM analysis whose sign convention is internally inconsistent. Because this inconsistency affects the central mechanistic claim, the paper cannot be accepted in its current form. The issue is potentially fixable, so I do not recommend rejection, but the experimental interpretation must be re-derived and clearly stated.

major comments (4)
  1. [Section II, KPFM paragraph] The KPFM analysis is internally inconsistent. The paper defines ΔVCPD = (W_substrate − W_sample)/e and then quotes W_Te = 4.96 eV and W_MoS2 = 5.15 eV with W_substrate = 5.05 eV. The same paragraph states that MoS2 has a higher surface potential than Te by ΔVCPD = 0.14 V and a higher surface potential than SiO2 by ΔVCPD = −0.10 V. Under the stated convention, a higher surface potential corresponds to a lower work function, so the reported contrast implies W_MoS2 < W_Te, opposite to the assigned values. The sentence about Te also appears garbled ('Te has lower (ΔVCPD = 0.09) work function than SiO2'). This contradiction matters because W_MoS2 − W_Te = 0.19 eV is used to define the built-in potential, the electron transfer direction from MoS2 to Te, and the type-I band offsets. The DFT Bader analysis in the same paper says electrons transfer from Te to MoS2, which is consistent with W_Te < W_MoS2 and not with the text's claimed MoS2→Te direction. The authors must re-derive the work functions from the raw KPFM data, state the sign convention unambiguously, and either reconcile the charge-transfer direction or revise the band-alignment and depletion-width conclusions (Vbi, ΔEC, ΔEV, WTe, WMoS2).
  2. [Section II, Raman characterization and Fig. 1(e) caption] The Raman evidence for charge transfer is presented with contradictory directions. The text says the MoS2 modes in the overlapped region show a finite red shift and interprets this as electron transfer from MoS2 to the Te NW. The caption of Fig. 1(e), however, says the inset shows an up shift of both MoS2 characteristic peaks in the overlapped region relative to pristine MoS2. Red shift and up shift are opposite observations. Since Raman is one of the two experimental probes used to establish the charge-transfer direction, the authors must report the actual measured peak positions (pristine MoS2 vs overlapped region) and state whether the shift is to lower or higher wavenumber; the present inconsistency leaves the Raman-based charge-transfer claim unsupported.
  3. [Section II, CAFM and gate-tunable rectification paragraphs] The paper reports two different values for the maximum rectification ratio without reconciling them. In the CAFM paragraph, the heterojunction is said to yield a current rectification ratio of around 400 at ±10 V tip voltage. Two paragraphs later, the text states that the diode's highest rectification ratio is 180 at V_DS = 4, and the Conclusions repeat the value ~180. If these are different devices, different bias conditions, or different measurement techniques, that must be stated explicitly. As written, the reader cannot determine the actual maximum rectification ratio of the diode, which is a central quantitative device characteristic.
  4. [Section II, Theoretical results, and Fig. 3 caption] The doping density used in the DFT-NEGF simulation is not matched to the experimental values and is described with an apparent typo. The text says the simulation uses experimentally relevant doping densities of 10^14 cm^-3, while the Fig. 3 caption reads a carrier density of 10^-14 cm^-3, which is unphysical as a doping density. Even taking the intended value as 10^14 cm^-3, this is orders of magnitude smaller than the measured NA = 1.05 × 10^19 cm^-3 and ND = 2.36 × 10^18 cm^-3 reported earlier in the same paper. The claim that the DFT calculation 'confirms' the experimental band bending and built-in potential is therefore not quantitatively grounded. The authors should specify the compensation-charge model, give the actual charge densities used, and either match the experimental doping regime or clearly state that the DFT result is only qualitative.
minor comments (5)
  1. [Section II, rectification ratio sentence] The sentence defining the rectification ratio says 'which compares forward current (If) and reverse currents (If)'—the second symbol should be Ir; please correct the notation.
  2. [Abstract and Section I] The phrase 'defect-free interfaces' is used as a claim, but the paper provides no atomic-scale evidence (e.g., TEM or STM) for the absence of defects. I suggest tempering the wording to 'clean interfaces' or adding supporting evidence.
  3. [Section II, FET mobility paragraph] The Te NW FET on-off ratio is reported as ~6.4, which is very low for a field-effect transistor; please specify whether this is the ratio of maximum to minimum current within the measured back-gate window and whether the device is fully depleted at negative gate voltages.
  4. [Section II, KPFM sentence] The sentence 'while Te has lower (ΔVCPD = 0.09) work function than SiO2' is grammatically ambiguous; it is unclear whether ΔVCPD = 0.09 refers to a surface-potential difference or a work-function difference.
  5. [References and comparison to prior work] References [36] and [37] already report Te/MoS2 1D/2D diodes and depletion-width estimates obtained by other growth methods; the Introduction and Conclusions should state more explicitly what new capability the present sequential CVD/PVD approach adds relative to those works.

Circularity Check

0 steps flagged · score 0.0 of 10

No significant circularity: the depletion-width, built-in potential, and band-alignment numbers are derived from measured inputs via standard formulas, not from the claims they support; the flagged KPFM sign inconsistency is a correctness/consistency issue, not a circular derivation.

full rationale

The paper's quantitative derivation chain is not circular. The depletion width (Wtotal = 6.85 nm) is computed from standard textbook formulas using NA and ND extracted from FET transfer curves, Vbi from KPFM work-function differences, and literature dielectric constants. The built-in potential (0.19 eV) is a converted KPFM measurement, not a fitted parameter, and it is not subsequently used to regenerate the measured I-V curves. The DFT/NEGF calculation imposes an explicit doping density (10^14 cm^-3) and is compared with experiment only in order of magnitude (Vint ~ 0.4 V vs ~0.19 V); this is a loose independent comparison, not the use of experimental output as input. No author-specific uniqueness theorem or self-citation chain is load-bearing; the cited formulas and prior junction results come from the general literature. I do flag a serious internal inconsistency in Section II: the text states 'MoS2 has higher surface potential than both Te (ΔVCPD = 0.14) and SiO2 (ΔVCPD = -0.10)' and then assigns W_MoS2 = 5.15 eV and W_Te = 4.96 eV. Under the paper's own convention, ΔVCPD = (W_substrate − W_sample)/e, higher surface potential corresponds to lower work function, so the assigned values, the claimed MoS2→Te electron transfer, and the DFT Bader result (Te→MoS2) are mutually inconsistent. This threatens the Vbi, band-offset, and charge-transfer interpretation, but it is an interpretative/measurement inconsistency, not a case of a prediction reducing by construction to its inputs. Therefore the circularity score is 0.

Assumptions & free parameters 6 free parameters · 5 assumptions · 0 invented entities

No new physical entities are introduced. The 'atomic compensation charge' used in the DFT simulation is a computational doping scheme, not a postulated physical object, and it has no independent falsifiable handle beyond the simulation itself.

free parameters (6)
  • Acceptor concentration NA (Te NW) = 1.05 x 10^19 cm^-3
    Extracted from the Te NW FET drain current at VBG = 0 V using NA = IDS L / (pi e mu_p VDS r^2). Used in the depletion width estimate.
  • Donor concentration ND (MoS2) = 2.36 x 10^18 cm^-3
    Extracted from the MoS2 FET drain current at VBG = 0 V using ND = IDS L / (e mu_n VDS t W). Used in the depletion width estimate.
  • Built-in potential Vbi = 0.19 V (from KPFM work functions)
    Obtained from the Fermi level difference between Te and MoS2 as derived from KPFM surface potential measurements. Used in the depletion width and electric field calculations.
  • KPFM-derived work functions (W_Te, W_MoS2) = 4.96 eV, 5.15 eV
    Computed from delta V_CPD using W_substrate = 5.05 eV. These values set the band alignment (type-I, delta EC = 0.36 eV, delta EV = 1.09 eV) but appear inconsistent with the stated KPFM contrast.
  • Doping density in DFT-NEGF simulation = 10^14 cm^-3 (text; figure caption says 10^-14 cm^-3)
    Chosen 'experimentally relevant' compensation charge in the QuantumATK simulation. This is six orders of magnitude lower than the experimental NA/ND values, so the simulated band bending may not reflect the measured devices.
  • Ideality factors = 2.60 (transport), 3.15 (CAFM)
    Extracted from I-V curve fits using n = (e/kBT) dV/d(ln I). Reported without error bars.
assumptions (5)
  • domain assumption The abrupt planar p-n junction depletion approximation applies to a 1D Te nanowire / 2D MoS2 van der Waals heterojunction.
    Used to compute W_Te and W_MoS2 (5.59 nm and 1.26 nm) from the standard formulas. The geometry is not an abrupt planar junction, so the depletion width estimate is approximate.
  • domain assumption The substrate work function is exactly 5.05 eV and the KPFM contact potential difference relation delta V_CPD = (W_substrate - W_sample)/e holds.
    Invoked to convert surface potential contrasts into absolute work functions. Any error in the substrate work function propagates into the band alignment and built-in potential.
  • domain assumption PBE-GGA with Grimme DFT-D2 describes the band alignment and charge transfer in the Te/MoS2 vdW heterostructure accurately.
    Used in both VASP (electronic structure) and QuantumATK (NEGF transport). PBE is known to underestimate band gaps, which affects the computed band offsets and the claimed type-I alignment.
  • domain assumption The drain current of each FET at VBG = 0 V is dominated by the channel doping and the extracted mobility is correct.
    Underlies the extraction of NA and ND from the transfer curves. Contact resistances and gate leakage would bias these values.
  • domain assumption The ionic liquid (DEME-TFSI) creates an ideal electric double layer without electrochemical reactions or doping artifacts.
    The IL-gated CMOS and logic gates rely on stable EDL gating at +/-2 V. The paper notes leakage current (0.1 nA at 1 V) and initial doping effects at VLG = 0.

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Cite this review

Pith. "Pith review of Tailored 1D/2D Van der Waals Heterostructures for Unified Analog and Digital Electronics." pith.science (2026). https://pith.science/paper/LWVUJVAV

@misc{pith2026241209291,
  author       = {Pith},
  title        = {Pith review of: Tailored 1D/2D Van der Waals Heterostructures for Unified Analog and Digital Electronics},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/LWVUJVAV}},
  note         = {Machine review of arXiv:2412.09291}
}
abstract

We report a sequential two-step vapor deposition process for growing mixed-dimensional van der Waals (vdW) materials, specifically Te nanowires (1D) and MoS$_2$ (2D), on a single SiO$_2$ wafer. Our growth technique offers a unique potential pathway to create large scale, high-quality, defect-free interfaces. The assembly of samples serves a twofold application: first, the as-prepared heterostructures (Te NW/MoS$_2$) provide insights into the atomically thin depletion region of a 1D/2D vdW diode, as revealed by electrical transport measurements and density functional theory-based quantum transport calculations. The charge transfer at the heterointerface is confirmed using Raman spectroscopy and Kelvin probe force microscopy (KPFM). We also observe modulation of the rectification ratio with varying applied gate voltage. Second, the non-hybrid regions on the substrate, consisting of the as-grown individual Te nanowires and MoS$_2$ microstructures, are utilized to fabricate separate p- and n-FETs, respectively. Furthermore, the ionic liquid gating helps to realize low-power CMOS inverter and all basic logic gate operations using a pair of n- and p- field-effect transistors (FETs) on Si/SiO$_2$ platform. This approach also demonstrates the potential for unifying diode and CMOS circuits on a single platform, opening opportunities for integrated analog and digital electronics.

Figures

Figures reproduced from arXiv: 2412.09291 by the authors.

Figure 1
Figure 1. FIG. 1. Schematic of growth setup and characterisation of as-grown Te-MoS [PITH_FULL_IMAGE:figures/full_fig_p022_1.png] view at source ↗
Figure 2
Figure 2. FIG. 2. Electrical transport measurement on SiO [PITH_FULL_IMAGE:figures/full_fig_p023_2.png] view at source ↗
Figure 3
Figure 3. FIG. 3. (a) Top and side views of a two-terminal device consisting of a monolayer MoS [PITH_FULL_IMAGE:figures/full_fig_p024_3.png] view at source ↗
Figures from the paper (2 more)
Figure 4
Figure 4. Figure 4: FIG. 4. (a) Schematic of an SiO [PITH_FULL_IMAGE:figures/full_fig_p025_4.png]
Figure 5
Figure 5. Figure 5: FIG. 5. CMOS and logic-gates using ionic-liquid gating. (a) Voltage transfer (V [PITH_FULL_IMAGE:figures/full_fig_p026_5.png]

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