Pith. sign in

REVIEW 4 major objections 5 minor 65 references

USEFUSE: Uniform Stride for Enhanced Performance in Fused Layer Architecture of Deep Neural Networks

T0 review · 4 major / 5 minor · reviewed 2026-08-11 · deepseek-v4-flash

Challenge this review Re-run · record.json Download PDF Read on arXiv ↗ Review JSON

Pith's one-line read USEFUSE, a fused CNN accelerator using most-significant-digit-first arithmetic, reports 1.43x-1.87x speedups and 42-49% energy savings without accuracy loss.

desk verdict The uniform-stride scheduling idea is solid and worth a look; the early-termination scheme is the load-bearing part that isn't proven. read the letter →

arxiv 2412.13724 v2 pith:MSL2YDDW submitted 2024-12-18 cs.LG cs.ARcs.PF

Muhammad Sohail Ibrahim , Muhammad Usman , Jeong-A Lee This is my paper · ORCID
classification cs.LGcs.ARcs.PF
keywords onlinearithmeticmost-significant-digit-firstCNNacceleratorlayerfusionuniformtilestrideearlynegativedetectionReLUFPGAimplementation
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

The paper proposes an FPGA accelerator for CNNs that fuses several convolution layers into one pyramid of tiles and computes every sum-of-products with most-significant-digit-first online arithmetic, so partial results stream directly into the next layer instead of going back to off-chip memory. It also chooses a uniform tile stride across pyramid levels, which removes synchronization stalls and duplicate recomputation, and adds an early negative-detection unit that stops computations that ReLU would zero out. The central claim is that this combination is faster and more energy-efficient than conventional bit-serial fused designs: 1.43x, 1.58x, and 1.87x speedups on VGG, AlexNet, and LeNet-5 with 42.6-48.5% energy savings and no measured accuracy loss. A second, temporal design trades area for latency and still achieves 1.46x-1.68x speedups with far fewer logic resources, making the approach relevant for both mission-critical and resource-constrained edge devices.

What carries the argument

The load-bearing mechanism is the fusion pyramid combined with most-significant-digit-first online arithmetic. Tile dimensions are propagated backward from an output region with $D_l = (D_o - 1)S_l + K_l$, and a uniform tile stride is chosen per layer so that the number of tile movements $\alpha = (IFM_j - H_j)/p + 1$ is the same integer at every level, maximizing the stride to minimize overlap. Inside each pixel processing unit, window processing units compute $K \times K \times N$ inner products with online serial-parallel multipliers using radix-2 signed digits $\{-1,0,1\}$ and online delay $\delta = 2$; an early negative detection unit compares the accumulated positive and negative output digit streams $z^+[j]$ and $z^-[j]$ and stops a convolution when $z^+[j] < z^-[j]$. The most-significant-digit-first output lets the next pyramid level start before the previous one finishes, which is what reduces intermediate buffering.

What would settle it

Take one fused convolution layer with fixed n-bit quantized inputs and weights and compare the exact signed convolution output against the early-termination decision of Algorithm 2 for all input patches, or a large randomized sample. If any patch has a negative prefix but a positive exact output, the skipped computation would change the ReLU result and the no-accuracy-loss claim fails; a brute-force search over 8-bit operands should reveal such a case if the missing tail bound is false.

Watch

Extended reading notes

Core claim

On its own terms, the paper claims that the bottleneck in fused CNN accelerators is not just arithmetic speed but the stride of the moving tile: if each pyramid level strides by its own convolution stride, levels move at different rates, forcing stalls, extra overlap, and re-buffering. USEFUSE selects, for each layer, the largest tile stride that keeps the number of tile movements integer and identical across all pyramid levels, and it shows this uniform stride improves operational intensity while reusing overlapped output pixels rather than recomputing them. The compute units are sum-of-products (SOP) engines built from online serial-parallel multipliers operating in a radix-2 signed-digit representation, whose most-significant-digit-first output lets an early negative detection unit terminate a convolution as soon as the redundant positive and negative digit streams show a negative prefix. Measured on an FPGA at 100 MHz, the spatial design outperforms the conventional bit-serial fused design by 1.43x-1.87x and cuts energy by 42.6-48.5% for VGG-16, AlexNet, and LeNet-5, while the temporal design achieves 1.46x-1.68x speedups with a fraction of the logic area.

Load-bearing premise

The load-bearing premise is that once the most-significant-digit partial sum is negative, the uncomputed lower-order digits cannot make the final convolution output positive, so terminating early never changes the post-ReLU result; the paper verifies this empirically on selected filters but gives no mathematical bound.

Editorial extensions

If this is right

  • If the measured speedups hold, fused-layer CNN accelerators can shrink on-chip buffers, because most-significant-digit-first output digits can be fed to the next layer immediately, cutting BRAM use by up to 5.2x on VGG-16 in the temporal design.
  • Uniform tile stride would make multi-layer fusion practical for deeper networks, such as the four fused convolution layers tested in VGG-16, without cross-level synchronization stalls.
  • Early negative detection would reduce energy for any ReLU-based CNN, with roughly 41-43% of first-layer activations detected negative on AlexNet and VGG-16 in the paper's measurements.
  • The temporal design gives a resource-constrained path to similar speedups, achieving 1.46x-1.68x over the conventional bit-serial fused baseline while using a fraction of the logic resources.
  • For ResNet-18, the early detection technique saves up to 50.1% of effective computation cycles in an end-to-end fused run in the paper's experiment.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • The no-accuracy-loss claim is only as strong as an unproven tail bound: if low-order digits can flip a negative prefix to a positive total, some pruned convolutions would be computed incorrectly. A conservative detector that waits until the maximum possible tail contribution is below the current negative margin would make the guarantee rigorous at some cost in savings.
  • The reported energy savings are measured on ten random filters of first convolution layers over 10,000 images; real deployments with different data and weights could see different fractions of negative activations and thus different savings.
  • The uniform-stride idea is a general nested-tiling principle and could be applied outside CNNs, for example to fused transformer attention or multi-stage stencil pipelines where tiles of different sizes must move in lockstep.
  • Because early termination relies on ReLU, the method's benefit is tied to ReLU-dominated networks; extending it to GELU or softmax would require implementing those activations in online arithmetic, which the paper leaves as future work.
Share X Bluesky LinkedIn Reddit HN

Signed reviews

No signed human review yet.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

4 major / 5 minor

Summary. The paper proposes USEFUSE, a fused-layer CNN accelerator built around most-significant-digit-first (MSDF) online arithmetic sum-of-products units. The contributions are (i) online-arithmetic window processing units, (ii) a layer-fusion methodology with a uniform tile stride computed by Algorithm 4, (iii) early termination of convolutions whose activations would be zeroed by ReLU (Algorithm 2), and (iv) two accelerator variants, a spatial design DS-1 and a temporal design DS-2. Against three baselines, the paper reports 1.43x-1.87x speedups and 42.6%-48.5% energy savings, and it also compares with several previous FPGA accelerators. The main claims are that the uniform stride improves operational intensity and that early termination saves energy without accuracy loss.

Significance. If the speedup, energy, and no-accuracy-loss claims are established, the paper makes a useful contribution: it combines online arithmetic with fused-layer tiling in a concrete FPGA-oriented design, and the Baseline-3 comparison isolates the benefit of the proposed tile stride from the benefit of online arithmetic. The paper also provides RTL descriptions and FPGA implementation results, which is a strength. However, the central correctness property of the early termination rule is asserted rather than proved, and the cycle counts underlying the headline speedups are not validated against RTL simulation, which leaves the quantitative claims less firmly supported than they could be.

major comments (4)
  1. [Section 3.2, Algorithm 2] The no-accuracy-loss claim for early termination is not rigorously established. The condition z+[j] < z−[j] can be made correct by a short tail-bound argument: because the positive and negative bit strings are compared as length-j binary fractions, a strict negative prefix is at most −2^{−j}, while the maximum contribution of all remaining radix-2 signed digits is 2^{−j}, so the final result cannot be positive. The manuscript, however, does not provide this or any equivalent argument, and instead relies on the post-hoc feature-map inspection in Section 4.3 (Fig. 12), which covers only 10 random filters of the first convolution layers and does not report end-to-end classification accuracy with and without END. Please add a formal correctness proof for Algorithm 2 and report accuracy comparisons for the full tested networks; otherwise the phrase 'without accuracy loss' is unsupported.
  2. [Section 3.3.2, Algorithm 4] The uniform stride method is not shown to be always feasible. Algorithm 4 collects candidate strides p that make alpha(i,j,p) integral, and the text states that values of ST resulting in the same alpha for every layer 'can be evaluated' and 'obtained,' but no proof is given that such a common integer alpha exists for arbitrary CNN layer dimensions and tile sizes. Since the central fusion claim is that a uniform tile movement is guaranteed, please either prove existence under explicit conditions, state the conditions under which Algorithm 4 succeeds, or describe the fallback when no common alpha exists, and report the chosen alpha/ST values for LeNet-5, AlexNet, VGG, and ResNet-18.
  3. [Section 4.2, Eqs. (3)-(4); Section 4.3, Tables 1-4] The performance and latency numbers appear to be computed from analytic cycle formulas, but the paper does not validate Eqs. (3)-(4) against cycle-accurate RTL simulation or on-FPGA timing. The RTL is described as 'functionally verified,' which does not establish that the analytic cycle counts capture pipeline stalls, tile-movement overhead, or memory conflicts. This is load-bearing because the 1.43x-1.87x speedups are derived from these durations. In addition, Table 2 contains an arithmetically inconsistent VGG CONV1 row: 173,408,256 operations at 1243.10 GOPS requires 139.5 microseconds, not 13.95 microseconds, and the proposed-design entry correspondingly requires 86.4 microseconds, not 8.64 microseconds; with these corrected values the per-layer durations no longer sum to the reported fused duration. Please validate the cycle model against RTL and correct the table.
  4. [Section 4.3, Figs. 12-14 and Section 5] The claimed energy savings from early termination are not accompanied by an accuracy measurement. Figures 12-14 quantify how many activations are terminated and how many cycles are saved, but the paper never reports classification accuracy of the full network with and without the END mechanism. The statement in the limitations section that END 'limits the applicability to models relying on ReLU' is appropriate, but it does not replace a correctness or accuracy evaluation. Please report top-1 accuracy for the evaluated workloads under both configurations.
minor comments (5)
  1. [Section 3.3.2] The pseudocode of Algorithm 4 uses the expression 'IFM_j −H_j /p + 1' without parentheses; it should be written as (IFM_j − H_j)/p + 1 to avoid ambiguity.
  2. [Section 4.1] The text refers to 'Xilinx Ultrascale+ Vertix-7 VU19P'; the correct spelling is Virtex-7, and the device family should be stated consistently in Tables 3-4.
  3. [Abstract and Section 6] The phrase 'utile stride' appears in the abstract, while the paper otherwise uses 'uniform stride'; please make the terminology consistent.
  4. [Section 4.3, Table 5] The comparison with previous accelerators uses different FPGA devices, frequencies, and resource budgets; the throughput and latency ratios should be accompanied by a caveat that these are not iso-resource or iso-technology comparisons.
  5. [Section 4.3, Figs. 12-14] The figures report results for '10 randomly selected filters' and '10 randomly selected output feature maps,' but no random seed or confidence interval is given; please state whether these selections are representative and add variability information.

Circularity Check

0 steps flagged · score 0.0 of 10

No significant circularity: the fused-layer, tile-stride, and online-arithmetic claims are self-contained; the early-termination safety gap is a correctness risk, not circular reasoning.

full rationale

The paper's central claims—fused-layer tiling, uniform stride selection, online-arithmetic SOP units, and the reported performance/energy numbers—are evaluated against external baselines rather than derived from the claims themselves. Baseline-3 shares the proposed tile stride, isolating the contribution of online arithmetic. Algorithms 3 and 4 select tile strides by an integer-movement and uniformity constraint, not by fitting the reported speedups. The only author self-citation is [54] for the online serial-parallel multiplier, but that component has independent derivations in the cited digital-arithmetic literature [20] and is not the target claim being verified. Algorithm 2's early-termination rule lacks a tail bound, so the 'without accuracy loss' statement is unsupported; however, this is an unproven correctness assumption about radix-2 online arithmetic, not a reduction of the output claim to its own inputs. No fitted parameter is renamed as a prediction, and no uniqueness theorem is imported from the authors' prior work. Therefore the derivation chain is not circular, though the END claim needs additional proof of safety.

Assumptions & free parameters 0 free parameters · 4 assumptions · 0 invented entities

The central results depend on the safety of the early termination rule and on the existence of uniform integer strides for the tested networks. Both are assumed rather than established with external benchmarks or formal proofs. The cycle equations use standard online arithmetic delays from Ercegovac and Lang and the authors' prior multiplier design; no fitted parameters are introduced. No new physical or conceptual entities are proposed.

assumptions (4)
  • ad hoc to paper The early termination condition z+[j] < z-[j] reliably indicates a final negative result in radix-2 signed-digit online arithmetic.
    Algorithm 2 in Section 3.2; no bound on the tail's contribution is given, so the safety of early termination is assumed.
  • ad hoc to paper An integer tile stride exists for every layer such that the movement counts alpha are equal across all fusion pyramid levels.
    Algorithm 4 searches for such strides but provides no existence proof for arbitrary CNN configurations; only the tested networks are shown to have solutions.
  • domain assumption ReLU is the activation function in the fused layers, and negative convolution outputs are discarded.
    Used throughout Section 3.2 and the END mechanism; the paper itself acknowledges in Section 5 that this limits applicability to ReLU-based models.
  • domain assumption Square tiles are used at every pyramid level.
    Stated in Section 3.3.1; this restricts the generality of the tile size and stride calculations.

how reviews work

0 comments
Cite this review

Pith. "Pith review of USEFUSE: Uniform Stride for Enhanced Performance in Fused Layer Architecture of Deep Neural Networks." pith.science (2026). https://pith.science/paper/MSL2YDDW

@misc{pith2026241213724,
  author       = {Pith},
  title        = {Pith review of: USEFUSE: Uniform Stride for Enhanced Performance in Fused Layer Architecture of Deep Neural Networks},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/MSL2YDDW}},
  note         = {Machine review of arXiv:2412.13724}
}
read the original abstract

Convolutional Neural Networks (CNNs) are crucial in various applications, but their deployment on resource-constrained edge devices poses challenges. This study presents the Sum-of-Products (SOP) units for convolution, which utilize low-latency left-to-right bit-serial arithmetic to minimize response time and enhance overall performance. The study proposes a methodology for fusing multiple convolution layers to reduce off-chip memory communication and increase overall performance. An effective mechanism detects and skips inefficient convolutions after ReLU layers, minimizing power consumption without compromising accuracy. Furthermore, efficient tile movement guarantees uniform access to the fusion pyramid. An analysis demonstrates the utile stride strategy improves operational intensity. Two designs cater to varied demands: one focuses on minimal response time for mission-critical applications, and another focuses on resource-constrained devices with comparable latency. This approach notably reduced redundant computations, improving the efficiency of CNN deployment on edge devices.

Figures

Figures reproduced from arXiv: 2412.13724 by the authors.

Figure 1
Figure 1. A general CNN architecture. A generic CNN architecture is illustrated in [PITH_FULL_IMAGE:figures/full_fig_p002_1.png] view at source ↗
Figure 2
Figure 2. Proposed layer fusion accelerator design pipeline [PITH_FULL_IMAGE:figures/full_fig_p007_2.png] view at source ↗
Figure 3
Figure 3. General layer fusion scheme the tile sizes of the respective layers in the fusion pyramid. Consider an example of a simple CNN such as LeNet-5 whose first two convolution layers are to be fused. Each convolution layer is followed by a sub-sampling layer, like Maxpooling. In a fusion of two convolution layers, R = C = 1 output pixels from the second sub-sampling layer serve as input to the third layer. To determine t… view at source ↗
Figures from the paper (11 more)
Figure 4
Figure 4. Figure 4: Overall Architecture. The solid black arrows represent the input, output, and control connections, while the [PITH_FULL_IMAGE:figures/full_fig_p010_4.png]
Figure 5
Figure 5. Figure 5: Tile/Pyramid Level Design [PITH_FULL_IMAGE:figures/full_fig_p011_5.png]
Figure 6
Figure 6. Figure 6: Internal Architecture of the Proposed Pixel Processing Unit with the window processing unit (WPU-S) that [PITH_FULL_IMAGE:figures/full_fig_p011_6.png]
Figure 7
Figure 7. Figure 7: Architecture of the proposed window processing unit (WPU-T) that leverages the temporal computation [PITH_FULL_IMAGE:figures/full_fig_p012_7.png]
Figure 8
Figure 8. Figure 8: Architecture of the window processing unit (WPU-S), for conventional bit-serial design, that performs [PITH_FULL_IMAGE:figures/full_fig_p012_8.png]
Figure 9
Figure 9. Figure 9: Architecture of the window processing unit (WPU-T), for conventional bit-serial design, that performs [PITH_FULL_IMAGE:figures/full_fig_p013_9.png]
Figure 10
Figure 10. Figure 10: Performance vs. operational intensity comparison of the proposed spatial design (DS-1) with the baseline [PITH_FULL_IMAGE:figures/full_fig_p014_10.png]
Figure 11
Figure 11. Figure 11: Performance vs. operational intensity comparison of the proposed spatial (DS-1) and temporal (DS-2) [PITH_FULL_IMAGE:figures/full_fig_p015_11.png]
Figure 12
Figure 12. Figure 12: Percentage of detected negative/ineffective activations for [PITH_FULL_IMAGE:figures/full_fig_p017_12.png]
Figure 13
Figure 13. Figure 13: Energy savings with the proposed early negative detection (END) technique for the first convolution layers [PITH_FULL_IMAGE:figures/full_fig_p018_13.png]
Figure 14
Figure 14. Figure 14: The average effective computation cycles for each fusion pyramid were compared between the Baseline-3 design and the proposed design, with and without the END technique. The results showed that the END technique achieved an average savings of 50.1% in computation cycl…

Discussion (0). Continue with ORCID to comment.

Reference graph

Works this paper leans on

65 extracted references · 57 canonical work pages

  1. [1]

    Automatically designing cnn architectures using the genetic algorithm for image classification

    Yanan Sun, Bing Xue, Mengjie Zhang, Gary G Yen, and Jiancheng Lv. Automatically designing cnn architectures using the genetic algorithm for image classification. IEEE transactions on cybernetics, 50(9):3840–3854, 2020

    work page 2020

  2. [2]

    Fully convolutional networks for semantic segmentation

    Jonathan Long, Evan Shelhamer, and Trevor Darrell. Fully convolutional networks for semantic segmentation. In Proceedings of the IEEE conference on computer vision and pattern recognition, pages 3431–3440, 2015

    2015

  3. [3]

    Efficient b-mode ultrasound image reconstruction from sub-sampled rf data using deep learning

    Yeo Hun Yoon, Shujaat Khan, Jaeyoung Huh, and Jong Chul Ye. Efficient b-mode ultrasound image reconstruction from sub-sampled rf data using deep learning. IEEE transactions on medical imaging, 38(2):325–336, 2018

    work page 2018

  4. [4]

    Afp-src: identification of antifreeze proteins using sparse representation classifier

    Muhammad Usman, Shujaat Khan, Seongyong Park, and Abdul Wahab. Afp-src: identification of antifreeze proteins using sparse representation classifier. Neural Computing and Applications, pages 1–11, 2022

    work page 2022

  5. [5]

    Citisen: A deep learning-based speech signal-processing mobile application

    Yu-Wen Chen, Kuo-Hsuan Hung, You-Jin Li, Alexander Chao-Fu Kang, Ya-Hsin Lai, Kai-Chun Liu, Szu-Wei Fu, Syu-Siang Wang, and Yu Tsao. Citisen: A deep learning-based speech signal-processing mobile application. IEEE Access, 10:46082–46099, 2022

    work page 2022

  6. [6]

    Dnnoff: offloading dnn-based intelligent iot applications in mobile edge computing

    Xing Chen, Ming Li, Hao Zhong, Yun Ma, and Ching-Hsien Hsu. Dnnoff: offloading dnn-based intelligent iot applications in mobile edge computing. IEEE transactions on industrial informatics, 18(4):2820–2829, 2021

    work page 2021

  7. [7]

    Intermittent-aware neural network pruning

    Chih-Chia Lin, Chia-Yin Liu, Chih-Hsuan Yen, Tei-Wei Kuo, and Pi-Cheng Hsiu. Intermittent-aware neural network pruning. In 2023 60th ACM/IEEE Design Automation Conference (DAC), pages 1–6. IEEE, 2023

    work page 2023

  8. [8]

    Non-uniform step size quantization for accurate post-training quantization

    Sangyun Oh, Hyeonuk Sim, Jounghyun Kim, and Jongeun Lee. Non-uniform step size quantization for accurate post-training quantization. In European Conference on Computer Vision, pages 658–673. Springer, 2022

    work page 2022

Show all 65 references
  1. [9]

    Adapt: Fast emulation of approximate dnn accelerators in pytorch.IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2022

    Dimitrios Danopoulos, Georgios Zervakis, Kostas Siozios, Dimitrios Soudris, and Jörg Henkel. Adapt: Fast emulation of approximate dnn accelerators in pytorch.IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2022

    2022

  2. [10]

    A 1.93 tops/w scalable deep learning/inference processor with tetra-parallel mimd architecture for big data applications

    Hoi-Jun Yoo, Seongwook Park, Kyeongryeol Bong, Dongjoo Shin, Jinmook Lee, and Sungpill Choi. A 1.93 tops/w scalable deep learning/inference processor with tetra-parallel mimd architecture for big data applications. In IEEE international solid-state circuits conference, pages 8...

    2015

  3. [11]

    Shidiannao: Shifting vision processing closer to the sensor

    Zidong Du, Robert Fasthuber, Tianshi Chen, Paolo Ienne, Ling Li, Tao Luo, Xiaobing Feng, Yunji Chen, and Olivier Temam. Shidiannao: Shifting vision processing closer to the sensor. In Proceedings of the 42nd Annual International Symposium on Computer Architecture, pages 92–104, 2015

    2015

  4. [12]

    Eyeriss: An energy-efficient reconfigurable accelerator for deep convolutional neural networks

    Yu-Hsin Chen, Tushar Krishna, Joel S Emer, and Vivienne Sze. Eyeriss: An energy-efficient reconfigurable accelerator for deep convolutional neural networks. IEEE journal of solid-state circuits, 52(1):127–138, 2016

    2016

  5. [13]

    Stripes: Bit-serial deep neural network computing

    Patrick Judd, Jorge Albericio, Tayler Hetherington, Tor M Aamodt, and Andreas Moshovos. Stripes: Bit-serial deep neural network computing. In 2016 49th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), pages 1–12. IEEE, 2016

    2016

  6. [14]

    Unpu: An energy-efficient deep neural network accelerator with fully variable weight bit precision

    Jinmook Lee, Changhyeon Kim, Sanghoon Kang, Dongjoo Shin, Sangyeob Kim, and Hoi-Jun Yoo. Unpu: An energy-efficient deep neural network accelerator with fully variable weight bit precision. IEEE Journal of Solid-State Circuits, 54(1):173–185, 2018

    2018

  7. [15]

    Bit fusion: Bit-level dynamically composable architecture for accelerating deep neural network

    Hardik Sharma, Jongse Park, Naveen Suda, Liangzhen Lai, Benson Chau, Vikas Chandra, and Hadi Esmaeilzadeh. Bit fusion: Bit-level dynamically composable architecture for accelerating deep neural network. In 2018 ACM/IEEE 45th Annual International Symposium on Computer Architect...

    2018

  8. [16]

    Compreend: Computation pruning through predictive early negative detection for relu in a deep neural network accelerator

    Namhyung Kim, Hanmin Park, Dongwoo Lee, Sungbum Kang, Jinho Lee, and Kiyoung Choi. Compreend: Computation pruning through predictive early negative detection for relu in a deep neural network accelerator. IEEE Transactions on Computers, 2021

    2021

  9. [17]

    Snapea: Predictive early activation for reducing computation in deep convolutional neural networks

    Vahideh Akhlaghi, Amir Yazdanbakhsh, Kambiz Samadi, Rajesh K Gupta, and Hadi Esmaeilzadeh. Snapea: Predictive early activation for reducing computation in deep convolutional neural networks. In 2018 ACM/IEEE 45th Annual International Symposium on Computer Architecture (ISCA), ...

    2018

  10. [18]

    Compend: Computation pruning through early negative detection for relu in a deep neural network accelerator

    Dongwoo Lee, Sungbum Kang, and Kiyoung Choi. Compend: Computation pruning through early negative detection for relu in a deep neural network accelerator. In Proceedings of the 2018 International Conference on Supercomputing, pages 139–148, 2018

    2018

  11. [19]

    Comprrae: Rram-based convolutional neural network accelerator with r educed computations through ar untime a ctivation e stimation

    Xizi Chen, Jingyang Zhu, Jingbo Jiang, and Chi-Ying Tsui. Comprrae: Rram-based convolutional neural network accelerator with r educed computations through ar untime a ctivation e stimation. In Proceedings of the 24th Asia and South Pacific design automation conference, pages 1...

    2019

  12. [20]

    Digital arithmetic

    Milos D Ercegovac and Tomas Lang. Digital arithmetic. Elsevier, 2004. 21 USEFUSE A PREPRINT

    2004

  13. [21]

    Fused-layer cnn accelerators

    Manoj Alwani, Han Chen, Michael Ferdman, and Peter Milder. Fused-layer cnn accelerators. In 2016 49th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), pages 1–12. IEEE, 2016

    2016

  14. [22]

    Proteus: Exploiting precision variability in deep neural networks

    Patrick Judd, Jorge Albericio, Tayler Hetherington, Tor Aamodt, Natalie Enright Jerger, Raquel Urtasun, and Andreas Moshovos. Proteus: Exploiting precision variability in deep neural networks. Parallel Computing, 73:40–51, 2018

    2018

  15. [23]

    Fixed-point optimization of deep neural networks with adaptive step size retraining

    Sungho Shin, Yoonho Boo, and Wonyong Sung. Fixed-point optimization of deep neural networks with adaptive step size retraining. In 2017 IEEE International conference on acoustics, speech and signal processing (ICASSP), pages 1203–1207. IEEE, 2017

    2017

  16. [24]

    Distilling bit- level sparsity parallelism for general purpose deep learning acceleration

    Hang Lu, Liang Chang, Chenglong Li, Zixuan Zhu, Shengjian Lu, Yanhuan Liu, and Mingzhe Zhang. Distilling bit- level sparsity parallelism for general purpose deep learning acceleration. In MICRO-54: 54th Annual IEEE/ACM International Symposium on Microarchitecture, pages 963–976, 2021

    2021

  17. [25]

    Design of high-throughput mixed-precision cnn acceler- ators on fpga

    Cecilia Latotzke, Tim Ciesielski, and Tobias Gemmeke. Design of high-throughput mixed-precision cnn acceler- ators on fpga. In 2022 32nd International Conference on Field-Programmable Logic and Applications (FPL), pages 358–365. IEEE, 2022

    2022

  18. [26]

    T-dla: An open-source deep learning accelerator for ternarized dnn models on embedded fpga

    Yao Chen, Kai Zhang, Cheng Gong, Cong Hao, Xiaofan Zhang, Tao Li, and Deming Chen. T-dla: An open-source deep learning accelerator for ternarized dnn models on embedded fpga. In 2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pages 13–18. IEEE, 2019

    2019

  19. [27]

    Talipot: Energy-efficient dnn booster employing hybrid bit parallel- serial processing in msb-first fashion

    Mahmut Burak Karadeniz and Mustafa Altun. Talipot: Energy-efficient dnn booster employing hybrid bit parallel- serial processing in msb-first fashion. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 41(8):2714–2727, 2021

    2021

  20. [28]

    A precision-scalable energy-efficient convolutional neural network accelerator

    Wenjian Liu, Jun Lin, and Zhongfeng Wang. A precision-scalable energy-efficient convolutional neural network accelerator. IEEE Transactions on Circuits and Systems I: Regular Papers, 67(10):3484–3497, 2020

    2020

  21. [29]

    Bit-pragmatic deep neural network computing

    Jorge Albericio, Alberto Delmás, Patrick Judd, Sayeh Sharify, Gerard O’Leary, Roman Genov, and Andreas Moshovos. Bit-pragmatic deep neural network computing. In 2017 50th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), pages 382–394, 2017

    2017

  22. [30]

    Towards a reconfigurable bit-serial/bit-parallel vector accelerator using in-situ processing-in-sram

    Khalid Al-Hawaj, Olalekan Afuye, Shady Agwa, Alyssa Apsel, and Christopher Batten. Towards a reconfigurable bit-serial/bit-parallel vector accelerator using in-situ processing-in-sram. In 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pages 1–5. IEEE, 2020

    2020

  23. [31]

    Convfusion: A model for layer fusion in convolutional neural networks

    Luc Waeijen, Savvas Sioutas, Maurice Peemen, Menno Lindwer, and Henk Corporaal. Convfusion: A model for layer fusion in convolutional neural networks. IEEE Access, 9:168245–168267, 2021

    2021

  24. [32]

    Deepthings: Distributed adaptive deep learning inference on resource-constrained iot edge clusters

    Zhuoran Zhao, Kamyar Mirzazad Barijough, and Andreas Gerstlauer. Deepthings: Distributed adaptive deep learning inference on resource-constrained iot edge clusters. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 37(11):2348–2359, 2018

    2018

  25. [33]

    Tgpa: Tile-grained pipeline architecture for low latency cnn inference

    Xuechao Wei, Yun Liang, Xiuhong Li, Cody Hao Yu, Peng Zhang, and Jason Cong. Tgpa: Tile-grained pipeline architecture for low latency cnn inference. In 2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pages 1–8. ACM, 2018

    2018

  26. [34]

    Exploring heterogeneous algorithms for accelerating deep convolutional neural networks on fpgas

    Qingcheng Xiao, Yun Liang, Liqiang Lu, Shengen Yan, and Yu-Wing Tai. Exploring heterogeneous algorithms for accelerating deep convolutional neural networks on fpgas. In Proceedings of the 54th Annual Design Automation Conference 2017, pages 1–6, 2017

    2017

  27. [35]

    Fused-layer-based dnn model parallelism and partial computation offloading

    Mingze Li, Ning Wang, Huan Zhou, Yubin Duan, and Jie Wu. Fused-layer-based dnn model parallelism and partial computation offloading. In GLOBECOM 2022-2022 IEEE Global Communications Conference, pages 5195–5200. IEEE, 2022

    2022

  28. [36]

    Accelerating deep learning inference via model parallelism and partial computation offloading

    Huan Zhou, Mingze Li, Ning Wang, Geyong Min, and Jie Wu. Accelerating deep learning inference via model parallelism and partial computation offloading. IEEE Transactions on Parallel and Distributed Systems, 34(2):475–488, 2022

    2022

  29. [37]

    Olympus: Reaching memory-optimality on dnn processors

    Xuyi Cai, Ying Wang, Kaijie Tu, Chengsi Gao, and Lei Zhang. Olympus: Reaching memory-optimality on dnn processors. IEEE Transactions on Computers, 71(8):1939–1951, 2021

    1939

  30. [38]

    Minimizing off-chip memory access for cnn accelerators

    Saurabh Tewari, Anshul Kumar, and Kolin Paul. Minimizing off-chip memory access for cnn accelerators. IEEE Consumer Electronics Magazine, 11(3):95–104, 2021

    2021

  31. [39]

    Superslash: A unified design space exploration and model compression methodology for design of deep learning accelerators with reduced off-chip memory access volume

    Hazoor Ahmad, Tabasher Arif, Muhammad Abdullah Hanif, Rehan Hafiz, and Muhammad Shafique. Superslash: A unified design space exploration and model compression methodology for design of deep learning accelerators with reduced off-chip memory access volume. IEEE Transactions on ...

    2020

  32. [40]

    Bus width aware off-chip memory access minimization for cnn accelerators

    Saurabh Tewari, Anshul Kumar, and Kolin Paul. Bus width aware off-chip memory access minimization for cnn accelerators. In 2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pages 240–245. IEEE, 2020

    2020

  33. [41]

    Multi-bank on-chip memory management techniques for cnn accelerators

    Duseok Kang, Donghyun Kang, and Soonhoi Ha. Multi-bank on-chip memory management techniques for cnn accelerators. IEEE Transactions on Computers, 71(5):1181–1193, 2021

    2021

  34. [42]

    Practical blind image denoising via swin-conv-unet and data synthesis

    Kai Zhang, Yawei Li, Jingyun Liang, Jiezhang Cao, Yulun Zhang, Hao Tang, Deng-Ping Fan, Radu Timofte, and Luc Van Gool. Practical blind image denoising via swin-conv-unet and data synthesis. Machine Intelligence Research, 20(6):822–836, 2023

    2023

  35. [43]

    An image denoising method based on swin transformer v2 and u-net architecture

    Mingkang Li, Wei Liu, and Weidong Chen. An image denoising method based on swin transformer v2 and u-net architecture. In 2024 IEEE 16th International Conference on Advanced Infocomm Technology (ICAIT), pages 204–209. IEEE, 2024

    2024

  36. [44]

    Plug-and-play image restora- tion with deep denoiser prior.IEEE Transactions on Pattern Analysis and Machine Intelligence, 44(10):6360–6376, 2021

    Kai Zhang, Yawei Li, Wangmeng Zuo, Lei Zhang, Luc Van Gool, and Radu Timofte. Plug-and-play image restora- tion with deep denoiser prior.IEEE Transactions on Pattern Analysis and Machine Intelligence, 44(10):6360–6376, 2021

    2021

  37. [45]

    Artadapter: Text-to-image style transfer using multi-level style encoder and explicit adaptation

    Dar-Yen Chen, Hamish Tennent, and Ching-Wen Hsu. Artadapter: Text-to-image style transfer using multi-level style encoder and explicit adaptation. In Proceedings of the IEEE/CVF Conference on Computer Vision and Pattern Recognition, pages 8619–8628, 2024

    2024

  38. [46]

    Stylitgan: Image-based relighting via latent control

    Anand Bhattad, James Soole, and DA Forsyth. Stylitgan: Image-based relighting via latent control. InProceedings of the IEEE/CVF Conference on Computer Vision and Pattern Recognition, pages 4231–4240, 2024

    2024

  39. [47]

    Sharingan: A transformer architecture for multi-person gaze following

    Samy Tafasca, Anshul Gupta, and Jean-Marc Odobez. Sharingan: A transformer architecture for multi-person gaze following. In Proceedings of the IEEE/CVF Conference on Computer Vision and Pattern Recognition, pages 2008–2017, 2024

    2008

  40. [48]

    A study on relu and softmax in transformer

    Kai Shen, Junliang Guo, Xu Tan, Siliang Tang, Rui Wang, and Jiang Bian. A study on relu and softmax in transformer. arXiv preprint arXiv:2302.06461, 2023

    2023 arXiv

  41. [49]

    Replacing softmax with relu in vision transformers

    Mitchell Wortsman, Jaehoon Lee, Justin Gilmer, and Simon Kornblith. Replacing softmax with relu in vision transformers. arXiv preprint arXiv:2309.08586, 2023

    2023 arXiv

  42. [50]

    Terminetor: Early convolution termination for efficient deep neural networks

    Uday Mallappa, Pranav Gangwar, Behnam Khaleghi, Haichao Yang, and Tajana Rosing. Terminetor: Early convolution termination for efficient deep neural networks. In 2022 IEEE 40th International Conference on Computer Design (ICCD), pages 635–643. IEEE, 2022

    2022

  43. [51]

    Bitset: Bit-serial early termination for computation reduction in convolutional neural networks

    Yunjie Pan, Jiecao Yu, Andrew Lukefahr, Reetuparna Das, and Scott Mahlke. Bitset: Bit-serial early termination for computation reduction in convolutional neural networks. ACM Transactions on Embedded Computing Systems, 22(5s):1–24, 2023

    2023

  44. [52]

    A novel architecture for early detection of negative output features in deep neural network accelerators

    Mohammadreza Asadikouhanjani and Seok-Bum Ko. A novel architecture for early detection of negative output features in deep neural network accelerators. IEEE Transactions on Circuits and Systems II: Express Briefs , 67(12):3332–3336, 2020

    2020

  45. [53]

    Msb-first distributed arithmetic circuit for convolution neural network computation

    Md Kamruzzaman Shuvo, David E Thompson, and Haibo Wang. Msb-first distributed arithmetic circuit for convolution neural network computation. In 2020 IEEE 63rd International Midwest Symposium on Circuits and Systems (MWSCAS), pages 399–402. IEEE, 2020

    2020

  46. [54]

    Ercegovac, and Jeong-A Lee

    Muhammad Usman, Miloš D. Ercegovac, and Jeong-A Lee. Low-latency online multiplier with reduced activities and minimized interconnect for inner product arrays. Journal of Signal Processing Systems, pages 1–20, 2023

    2023

  47. [55]

    Optimizing fpga-based accelerator design for deep convolutional neural networks

    Chen Zhang, Peng Li, Guangyu Sun, Yijin Guan, Bingjun Xiao, and Jason Cong. Optimizing fpga-based accelerator design for deep convolutional neural networks. In Proceedings of the 2015 ACM/SIGDA international symposium on field-programmable gate arrays, pages 161–170, 2015

    2015

  48. [56]

    Gradient-based learning applied to document recognition

    Yann LeCun, Léon Bottou, Yoshua Bengio, and Patrick Haffner. Gradient-based learning applied to document recognition. Proceedings of the IEEE, 86(11):2278–2324, 1998

    1998

  49. [57]

    Imagenet classification with deep convolutional neural networks

    Alex Krizhevsky, Ilya Sutskever, and Geoffrey E Hinton. Imagenet classification with deep convolutional neural networks. Advances in neural information processing systems, 25, 2012

    2012

  50. [58]

    Very deep convolutional networks for large-scale image recognition

    Karen Simonyan and Andrew Zisserman. Very deep convolutional networks for large-scale image recognition. arXiv preprint arXiv:1409.1556, 2014

    2014 arXiv

  51. [59]

    Applying the roofline model

    Georg Ofenbeck, Ruedi Steinmann, Victoria Caparros, Daniele G Spampinato, and Markus Püschel. Applying the roofline model. In 2014 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), pages 76–85. IEEE, 2014. 23 USEFUSE A PREPRINT

    2014

  52. [60]

    Pytorch: An imperative style, high-performance deep learning library

    Adam Paszke, Sam Gross, Francisco Massa, Adam Lerer, James Bradbury, Gregory Chanan, Trevor Killeen, Zeming Lin, Natalia Gimelshein, Luca Antiga, et al. Pytorch: An imperative style, high-performance deep learning library. Advances in neural information processing systems, 32, 2019

    2019

  53. [61]

    Automatic compilation of diverse cnns onto high- performance fpga accelerators

    Yufei Ma, Yu Cao, Sarma Vrudhula, and Jae-sun Seo. Automatic compilation of diverse cnns onto high- performance fpga accelerators. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 39(2):424–437, 2018

    2018

  54. [62]

    Shortcutfusion: From tensorflow to fpga-based accelerator with a reuse-aware memory allocation for shortcut data

    Duy Thanh Nguyen, Hyeonseung Je, Tuan Nghia Nguyen, Soojung Ryu, Kyujoong Lee, and Hyuk-Jae Lee. Shortcutfusion: From tensorflow to fpga-based accelerator with a reuse-aware memory allocation for shortcut data. IEEE Transactions on Circuits and Systems I: Regular Papers, 69(6)...

    2022

  55. [63]

    Accelerating deep convolutional neural networks using number theoretic transform

    Seongmin Hong, Yashael Faith Arthanto, Joo-Young Kim, et al. Accelerating deep convolutional neural networks using number theoretic transform. IEEE Transactions on Circuits and Systems I: Regular Papers, 70(1):315–326, 2022

    2022

  56. [64]

    An efficient and flexible accelerator design for sparse convolutional neural networks

    Xiaoru Xie, Jun Lin, Zhongfeng Wang, and Jinghe Wei. An efficient and flexible accelerator design for sparse convolutional neural networks. IEEE Transactions on Circuits and Systems I: Regular Papers, 68(7):2936–2949, 2021

    2021

  57. [65]

    Multiplication-free lookup-based cnn accelerator using residual vector quantization and its fpga implementation

    Hiroshi Fuketa, Toshihiro Katashita, Yohei Hori, and Masakazu Hioki. Multiplication-free lookup-based cnn accelerator using residual vector quantization and its fpga implementation. IEEE Access, 2024. 24

    2024

Pith tools

Reviewed August 11, 2026 · model on record in the stance chip above.