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Bitnet.cpp: Efficient Edge Inference for Ternary LLMs

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arxiv 2502.11880 v1 pith:YYMU3LDS submitted 2025-02-17 cs.LG cs.AIcs.CLcs.DC

classification cs.LGcs.AIcs.CLcs.DC
keywords bitnetllmsinferenceternaryedgeefficientbaselineslibrary
verification ladder T0 review T1 audit T2 compute T3 formal
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The advent of 1-bit large language models (LLMs), led by BitNet b1.58, has spurred interest in ternary LLMs. Despite this, research and practical applications focusing on efficient edge inference for ternary LLMs remain scarce. To bridge this gap, we introduce Bitnet.cpp, an inference system optimized for BitNet b1.58 and ternary LLMs. Given that mixed-precision matrix multiplication (mpGEMM) constitutes the bulk of inference time in ternary LLMs, Bitnet.cpp incorporates a novel mpGEMM library to facilitate sub-2-bits-per-weight, efficient and lossless inference. The library features two core solutions: Ternary Lookup Table (TL), which addresses spatial inefficiencies of previous bit-wise methods, and Int2 with a Scale (I2_S), which ensures lossless edge inference, both enabling high-speed inference. Our experiments show that Bitnet.cpp achieves up to a 6.25x increase in speed over full-precision baselines and up to 2.32x over low-bit baselines, setting new benchmarks in the field. Additionally, we expand TL to element-wise lookup table (ELUT) for low-bit LLMs in the appendix, presenting both theoretical and empirical evidence of its considerable potential. Bitnet.cpp is publicly available at https://github.com/microsoft/BitNet/tree/paper , offering a sophisticated solution for the efficient and practical deployment of edge LLMs.

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Cited by 4 Pith papers

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  1. Vec-LUT: Vector Table Lookup for Parallel Ultra-Low-Bit LLM Inference on Edge Devices

    cs.DC 2025-12 conditional novelty 7.0 of 10

    Vec-LUT delivers up to 4.2x speedup over prior LUT methods for parallel ultra-low-bit LLM inference on edge devices by unifying lookups across tokens and adding cache-aware tensor layouts.

  2. PolyQ: Codesigning End-to-End Quantization Framework for Scalable Edge CPU LLM Inference

    cs.LG 2026-07 conditional novelty 6.0 of 10

    PolyQ makes fractional-bit CPU LLM inference practical via per-channel bit allocation from {2,3,4,8,16} and compile-time channel-order merging.

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    BitRL enables on-device RL agents via 1-bit quantized language models, delivering 10-16x memory reduction and 3-5x energy efficiency gains with 85-98% retained performance.

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