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A Survey of Circuit Foundation Model: Foundation AI Models for VLSI Circuit Design and EDA

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arxiv 2504.03711 v3 pith:BCH3VNZM submitted 2025-03-28 cs.AR cs.LG

classification cs.ARcs.LG
keywords circuitmodelsfoundationdesignworksapplicationsdatamodel
verification ladder T0 review T1 audit T2 compute T3 formal
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Artificial intelligence (AI)-driven electronic design automation (EDA) techniques have been extensively explored for VLSI circuit design applications. Most recently, foundation AI models for circuits have emerged as a new technology trend. Unlike traditional task-specific AI solutions, these new AI models are developed through two stages: 1) self-supervised pre-training on a large amount of unlabeled data to learn intrinsic circuit properties; and 2) efficient fine-tuning for specific downstream applications, such as early-stage design quality evaluation, circuit-related context generation, and functional verification. This new paradigm brings many advantages: model generalization, less reliance on labeled circuit data, efficient adaptation to new tasks, and unprecedented generative capability. In this paper, we propose referring to AI models developed with this new paradigm as circuit foundation models (CFMs). This paper provides a comprehensive survey of the latest progress in circuit foundation models, unprecedentedly covering over 130 relevant works. Over 90% of our introduced works were published in or after 2022, indicating that this emerging research trend has attracted wide attention in a short period. In this survey, we propose to categorize all existing circuit foundation models into two primary types: 1) encoder-based methods performing general circuit representation learning for predictive tasks; and 2) decoder-based methods leveraging large language models (LLMs) for generative tasks. For our introduced works, we cover their input modalities, model architecture, pre-training strategies, domain adaptation techniques, and downstream design applications. In addition, this paper discussed the unique properties of circuits from the data perspective. These circuit properties have motivated many works in this domain and differentiated them from general AI techniques.

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Cited by 5 Pith papers

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    A multi-agent LLM framework that iteratively co-designs CGRA hardware and software parameters, reporting power and performance improvements over LLM and manual baselines.

  2. SynCircuit: Automated Generation of New Synthetic RTL Circuits Can Enable Big Data in Circuits

    cs.LG 2025-08 conditional novelty 6.0 of 10

    SynCircuit generates new, structurally valid RTL circuits with a directed-cyclic-graph diffusion model plus post-processing and MCTS, and shows they improve ML-based PPA prediction when added to training data.

  3. Discovering heuristics in a complex SAT solver with large language models

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    LLM-guided evolutionary search over seven modularized SAT solver heuristics yields solvers that beat tuned Kissat and CaDiCaL on most of eleven test families.

  4. VeriOpt: PPA-Aware High-Quality Verilog Generation via Multi-Role LLMs

    cs.SE 2025-07 conditional novelty 5.0 of 10

    A multi-role LLM prompting framework with PPA-aware in-context learning reports 25/29 functional correctness on RTLLM and up to 88% power, 76% area, and 73% timing gains over its own baseline.

  5. FuncGNN: Learning Functional Semantics of Logic Circuits with Graph Neural Networks

    cs.LG 2025-06 conditional novelty 5.0 of 10

    FuncGNN, a GNN with hybrid aggregation, ratio-conditioned normalization, and dense layer fusion, reports state-of-the-art MAE on signal probability and truth-table distance prediction for AIG circuits.

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