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REVIEW 5 major objections 6 minor 1 cited by

Coordinated Reinforcement Learning Prefetching Architecture for Multicore Systems

T0 review · 5 major / 6 minor · reviewed 2026-08-04 · deepseek-v4-flash

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Pith's one-line read Shared Q-table lifts multicore prefetch performance by 12 percent

desk verdict Real architectural idea, but the evaluation contradicts itself and the 12% IPC claim does not survive contact with the paper's own §7.2. read the letter →

arxiv 2509.10719 v1 pith:ILG2CL2X submitted 2025-09-12 cs.DC cs.ARcs.LGcs.PF

Mohammed Humaid Siddiqui , Fernando Guzman , Yufei Wu , Ruishu Ann This is my paper · ORCID
classification cs.DCcs.ARcs.LGcs.PF
keywords hardwareprefetchingreinforcementlearningmulticoreprocessorsQ-learningsharedmemorybandwidthprefetchcoordinationPythia
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

This paper tries to establish that the performance loss suffered by state-of-the-art reinforcement-learning prefetchers when moving from one core to several is avoidable if the cores stop learning in isolation. It proposes CRL-Pythia, a multicore prefetcher in which all cores share a single Q-value table and evaluation queue, updated through atomic operations, plus a global state table that records system-wide access patterns. The paper argues this coordination cuts duplicate prefetch requests, accelerates learning convergence, and produces roughly 12% higher IPC than per-core Pythia under bandwidth-constrained workloads, at moderate hardware cost. If true, this is a practical path to making existing RL prefetchers scale to modern multicore systems without new memory technology.

What carries the argument

The load-bearing object is the Shared Learning Repository (SLR), which centralizes the Q-Value Store (QVStore) and Evaluation Queue (EQ) that original Pythia kept per core. The QVStore holds Q-values for state-action pairs observed anywhere in the system; the EQ holds a FIFO list of recently issued prefetch actions with a filled bit that gates rewards. Around these sit the Global State Table (GST), which records program counters, accessed addresses, core IDs, and timestamps to expose cross-core temporal and spatial patterns, and lightweight atomic synchronization so multiple cores can update shared structures safely. The learning rule remains Pythia's SARSA update with epsilon-greedy explora

What would settle it

Run the same four-core simulation with CRL-Pythia's shared Q-table replaced by private per-core Q-tables plus a simple hardware duplicate-request filter. If the private-table version matches or beats CRL-Pythia's IPC under bandwidth-constrained workloads, then the shared learning table—not duplicate elimination—is not the source of the 12% gain, and the paper's central claim fails.

Watch

Extended reading notes

Core claim

On the paper's own terms, CRL-Pythia shows that treating a multicore system as one collective reinforcement-learning agent beats treating each core as an independent agent. Instead of each core maintaining its own QVStore and Evaluation Queue, all cores read and write a shared repository; rewards from any core's prefetch outcomes update the same Q-values, so a pattern learned by one core immediately benefits the others. The paper reports that this shared-learning design outperforms standalone Pythia in every evaluated configuration, with about a 12% IPC gain specifically when memory bandwidth is tight, and with moderate hardware overhead (roughly 28 KB in the simulation configuration). It al

Load-bearing premise

The whole benefit rests on the assumption that one shared Q-table updated by all cores yields better decisions than separate per-core tables—if the mixing of different cores' patterns biases the policy (as the paper's own analysis says it can), the claimed IPC gain would not materialize.

Editorial extensions

If this is right

  • If the central claim holds, hardware designers can get a meaningful multicore prefetching gain without changing memory technology, just by sharing the RL state across cores.
  • Bandwidth-constrained workloads, common in server and data-center settings, stand to gain roughly 12% IPC, which is a large effect for a prefetcher change.
  • The 15-20% duplicate prefetch traffic in uncoordinated multicore systems should mostly disappear, freeing memory bus bandwidth for useful demand traffic.
  • Cross-core learning convergence should accelerate: a pattern discovered on one core propagates to all cores immediately, shortening the learning ramp for new access patterns.
  • The design opens a path for other RL-based memory-system agents, such as cache replacement or memory scheduling, to adopt coordinated shared-learning architectures.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • Editorial inference: The same shared-table idea that creates the gain also creates the risk the paper itself names—mixing conflicting per-core patterns into 'ghost' Q-values and non-stationary learning. A natural follow-up experiment is to compare the shared table against a per-core-table design with a lightweight duplicate filter; if the filter alone recovers most of the 12% gain, the benefit com
  • Editorial inference: The paper leaves implicit that coordination overhead grows with core count; the sensitivity analysis shows bandwidth use rising with cores, so a testable extension is to make the sharing topology adaptive (e.g., cluster cores by sharing patterns) to avoid Q-table thrashing at manycore scales.
  • Editorial inference: Because the reported results are from a trace-based simulator with limited benchmarks and a single channel of DRAM, the 12% figure should be understood as a proof-of-concept number; a hardware prototype or full-system simulation with more diverse workloads would sharpen the claim.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

5 major / 6 minor

Summary. The paper proposes CRL-Pythia, a multicore hardware prefetcher that extends the Pythia reinforcement-learning prefetcher by replacing per-core QVStore and Evaluation Queue structures with a shared learning repository (SLR) and a global state table (GST). The authors claim that this coordinated, cross-core design reduces redundant prefetch requests, improves learning convergence, and yields about 12% IPC improvement over Pythia under bandwidth-constrained workloads, at moderate hardware overhead. Evaluation is performed in ChampSim on single- and four-core configurations using CloudSuite and SPEC 2017 traces. The paper also reports sensitivity analyses for SLR size, core count, and bandwidth limits.

Significance. If the central claim were established, a coordinated RL-based prefetching architecture that shares Q-values across cores would be a useful contribution to multicore memory-system design, particularly for bandwidth-constrained workloads. The paper also correctly identifies a real problem: per-core prefetchers can generate redundant and interfering prefetch traffic. However, the evidence presented is internally contradictory and not statistically or methodologically adequate. The paper's own Section 7.2 describes failure modes that directly contradict the abstract's universal improvement claim, the hardware-overhead numbers are inconsistent, and the simulation runs are far too short to support convergence claims. The contribution is therefore currently unsupported. No code or artifact is supplied, and no external validation of the Pythia reimplementation is reported.

major comments (5)
  1. [§7.2 and Table 11] The results are self-contradictory. Section 7.2 states that CRL-Pythia 'generates 200%, 100%, and 40% higher overpredictions' than SPP, Bingo, and Pythia, respectively. Table 11 reports the opposite: CRL-4 has lower overprediction than Pythia in every listed benchmark (e.g., 60 vs 100 for 482.sphinx3; 30 vs 70 for Ligra-PageRankDelta). Since the abstract's central claim is that CRL-Pythia reduces wasted bandwidth and 'outperforms single Pythia configurations in all cases,' these two statements cannot both be true. The authors must report the actual measured overprediction numbers and explain which comparison is correct; as written, a reader cannot determine whether the shared table helps or hurts.
  2. [§5 vs §7.2] The proposed mechanism is undermined by the paper's own analysis. Section 5 says that with the shared QVStore 'the multiple cores collectively act as one learning agent' and that this improves system-wide performance. Section 7.2 then admits that 'All cores write to the same Q-table,' 'the learned Q-values now mix conflicting behaviors,' 'There could be Ghost patterns,' and 'even if one core mispredicts, its feedback can bias the shared policy,' and that 'exploration×nºCores can lead to exponential noise.' These are exactly the failure modes that would produce overprediction, not the bandwidth savings promised in the abstract. The paper needs either a formal/conceptual argument for why the shared table converges despite the non-stationarity, or a direct empirical comparison against per-core Q-tables showing a net benefit. Neither is provided.
  3. [§5, Tables 2, 8, 9] The hardware-overhead numbers are inconsistent. Section 5 and Table 2 report QVStore 192 Kb plus EQ 13 Kb, totaling 205 KB (or Kb — the units are ambiguous), and call this the storage overhead of CRL-Pythia. Table 8 lists CRL-Pythia's overhead as 28 KB, while Table 9 lists it as 25.5 KB. The abstract claims 'moderate hardware overhead.' A factor-of-eight discrepancy (205 KB vs 25.5 KB, depending on units) is load-bearing for that claim. The authors must state one consistent configuration, clarify whether values are bits or bytes, and justify whether bit-packing and entry-count assumptions match the evaluated simulator configuration.
  4. [§6.4] The simulation is too short to support the claims. The paper uses 1M warmup + 1M simulation per core, so a four-core run covers only about 4M simulated instructions. RL-based prefetching is an online learning process, and the paper explicitly claims 'learning convergence across cores.' Standard ChampSim evaluation for prefetching uses hundreds of millions or billions of instructions with multiple SimPoints; 1M instructions cannot produce stable IPC, coverage, or overprediction measurements, and no confidence intervals or variance across runs are reported. All performance conclusions are therefore statistically unsupported.
  5. [§6.1] The baseline Pythia implementation is not validated. The authors say the simulator is 'extended from the publicly available Pythia prefetcher framework,' but they do not reproduce any published Pythia result or compare their reimplementation against the original paper's numbers. Without such validation, the claimed 10% scaling loss of Pythia, the 15–20% duplicate-prefetch measurement, and all relative gains could be artifacts of the authors' modifications rather than properties of the real Pythia design. The paper should provide an artifact, a validation run against known baselines, or at least a clear description of how the reimplementation was checked.
minor comments (6)
  1. [Throughout] The naming is inconsistent: 'CRL-Pythia,' 'Pythia CRL,' and 'Pythia CRL' are used interchangeably. Please standardize.
  2. [§2, Table 1] The long dog-training RL example and the GPU specification table are unrelated to the prefetching contribution and should be removed or drastically shortened.
  3. [Figures] Several figures are referenced by vague descriptions ('Figure above,' 'This figure illustrates') without figure numbers, and some appear to be missing from the text. Please number all figures and refer to them explicitly.
  4. [§7.1 vs Tables 10–12] The benchmark list in Section 7.1 (CloudSuite cassandra/nutch/cloud9/streaming; SPEC 605.mcf/620.omnetpp/649.fotonik) does not match the benchmarks in Tables 10–12 (482.sphinx3, PARSEC-Canneal, PARSEC-Facesim, 459.GemsFDTD, Ligra-CC, Ligra-PageRankDelta). Clarify which benchmarks were actually evaluated and ensure tables are labeled correctly.
  5. [References] Reference [4] is a Pythia LLM suite, not the Pythia prefetcher, and is used as if it were the hardware Pythia paper. Reference [35] is described as a Bingo paper but the citation details differ from [2]. Please correct the bibliography.
  6. [§5] There is a typo: 'prefetched of each core' should be 'prefetcher of each core.' Also, the sentence 'A filled bit. A set filled bit indicates...' is awkward and should be rewritten.

Circularity Check

0 steps flagged · score 0.0 of 10

No circular derivation: the paper reports simulation measurements, not predictions derived from the claims.

full rationale

The paper contains no formal derivation or first-principles prediction that could reduce to its inputs. CRL-Pythia is an architectural modification of the externally published Pythia framework [3], implemented in ChampSim and evaluated by simulation; the claimed IPC gains are measured outcomes, not consequences of a definition. The SLR/GST design is not defined in terms of the IPC improvement, and no parameter is fitted to the benchmark results and then renamed a prediction. The paper inherits Pythia's RL algorithm by citation to independent external work [3], and the comparison baseline is that same external implementation. There are no load-bearing self-citations or imported uniqueness theorems. Section 7.2 does contain a serious internal inconsistency: after reporting that CRL-Pythia generates 200%, 100%, and 40% higher overpredictions than SPP, Bingo, and Pythia, it later presents Table 11 as showing overprediction reduction. This is a threat to the paper's conclusion and should be weighed as a correctness/validity concern, but it is not circularity: the contradictory measurements are not equivalence-by-construction, fitted-parameter renaming, or a self-citation chain. The reliance on the authors' own reimplementation is a reproducibility concern, not a circular one. No circular step can be exhibited with Eq. X = Eq. Y or a fitted parameter renamed as prediction.

Assumptions & free parameters 5 free parameters · 4 assumptions · 2 invented entities

The central claim rests on the assumption that a shared Q-table and a system-wide state table improve multicore prefetching. The RL hyperparameters are unstated free parameters, and the two invented hardware structures have no independent evidence beyond the simulation in this paper.

free parameters (5)
  • RL learning rate alpha
    Not reported; used in the SARSA update in Algorithm 2, but no value is given.
  • RL discount factor gamma
    Not reported; used in Algorithm 2, no value given.
  • Exploration rate epsilon = about 10% (implied in Section 7.2)
    Mentioned only as '10% random actions' in the overprediction discussion; no systematic tuning reported.
  • QVStore entry count = 16384 entries
    Chosen in Section 5; affects capacity and convergence; sensitivity only on SLR size, not on this count.
  • Q-value width = 16 bits
    Chosen in Section 5; affects precision and storage; not varied in experiments.
assumptions (4)
  • domain assumption ChampSim with the stated configuration (1M warmup + 1M simulated instructions per core) faithfully represents multicore processor behavior.
    Introduced in Section 6.4; without this, the IPC numbers are uninterpretable.
  • domain assumption The selected CloudSuite and SPEC 2017 traces are representative of the claimed 'contemporary multicore workloads'.
    Benchmarks chosen in Section 7.1; no justification that they generalize.
  • ad hoc to paper SARSA Q-learning converges and is stable when a single Q-table is updated by multiple cores with atomic operations.
    The paper's own Section 7.2 notes non-stationarity and 'ghost' patterns, weakening this premise.
  • domain assumption The reimplementation of Pythia in the simulator is faithful to the MICRO 2021 Pythia paper.
    Used implicitly as the baseline in Section 6.1; no verification is provided.
invented entities (2)
  • Shared Learning Repository (SLR)
    purpose: Central table where all cores read and write Q-values to share learned behavior.
    Only simulated; no silicon or independent measurement exists. Its benefit is the paper's central claim.
  • Global State Table (GST)
    purpose: Records system-wide PC, addresses, core IDs, and timestamps to detect cross-core patterns.
    Described in Sections 3.3 and 5; no separate evaluation or quantitative results attributed to it.

how reviews work

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Cite this review

Pith. "Pith review of Coordinated Reinforcement Learning Prefetching Architecture for Multicore Systems." pith.science (2026). https://pith.science/paper/ILG2CL2X

@misc{pith2026250910719,
  author       = {Pith},
  title        = {Pith review of: Coordinated Reinforcement Learning Prefetching Architecture for Multicore Systems},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/ILG2CL2X}},
  note         = {Machine review of arXiv:2509.10719}
}
read the original abstract

Hardware prefetching is critical to fill the performance gap between CPU speeds and slower memory accesses. With multicore architectures becoming commonplace, traditional prefetchers are severely challenged. Independent core operation creates significant redundancy (up to 20% of prefetch requests are duplicates), causing unnecessary memory bus traffic and wasted bandwidth. Furthermore, cutting-edge prefetchers such as Pythia suffer from about a 10% performance loss when scaling from a single-core to a four-core system. To solve these problems, we propose CRL-Pythia, a coordinated reinforcement learning based prefetcher specifically designed for multicore systems. In this work, CRL-Pythia addresses these issues by enabling cross-core sharing of information and cooperative prefetching decisions, which greatly reduces redundant prefetch requests and improves learning convergence across cores. Our experiments demonstrate that CRL-Pythia outperforms single Pythia configurations in all cases, with approximately 12% IPC (instructions per cycle) improvement for bandwidth-constrained workloads, while imposing moderate hardware overhead. Our sensitivity analyses also verify its robustness and scalability, thereby making CRL-Pythia a practical and efficient solution to contemporary multicore systems.

Discussion (0). Continue with ORCID to comment.

Forward citations

Cited by 1 Pith paper

Reviewed papers in the Pith corpus that reference this work. Sorted by Pith novelty score. Full citation record

  1. ArchAgent v2: A Case Study with the Data Prefetching Championship

    cs.AI 2026-08 conditional novelty 6.0 of 10

    An LLM-based evolutionary framework automatically discovered a multi-level prefetcher that beats the prior hand-designed DPC4 champion on held-out traces.

Reference graph

Works this paper leans on

41 extracted references · 3 canonical work pages · cited by 1 Pith paper

  1. [4]

    Stella Biderman, Hailey Schoelkopf, Quentin Anthony, Herbie Bradley, Kyle O’Brien, Eric Hallahan, Mohammad Aflah Khan, Shivanshu Purohit, USVSN Sai Prashanth, Edward Raff, Aviya Skowron, Lintang Sutawika, and Oskar van der Wal. 2023. Pythia: A Suite for Analyzing Large Language Models Across Training and Scaling. arXiv:2304.01373 [cs.CL] https://arxiv.org...

    arXiv 2023

  2. [2]

    Mohammad Bakhshalipour, Mehran Shakerinava, Pejman Lotfi-Kamran, and Hamid Sarbazi-Azad. 2019. Bingo Spatial Data Prefetcher. In2019 IEEE Interna- tional Symposium on High Performance Computer Architecture (HPCA). 399–411. https://doi.org/10.1109/HPCA.2019.00053

    arXiv 2019

  3. [35]

    Mayank Sachan, Sagar Garg, and Rajeev Balasubramonian. 2019. Bingo: A Semantic Prefetcher for Convolutional Neural Networks. InProceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO). 1–13. https://doi.org/10.1145/3352460.3358271

    arXiv 2019

  4. [1]

    Amazon Web Services, Inc. 2024. Amazon Elastic Block Store (EBS). https: //aws.amazon.com/ebs/. Accessed: 2025-04-19

    2024

  5. [3]

    Nori, Taha Shahroodi, Sreeni- vas Subramoney, and Onur Mutlu

    Rahul Bera, Konstantinos Kanellopoulos, Anant V. Nori, Taha Shahroodi, Sreeni- vas Subramoney, and Onur Mutlu. 2021. Pythia: A Customizable Hardware Prefetching Framework Using Online Reinforcement Learning. InProceedings of the 54th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO). 1121–1137. https://doi.org/10.1145/3466752.3480101

    arXiv 2021

  6. [5]

    ChampSim Contributors. 2019. ChampSim: A Trace-Based Simulator for Research in Memory Systems. https://github.com/ChampSim/ChampSim. Accessed: 2025- 04-19

    2019

  7. [6]

    Tien-Fu Chen and Jean-Loup Baer. 2007. Reducing memory latency via non- blocking and prefetching caches.IEEE Trans. Comput.(2007)

    2007

  8. [7]

    Chia-Hsiu Chou, Ming-Chang Shieh, and Yu-Ching Wang. 2020. Coordinated Cache Management for Multi-Core Systems.IEEE Trans. Comput.69, 4 (2020), 530–544

    2020

Show all 41 references
  1. [8]

    Tien Anh Dang, Van Hieu Pham, and Jangwoo Kim. 2021. Memory System Challenges for Machine Learning and Big Data Workloads.Comput. Surveys54, 5 (2021), 1–35. https://doi.org/10.1145/3451234

    2021 doi

  2. [9]

    diagrams.net. 2024. diagrams.net (formerly draw.io). https://www.diagrams.net/. Accessed: 2025-04-18

    2024

  3. [10]

    Michael Ferdman, Almutaz Adileh, Onur Kocberber, Stavros Volos, Mohammad Alisafaee, Djordje Jevdjic, Cyril Kaynak, Adrian Daniel Popescu, Anastasia Aila- maki, and Babak Falsafi. 2012. Clearing the Clouds: A Study of Emerging Scale- Out Workloads on Modern Hardware. InProceedi...

    2012

  4. [11]

    Free Software Foundation. 2023. GCC, the GNU Compiler Collection - G++. https://gcc.gnu.org/. Accessed: 2025-04-19

    2023

  5. [12]

    GCC Manual. 2022. Optimization Options -fprefetch-loop-arrays. https://gcc. gnu.org/onlinedocs/gcc/Optimize-Options.html

    2022

  6. [13]

    Mohammad Hashemi, Kevin Swersky, and Babak Falsafi. 2018. Learning Memory Access Patterns. InProceedings of the 35th International Conference on Machine Learning (ICML)

    2018

  7. [14]

    Hennessy and David A

    John L. Hennessy and David A. Patterson. 2011.Computer Architecture: A Quan- titative Approach. Morgan Kaufmann

    2011

  8. [15]

    Hennessy and David A

    John L. Hennessy and David A. Patterson. 2017.Computer Architecture: A Quan- titative Approach(6th ed.). Morgan Kaufmann

    2017

  9. [16]

    John D. Hunter. 2007. Matplotlib: A 2D Graphics Environment. , 90–95 pages. https://doi.org/10.1109/MCSE.2007.55 https://matplotlib.org/

    2007 doi

  10. [17]

    Hunter, J. D. and Matplotlib Development Team. 2024. Matplotlib: Visualization with Python. https://matplotlib.org. Accessed: 2025-04-19

    2024

  11. [18]

    Intel Corporation. 2023. Intel Xeon Platinum 8124M Processor Specifications. https://ark.intel.com/content/www/us/en/ark/products/192447. Accessed: 2025- 04-19

    2023

  12. [19]

    Martínez, and Rich Caruana

    Engin Ipek, Onur Mutlu, José F. Martínez, and Rich Caruana. 2008. Self- Optimizing Memory Controllers: A Reinforcement Learning Approach. InPro- ceedings of the 35th Annual International Symposium on Computer Architecture (ISCA)

    2008

  13. [20]

    Ng, and David T

    Bruce Jacob, Spencer W. Ng, and David T. Wang. 2007.Memory Systems: Cache, DRAM, Disk. Morgan Kaufmann

    2007

  14. [21]

    Ng, and David T

    Bruce Jacob, Spencer W. Ng, and David T. Wang. 2010.Memory Systems: Cache, DRAM, Disk. Morgan Kaufmann

    2010

  15. [22]

    Rakesh Jain and Chia-Lin Lin. 2016. Back to the Future: Leveraging Belady’s Algorithm for Improved Cache Replacement.ACM Transactions on Architecture and Code Optimization (TACO)12, 4 (2016), 1–23. https://doi.org/10.1145/2841220

    2016 doi

  16. [23]

    Qureshi, Steven C

    Aamer Jaleel, Moinuddin K. Qureshi, Steven C. Steely Jr., and Joel Emer. 2010. High Performance Cache Replacement Using Re-reference Interval Prediction (RRIP). InProceedings of the 37th Annual International Symposium on Computer Architecture (ISCA)

    2010

  17. [24]

    Xiaoming Jiang, Anshuman Agrawal, Yixin Zhu, and Thomas F. Wenisch. 2020. RLHint: Leveraging Reinforcement Learning for Heterogeneous Prefetching. In Proceedings of the 53rd IEEE/ACM International Symposium on Microarchitecture (MICRO). https://doi.org/10.1109/MICRO50266.2020.00039

    2020

  18. [25]

    Kitware, Inc. 2023. CMake Build System. https://cmake.org. Accessed: 2025-04-19

    2023

  19. [26]

    Anshuman Kumar, Dhia Alshammari, Abhishek Arunkumar, and Mattan Erez

  20. [27]

    Linux Kernel Community. 2024. Kernel-based Virtual Machine (KVM) Documen- tation. https://www.linux-kvm.org/page/Main_Page. Accessed: 2025-04-19

    2024

  21. [28]

    Yifan Liu, Jie Zhang, and Daniel Hsu. 2021. Ensemble Learning for Prefetch- ing: Balancing Exploration and Exploitation in Shared Memory Systems. In Proceedings of the IEEE International Symposium on High Performance Computer Architecture (HPCA)

    2021

  22. [29]

    Onur Mutlu and Thomas Moscibroda. 2007. Stall-Time Fair Memory Access Scheduling for Chip Multiprocessors. InProceedings of the 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)

    2007

  23. [30]

    Onur Mutlu and Lavanya Subramanian. 2014. Research Problems and Opportu- nities in Memory Systems.Supercomputing Frontiers and Innovations1, 3 (2014), 19–55. https://doi.org/10.14529/jsfi140302

    2014 doi

  24. [31]

    Nesbit and James E

    Karthikeyan J. Nesbit and James E. Smith. 2004. Data Cache Prefetching Using a Global History Buffer. InProceedings of the 10th International Symposium on High Performance Computer Architecture (HPCA). 96–105

    2004

  25. [32]

    pandas development team. 2024. Pandas: Python Data Analysis Library. https: //pandas.pydata.org. Accessed: 2025-04-19

    2024

  26. [33]

    Patterson and John L

    David A. Patterson and John L. Hennessy. 2013.Computer Organization and Design(5th ed.). Morgan Kaufmann

    2013

  27. [34]

    Perl Foundation. 2023. Perl 5.24 Documentation. https://perldoc.perl.org/5.24.1. Accessed: 2025-04-19

    2023

  28. [36]

    Srilatha Srinath, Bradley Moyer, and Josep Torrellas. 2007. Feedback Directed Prefetching: Improving the Performance and Bandwidth-Efficiency of Hardware Prefetchers. InProceedings of the 13th International Symposium on High Perfor- mance Computer Architecture (HPCA)

    2007

  29. [37]

    Standard Performance Evaluation Corporation. 2017. SPEC CPU 2017 Benchmark Suite. https://www.spec.org/cpu2017/. Accessed: 2025-04-18

    2017

  30. [38]

    Sutton and Andrew G

    Richard S. Sutton and Andrew G. Barto. 2018.Reinforcement Learning: An Intro- duction. MIT Press

    2018

  31. [39]

    Zixuan Wang, Mengying Xu, Youfeng Wang, Zhen Guo, and Yanyan Zhang. 2019. Reinforcement Learning for Runtime Hardware Prefetching. InProceedings of the 26th ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS)

    2019

  32. [40]

    Wenisch, Babak Falsafi, and Steven K

    Thomas F. Wenisch, Babak Falsafi, and Steven K. Reinhardt. 2009. Temporal Streaming of Shared Memory. InProceedings of the 36th Annual International Symposium on Computer Architecture (ISCA)

    2009

  33. [2021]

    InProceedings of the 48th International Symposium on Computer Architecture (ISCA)

    Morpheus: Memory Access Prefetching with Contextual Multi-Armed Ban- dits. InProceedings of the 48th International Symposium on Computer Architecture (ISCA). https://doi.org/10.1145/3458817.3476227

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Reviewed August 4, 2026 · model on record in the stance chip above.