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arxiv: 2511.17265 · v2 · submitted 2025-11-21 · 💻 cs.AR · cs.AI· cs.ET· cs.PF

DISCA: A Digital In-memory Stochastic Computing Architecture Using A Compressed Bent-Pyramid Format

Shady Agwa , Yikang Shen , Shiwei Wang , Themis Prodromakis This is my paper

Pith reviewed 2026-05-17 20:20 UTC · model grok-4.3

classification 💻 cs.AR cs.AIcs.ETcs.PF
keywords digital in-memory computingstochastic computingBent-Pyramid formatenergy efficiencymatrix multiplicationAI hardwareCMOS technologyedge computing
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The pith

DISCA achieves 3.59 TOPS/W per bit in digital in-memory stochastic computing for matrix multiplications using a compressed Bent-Pyramid format.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper introduces DISCA, a digital in-memory stochastic computing architecture built around a compressed version of the Bent-Pyramid data format. It seeks to deliver the simple arithmetic of analog in-memory designs while retaining the scalability, reliability, and ease of use that digital circuits provide. This matters for edge AI applications such as robotics and unmanned vehicles, where large matrix multiplications must fit inside tight power and area limits. The work reports post-layout results showing 3.59 TOPS/W per bit at 500 MHz in 180 nm CMOS and claims this yields orders-of-magnitude energy-efficiency gains over existing architectures when scaled to the same workloads.

Core claim

DISCA is a digital in-memory stochastic computing architecture that utilizes a compressed version of the quasi-stochastic Bent-Pyramid data format. This approach inherits the computational simplicity of analog computing while preserving the scalability, productivity, and reliability of digital systems. Post-layout modeling results of DISCA show an energy efficiency of 3.59 TOPS/W per bit at 500 MHz using a commercial 180 nm CMOS technology, leading to significant improvements in energy efficiency for matrix multiplication workloads by orders of magnitude if scaled and compared to counterpart architectures.

What carries the argument

The compressed Bent-Pyramid format, which supplies a quasi-stochastic data representation that simplifies arithmetic operations inside a fully digital in-memory array.

If this is right

  • Matrix multiplication for AI models can be executed at far lower energy cost than in conventional digital or analog in-memory designs.
  • Edge devices such as robots and surveillance UAVs can support larger models within existing power budgets.
  • Digital implementations can capture analog-like computational simplicity without the usual reliability penalties.
  • Standard commercial CMOS processes can be used to build scalable versions of the architecture.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • If the modeled accuracy holds on silicon, the architecture could be combined with existing digital accelerators to reduce overall system power in autonomous systems.
  • Real chip measurements would also reveal whether the compressed format needs extra error-correction circuitry for safety-critical applications.
  • The same format might extend to other linear-algebra kernels beyond matrix multiplication if the stochastic representation remains stable.

Load-bearing premise

Post-layout modeling in 180 nm CMOS accurately predicts the energy efficiency and numerical accuracy that a fabricated chip would achieve on real AI inference tasks.

What would settle it

Fabricate a DISCA test chip in 180 nm CMOS, run matrix-multiplication workloads from actual AI models, and measure the realized energy efficiency together with end-to-end inference accuracy.

Figures

Figures reproduced from arXiv: 2511.17265 by Shady Agwa, Shiwei Wang, Themis Prodromakis, Yikang Shen.

Figure 1
Figure 1. Figure 1: A compressed 8-bit Version of Bent-Pyramid datasets, achieving the [PITH_FULL_IMAGE:figures/full_fig_p002_1.png] view at source ↗
Figure 2
Figure 2. Figure 2: In-memory computing for matrix-matrix multiplication: (a) an example of matrix-matrix multiplication workload including the micro-algorithm, where [PITH_FULL_IMAGE:figures/full_fig_p004_2.png] view at source ↗
Figure 3
Figure 3. Figure 3: An 8CX128R SRAM core slice, including the layout of 8x8 6T bitcells [PITH_FULL_IMAGE:figures/full_fig_p005_3.png] view at source ↗
Figure 4
Figure 4. Figure 4: Simulations of eight read operations for different 8-bit values stored [PITH_FULL_IMAGE:figures/full_fig_p005_4.png] view at source ↗
Figure 5
Figure 5. Figure 5: Simulation results of SC multiplication using the bitline computing [PITH_FULL_IMAGE:figures/full_fig_p005_5.png] view at source ↗
read the original abstract

Nowadays, we are witnessing an Artificial Intelligence revolution that dominates the technology landscape in various application domains, such as healthcare, robotics, automotive, security, and defense. Massive-scale AI models, which mimic the human brain's functionality, typically feature millions and even billions of parameters through data-intensive matrix multiplication tasks. While conventional Von-Neumann architectures struggle with the memory wall and the end of Moore's Law, these AI applications are migrating rapidly towards the edge, such as in robotics and unmanned aerial vehicles for surveillance, thereby adding more constraints to the hardware budget of AI architectures at the edge. Although in-memory computing has been proposed as a promising solution for the memory wall, both analog and digital in-memory computing architectures suffer from substantial degradation of the proposed benefits due to various design limitations. We propose a new digital in-memory stochastic computing architecture, DISCA, utilizing a compressed version of the quasi-stochastic Bent-Pyramid data format. DISCA inherits the same computational simplicity of analog computing, while preserving the same scalability, productivity, and reliability of digital systems. Post-layout modeling results of DISCA show an energy efficiency of 3.59TOPS/W per bit at 500 MHz using a commercial 180 nm CMOS technology. Therefore, DISCA significantly improves the energy efficiency for matrix multiplication workloads by orders of magnitude if scaled and compared to its counterpart architectures.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

2 major / 2 minor

Summary. The manuscript introduces DISCA, a digital in-memory stochastic computing architecture that uses a compressed Bent-Pyramid format for quasi-stochastic data representation. It targets matrix-multiplication workloads in edge AI applications and reports an energy efficiency of 3.59 TOPS/W per bit at 500 MHz in a commercial 180 nm CMOS process, obtained via post-layout modeling. The authors claim that this yields orders-of-magnitude efficiency gains relative to counterpart in-memory architectures when scaled.

Significance. If the post-layout energy figures prove predictive of silicon behavior and the compressed Bent-Pyramid representation maintains acceptable numerical accuracy for AI inference without prohibitive increases in bit-stream length, the architecture would offer a digitally reliable alternative to analog in-memory computing while retaining computational simplicity. The work addresses the memory wall in edge AI but currently lacks direct empirical support for either the performance prediction or the accuracy claim.

major comments (2)
  1. [Abstract] Abstract: The central efficiency claim of 3.59 TOPS/W per bit rests exclusively on post-layout modeling results; the manuscript provides neither fabricated silicon measurements, measured power/accuracy data on real AI workloads, nor error bars, leaving the 'orders of magnitude' improvement claim without direct empirical grounding.
  2. [Abstract] The manuscript does not quantify how compression in the Bent-Pyramid format affects stochastic correlation or required bit-stream length, nor does it compare matrix-multiplication accuracy against fixed-point or other in-memory baselines in the same technology node; without this analysis the claim that accuracy remains sufficient for AI tasks cannot be evaluated.
minor comments (2)
  1. Clarify the exact definition and compression algorithm for the Bent-Pyramid format, including any pseudocode or equations that define the mapping from binary values to stochastic streams.
  2. Provide a table comparing area, power, and latency against at least two published digital and analog in-memory designs in comparable process nodes.

Simulated Author's Rebuttal

2 responses · 1 unresolved

We thank the referee for the constructive comments. We address each major point below and clarify the scope of our post-layout results while strengthening the manuscript with additional analysis where feasible.

read point-by-point responses

  1. Referee: [Abstract] Abstract: The central efficiency claim of 3.59 TOPS/W per bit rests exclusively on post-layout modeling results; the manuscript provides neither fabricated silicon measurements, measured power/accuracy data on real AI workloads, nor error bars, leaving the 'orders of magnitude' improvement claim without direct empirical grounding.

    Authors: We acknowledge that all reported efficiency numbers derive from post-layout simulations rather than silicon measurements. This approach is standard for architectural proposals prior to tape-out. In the revision we have added error bars obtained from Monte Carlo process-variation simulations and expanded the power-breakdown discussion. We have also revised the abstract to explicitly state that the efficiency and scaling claims rest on post-layout modeling and published comparisons to other 180 nm designs. Direct measured silicon data cannot be supplied at present because the circuit has not been fabricated. revision: partial

  2. Referee: [Abstract] The manuscript does not quantify how compression in the Bent-Pyramid format affects stochastic correlation or required bit-stream length, nor does it compare matrix-multiplication accuracy against fixed-point or other in-memory baselines in the same technology node; without this analysis the claim that accuracy remains sufficient for AI tasks cannot be evaluated.

    Authors: We agree that a quantitative treatment of compression effects was missing. The revised manuscript now includes a dedicated subsection that measures the increase in bit-stream length and the change in stochastic correlation caused by the compressed Bent-Pyramid encoding. It also reports matrix-multiplication accuracy for representative edge-AI workloads and compares these results against fixed-point implementations synthesized in the identical 180 nm node, confirming that accuracy remains within acceptable limits for inference. revision: yes

standing simulated objections not resolved
  • Fabricated silicon measurements and measured power/accuracy data on real AI workloads, because no physical prototype has been taped out.

Circularity Check

0 steps flagged

No circularity in derivation chain; efficiency from independent post-layout modeling

full rationale

The paper derives its central energy-efficiency figure directly from post-layout simulation results in a commercial 180 nm CMOS process at 500 MHz. This modeling outcome is presented as an empirical measurement rather than a fitted parameter or self-referential definition. The subsequent claim of orders-of-magnitude improvement upon scaling is an extrapolation based on comparison to external counterpart architectures, not a quantity forced by the paper's own inputs or equations. No self-citations are invoked to justify load-bearing premises, no uniqueness theorems are imported from prior author work, and the compressed Bent-Pyramid format is introduced as a proposed representation without reducing to tautological redefinition. The derivation chain therefore remains self-contained against external benchmarks and does not collapse by construction.

Axiom & Free-Parameter Ledger

0 free parameters · 0 axioms · 1 invented entities

The proposal rests on standard CMOS modeling assumptions and the validity of the new compressed stochastic format; no explicit free parameters or invented physical entities are stated in the abstract.

invented entities (1)
  • Compressed Bent-Pyramid format no independent evidence
    purpose: Enable efficient stochastic representation for digital in-memory matrix multiplication
    Introduced as the core data format innovation in DISCA.

pith-pipeline@v0.9.0 · 5561 in / 1163 out tokens · 25353 ms · 2026-05-17T20:20:09.038951+00:00 · methodology

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