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arxiv: 2512.01683 · v3 · submitted 2025-12-01 · 📡 eess.SY · cs.SY

A Modified Boost Converter Topology for Dynamic Characterization of Hot Carrier and Trap Generation in GaN HEMTs

Moshe Azoulay , Gilad Orr , Gady Golan This is my paper

Pith reviewed 2026-05-17 02:49 UTC · model grok-4.3

classification 📡 eess.SY cs.SY
keywords GaN HEMThot carrier degradationtrap generationboost converterreliability modelR_DS(on) driftMTOL modelphonon scattering
0
0 comments X

The pith

A modified boost converter stresses GaN HEMTs at high duty cycle to measure logarithmic R_DS(on) rise and validate phonon scattering energies.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper presents a circuit-based method to accelerate and characterize hot carrier and trap generation in GaN power transistors. It uses a modified boost converter operating at 70 percent duty cycle to apply maximum rated voltage and current with low input power, then tracks the resulting increase in on-resistance over time. The measurements match the logarithmic degradation trend predicted by the EPC Phase 12 model and produce longitudinal optical phonon energies that align with prior theory when tested at 70 V and 100 V. A sympathetic reader would care because this setup offers a practical way to extract reliability parameters for the MTOL model without needing large power supplies or risking immediate device failure.

Core claim

The modified boost converter applies constant 400 mA drain current at 0.7 duty cycle to an EPC 2038 GaN HEMT, producing a logarithmic rise in R_DS(on) that matches the EPC Phase 12 reliability model; stress tests at 70 V and 100 V further yield ħω_LO values that agree with existing theoretical and experimental data, thereby confirming the circuit as a tool for determining MTOL reliability factors through controlled hot carrier and trap generation.

What carries the argument

The modified boost converter topology that delivers high-duty-cycle stress at rated voltage and current while keeping input power low.

If this is right

  • Device lifetime under varying voltage and current can be predicted from short accelerated tests using the same logarithmic model.
  • The MTOL reliability framework gains an experimental route to extract phonon-scattering parameters directly from packaged power transistors.
  • Power-electronics designers can qualify GaN HEMTs for specific operating points without full-scale high-power burn-in equipment.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • The same converter topology could be adapted to study other wide-bandgap devices such as SiC MOSFETs by changing only the duty cycle and voltage set points.
  • If the logarithmic trend holds across more device generations, manufacturers could publish standardized degradation curves derived from this low-cost test rather than proprietary high-power rigs.
  • Circuit designers might incorporate the measured ħω_LO dependence into real-time temperature and bias monitors to extend safe operating area margins.

Load-bearing premise

The high-duty-cycle stress inside the converter produces the same hot-carrier and trap-generation physics that occur in normal circuit operation without adding new failure modes or measurement errors from the test setup itself.

What would settle it

An independent long-term stress test on the same GaN device under normal switching conditions shows a linear rather than logarithmic R_DS(on) increase or extracts ħω_LO values outside the accepted theoretical range.

Figures

Figures reproduced from arXiv: 2512.01683 by Gady Golan, Gilad Orr, Moshe Azoulay.

Figure 1
Figure 1. Figure 1: (top) simplified representation of a switching mode power converter [PITH_FULL_IMAGE:figures/full_fig_p002_1.png] view at source ↗
Figure 3
Figure 3. Figure 3: illustrates the circuit action during the initial high period of the high frequency square wave applied to the GaN gate at start up. During this time GaN conducts, placing a short circuit from the right-hand side of L1 to the negative input supply terminal. Therefore a current flows between the positive and negative supply terminals through L1, which stores energy in its magnetic field. There is virtually … view at source ↗
Figure 4
Figure 4. Figure 4: Current Path with GaN Off GaN on periods after the initial start-up. Each time the GaN conducts, the cathode of D1 is more positive than its anode, due to the charge on C1. D1 is therefore turned off so the output of the circuit is isolated from the input, however the load continues to be supplied with Vin + VL from the charge on C1. Although the charge C1 drains away through the load during this period, C… view at source ↗
Figure 5
Figure 5. Figure 5: Current Path with GaN On 1) Boost convertor based on the EPC 2038 GaN transistor: The boost converter that we are showing in this paper is based on GaN n-channel transistor (EPC 2038) which used as switch, similar to the traditional Boost converter circuit with one main difference: the output is connected to a high-voltage supply instead of a regular load ( [PITH_FULL_IMAGE:figures/full_fig_p003_5.png] view at source ↗
Figure 6
Figure 6. Figure 6: Electrical diagram of Boost Converter circuit [PITH_FULL_IMAGE:figures/full_fig_p004_6.png] view at source ↗
Figure 7
Figure 7. Figure 7: GaN Based boost converter assembled board [PITH_FULL_IMAGE:figures/full_fig_p004_7.png] view at source ↗
Figure 9
Figure 9. Figure 9: Simulation result which presents the current versus time, the peak [PITH_FULL_IMAGE:figures/full_fig_p004_9.png] view at source ↗
Figure 10
Figure 10. Figure 10: Schematic of degradation mechanisms in AlGaN/GaN HEMTs [PITH_FULL_IMAGE:figures/full_fig_p005_10.png] view at source ↗
Figure 11
Figure 11. Figure 11: RDS(on) versus time voltage 40v 0 10 20 30 40 50 1 1.05 1.1 1.15 1.2 1.25 1.3 Time [Hs] RDS, Dynamic [Norm] [PITH_FULL_IMAGE:figures/full_fig_p006_11.png] view at source ↗
Figure 14
Figure 14. Figure 14: RDS(on) on versus time voltage 70v 3) Test with 100V stress, 400mA: This test was performed with a constant drain current of 400 mA and constant output voltage of 100v ,Vmax reached 110 v ; below in [PITH_FULL_IMAGE:figures/full_fig_p006_14.png] view at source ↗
Figure 15
Figure 15. Figure 15: Normalized RDS(on) versus time voltage 70v 0 0.5 1 1.5 2 3.7 3.75 3.8 3.85 3.9 3.95 4 RDS, Dynamic [Ω] Time [log(H)] [PITH_FULL_IMAGE:figures/full_fig_p007_15.png] view at source ↗
Figure 18
Figure 18. Figure 18: Normalized RDS(on) versus time voltage 100v effect in eGaN FETs from the basic physics of hot carrier scattering into surface traps: ∆R R = a+b log  1 + exp  VDS − VFD α  √ T exp  ℏωLO kT  Independent Variables: VDS = Drain voltage (V) T = Device temperature (K) t = Time (min) Parameters: a = 0.00 (unitless) b = 2.0E − 5 (E−1/2 ) ℏωLO = 92 meV VFD= 100V (appropriate for Gen5 100V products only) a = … view at source ↗
Figure 19
Figure 19. Figure 19: RDS(on) versus log time voltage 100v parameters. The values of the parameters shown in Table I are appropriate for an EPC2038 or other 100 V, 5’th Generation, FETs listed in Appendix B. Natural log (base e) was used for fitting. While the general form of this equation applies to all eGaN FETs. Our next goal is to confirm the equation that the EPC has developed for RDS(on) changes by using our presented me… view at source ↗
read the original abstract

Modern microelectronic systems require long term operational stability, necessitating precise reliability models to predict device lifecycles and identify governing failure mechanisms. This is particularly critical for high power GaN High-Electron-Mobility Transistors (HEMTs), where reliability research has historically trailed behind low power digital counterparts. This study introduces a novel application of a modified boost converter circuit designed to investigate GaN failure mechanisms, specifically targeting the determination of reliability factors for the MTOL model. By utilizing a high duty cycle, the circuit stresses the device at maximum rated voltages and currents with minimal input requirements, accelerating hot carrier and trap generation without immediate detrimental failure. Experimental validation was conducted using an EPC 2038 GaN transistor under a constant drain current of 400 mA and a duty cycle of 0.7. The results confirmed that the increase in Drain-Source on-resistance ($R_{DS(on)}$) follows a logarithmic trend over time, consistent with the EPC Phase 12 reliability model. While initial tests at 40V did not successfully validate the longitudinal optical phonon scattering energy ($\hbar\omega_{LO}$), but were reasonably acceptable, subsequent stress tests at 70V and 100V yielded $\hbar\omega_{LO}$ values that were successfully validated against existing theoretical and experimental data. This methodology provides a robust framework for predicting performance and lifetime across varying operational parameters in modern power electronics.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

2 major / 2 minor

Summary. The paper proposes a modified boost converter topology to dynamically stress GaN HEMTs and characterize hot-carrier and trap generation for reliability modeling (MTOL). Using an EPC 2038 device stressed at constant 400 mA drain current and 0.7 duty cycle, the authors report a logarithmic rise in R_DS(on) consistent with the EPC Phase 12 model; ħω_LO values extracted at 70 V and 100 V are stated to match existing theoretical and experimental data, while the 40 V test yielded only partial success.

Significance. If the measured degradation can be shown to arise solely from intrinsic hot-carrier and trap mechanisms without confounding contributions from the switching circuit, the approach would offer a practical, low-input-power method for accelerated reliability testing of power GaN devices. The reported consistency with an established model is a positive indicator, but the absence of raw data, error bars, extraction details, and controls for circuit artifacts currently limits the strength of this contribution.

major comments (2)
  1. [Abstract] Abstract (experimental validation paragraph): the claim that ħω_LO values at 70 V and 100 V 'were successfully validated' is not supported by any description of the extraction procedure, fitting method, uncertainty quantification, or comparison plots; without these the validation cannot be assessed as independent of the reference data.
  2. [Abstract] Abstract and circuit description: the high-duty-cycle (0.7) boost-converter stress necessarily includes hard-switching transients, inductor ripple, and possible drain voltage overshoot, yet no section quantifies or subtracts these circuit-specific contributions (e.g., via DC-bias control experiments or in-situ waveform monitoring). This leaves open the possibility that part of the observed R_DS(on) rise is an artifact rather than intrinsic hot-carrier physics, directly undermining the central claim that the topology enables clean dynamic characterization.
minor comments (2)
  1. [Abstract] Abstract: the phrasing 'did not successfully validate ... but were reasonably acceptable' is ambiguous and should be replaced with a clear statement of the quantitative criteria used for validation.
  2. [Abstract] Abstract: no error bars, number of devices tested, or statistical analysis of the R_DS(on) time series are mentioned; these should be added to allow readers to judge the reliability of the logarithmic trend.

Simulated Author's Rebuttal

2 responses · 0 unresolved

We thank the referee for the constructive comments on our manuscript. We address each major point below and outline the revisions we will make to strengthen the presentation of the experimental validation and circuit considerations.

read point-by-point responses

  1. Referee: [Abstract] Abstract (experimental validation paragraph): the claim that ħω_LO values at 70 V and 100 V 'were successfully validated' is not supported by any description of the extraction procedure, fitting method, uncertainty quantification, or comparison plots; without these the validation cannot be assessed as independent of the reference data.

    Authors: We agree that the abstract lacks sufficient detail on the ħω_LO extraction. The values were obtained by fitting the measured logarithmic R_DS(on) rise to the MTOL model form used in the EPC Phase 12 framework, with the slope parameter directly yielding the phonon energy; these were then compared numerically to the accepted 0.09 eV theoretical value and prior experimental reports. Multiple devices were measured to estimate variability. We will revise the abstract to include a concise description of the fitting procedure and uncertainty, and we will add a dedicated figure showing the data, fits, and literature comparison in the revised manuscript. revision: yes

  2. Referee: [Abstract] Abstract and circuit description: the high-duty-cycle (0.7) boost-converter stress necessarily includes hard-switching transients, inductor ripple, and possible drain voltage overshoot, yet no section quantifies or subtracts these circuit-specific contributions (e.g., via DC-bias control experiments or in-situ waveform monitoring). This leaves open the possibility that part of the observed R_DS(on) rise is an artifact rather than intrinsic hot-carrier physics, directly undermining the central claim that the topology enables clean dynamic characterization.

    Authors: The concern about possible circuit artifacts is valid and merits explicit discussion. The observed degradation exhibits a clean logarithmic time dependence that matches the established hot-carrier model across the 70 V and 100 V conditions, which is inconsistent with typical transient-induced mechanisms that produce different kinetics. Inductor selection and layout were chosen to limit ripple, and voltage overshoot was monitored during setup. We will expand the circuit description section to include measured waveform captures, estimated ripple and overshoot values from simulation and experiment, and a brief analysis arguing that these do not dominate the long-term logarithmic trend. Full DC-bias-only control experiments lie outside the present scope but will be noted as recommended future work. revision: partial

Circularity Check

0 steps flagged

No circularity: experimental measurements compared to external models and data

full rationale

The manuscript describes an experimental apparatus (modified boost converter) that applies high-duty-cycle stress to an EPC 2038 GaN HEMT and records the time evolution of R_DS(on). The observed logarithmic rise is reported as consistent with the pre-existing EPC Phase 12 model, and ħω_LO values extracted at 70 V and 100 V are stated to match independent theoretical and experimental literature. No equations, fitted parameters, or self-citations are shown that would make the reported trends or extracted energies equivalent to the input data by construction. The central claims rest on direct measurement and external comparison rather than on any self-referential derivation chain.

Axiom & Free-Parameter Ledger

0 free parameters · 1 axioms · 0 invented entities

The central claim rests on the MTOL reliability model and the EPC Phase 12 model as external benchmarks; experimental parameters such as duty cycle and current are chosen rather than fitted, and no new entities are postulated.

axioms (1)
  • domain assumption The MTOL model provides the correct framework for extracting reliability factors from hot-carrier and trap data in GaN HEMTs
    The study targets determination of reliability factors for the MTOL model and compares results to the EPC Phase 12 model.

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Lean theorems connected to this paper

Citations machine-checked in the Pith Canon. Every link opens the source theorem in the public Lean library.

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    Relation between the paper passage and the cited Recognition theorem.

    The results confirmed that the increase in Drain-Source on-resistance (R_DS(on)) follows a logarithmic trend over time, consistent with the EPC Phase 12 reliability model... ħω_LO values that were successfully validated against existing theoretical and experimental data.

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Reference graph

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